Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13088885

1

T1

493

T2

11653

T4

25731

full_word

52435396

1

T1

4985

T2

115515

T3

43008

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	65523971	1			T1	5478		T2	127168		T3	43008
auto[TlIntgErrCmd]	103	1			T26	8		T27	4		T28	6
auto[TlIntgErrData]	106	1			T26	5		T27	7		T28	10
auto[TlIntgErrBoth]	101	1			T26	7		T27	9		T28	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29957088

1

T1

2710

T2

63549

T3

21504

auto[1]

35567193

1

T1

2768

T2

63619

T3

21504

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6287921	1			T1	249		T2	5854		T4	9832
auto[TlIntgErrNone]	partial	auto[1]	6800676	1			T1	244		T2	5799		T4	15899
auto[TlIntgErrNone]	full_word	auto[0]	23669026	1			T1	2461		T2	57695		T3	21504
auto[TlIntgErrNone]	full_word	auto[1]	28766348	1			T1	2524		T2	57820		T3	21504
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T26	3		T28	2		T46	2
auto[TlIntgErrCmd]	partial	auto[1]	57	1			T26	4		T27	4		T28	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T47	1		T100	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T26	1		T47	1		T51	2
auto[TlIntgErrData]	partial	auto[0]	57	1			T26	2		T27	5		T28	7
auto[TlIntgErrData]	partial	auto[1]	39	1			T26	3		T27	2		T28	3
auto[TlIntgErrData]	full_word	auto[0]	1	1			T102	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	9	1			T48	1		T52	2		T100	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T26	3		T27	6		T28	1
auto[TlIntgErrBoth]	partial	auto[1]	55	1			T26	4		T27	3		T28	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T50	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T46	1		T100	1		T103	1