Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	489577	1			T2	7037		T8	525		T12	376
auto[1]	10059603	1			T2	1657		T4	14842		T5	5050
auto[2]	407571	1			T2	6311		T8	313		T12	379
auto[3]	9985908	1			T2	989		T4	14798		T5	4947

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13533578	1			T2	12496		T4	24794		T5	9997
auto[1]	2015876	1			T2	1752		T4	2235		T7	809
auto[2]	2015856	1			T2	1553		T4	2403		T7	800
auto[3]	3377349	1			T2	193		T4	208		T7	79

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7944536

1

T2

15972

T4

29616

T5

9989

auto[1]

12998123

1

T2

22

T4

24

T5

8

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	195661	1			T2	5736		T8	435		T12	313
auto[0]	auto[0]	auto[1]	20014	1			T2	627		T8	42		T12	28
auto[0]	auto[0]	auto[2]	20005	1			T2	607		T8	41		T12	35
auto[0]	auto[0]	auto[3]	6312	1			T2	57		T8	7		T13	117
auto[0]	auto[1]	auto[0]	3055136	1			T2	954		T4	12413		T5	5046
auto[0]	auto[1]	auto[1]	321910	1			T2	563		T4	1036		T7	408
auto[0]	auto[1]	auto[2]	310958	1			T2	82		T4	1280		T7	399
auto[0]	auto[1]	auto[3]	73838	1			T2	56		T4	99		T7	37
auto[0]	auto[2]	auto[0]	167656	1			T2	5327		T8	235		T12	324
auto[0]	auto[2]	auto[1]	17313	1			T2	518		T8	27		T12	32
auto[0]	auto[2]	auto[2]	16619	1			T2	422		T8	44		T12	21
auto[0]	auto[2]	auto[3]	5021	1			T2	37		T8	7		T12	2
auto[0]	auto[3]	auto[0]	3029066	1			T2	462		T4	12360		T5	4943
auto[0]	auto[3]	auto[1]	307996	1			T2	41		T4	1198		T7	399
auto[0]	auto[3]	auto[2]	319880	1			T2	440		T4	1121		T7	401
auto[0]	auto[3]	auto[3]	77151	1			T2	43		T4	109		T7	42
auto[1]	auto[0]	auto[0]	8348	1			T2	8		T13	18		T106	5
auto[1]	auto[0]	auto[1]	36821	1			T2	1		T13	1		T106	1
auto[1]	auto[0]	auto[2]	36954	1			T2	1		T106	2		T24	1
auto[1]	auto[0]	auto[3]	165462	1			T93	10955		T107	1		T97	10705
auto[1]	auto[1]	auto[0]	3537212	1			T2	1		T4	12		T5	4
auto[1]	auto[1]	auto[1]	648910	1			T2	1		T4	1		T9	1
auto[1]	auto[1]	auto[2]	639666	1			T4	1		T13	1		T70	2
auto[1]	auto[1]	auto[3]	1471973	1			T90	650		T91	629		T92	966
auto[1]	auto[2]	auto[0]	6811	1			T2	6		T13	18		T106	5
auto[1]	auto[2]	auto[1]	30326	1			T2	1		T13	3		T93	2248
auto[1]	auto[2]	auto[2]	29975	1			T13	1		T93	2052		T97	1650
auto[1]	auto[2]	auto[3]	133850	1			T93	9320		T107	1		T97	7111
auto[1]	auto[3]	auto[0]	3533688	1			T2	2		T4	9		T5	4
auto[1]	auto[3]	auto[1]	632586	1			T7	2		T13	1		T23	2
auto[1]	auto[3]	auto[2]	641799	1			T2	1		T4	1		T14	4
auto[1]	auto[3]	auto[3]	1443742	1			T90	658		T91	634		T15	1