Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	313623378	6585	0	0
ctrl_regwen_rd_A	313623378	1636	0	0
exec_rd_A	313623378	1581	0	0
exec_regwen_rd_A	313623378	1540	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313623378	6585	0	0
T26	13733	2	0	0
T28	15585	2	0	0
T29	7238	119	0	0
T30	3859	509	0	0
T45	4674	149	0	0
T46	17767	4	0	0
T47	16174	3	0	0
T48	11245	2	0	0
T49	14631	2	0	0
T50	8551	1	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313623378	1636	0	0
T45	4674	36	0	0
T46	17767	79	0	0
T47	16174	43	0	0
T51	15123	41	0	0
T58	17497	493	0	0
T59	1370	6	0	0
T83	1612	1	0	0
T85	2570	22	0	0
T86	1552	3	0	0
T98	11234	50	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313623378	1581	0	0
T45	4674	45	0	0
T46	17767	83	0	0
T47	16174	40	0	0
T51	15123	18	0	0
T58	17497	486	0	0
T83	1612	43	0	0
T85	2570	10	0	0
T86	1552	6	0	0
T98	11234	17	0	0
T99	1550	17	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313623378	1540	0	0
T45	4674	38	0	0
T46	17767	68	0	0
T47	16174	18	0	0
T51	15123	35	0	0
T58	17497	428	0	0
T59	1370	35	0	0
T83	1612	41	0	0
T85	2570	23	0	0
T86	1552	19	0	0
T98	11234	38	0	0