Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13341981

1

T1

923

T2

911

T3

20866

full_word

52531616

1

T1

57

T2

56

T3

210696

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	65873277	1			T1	980		T2	967		T3	231562
auto[TlIntgErrCmd]	90	1			T26	3		T27	5		T28	5
auto[TlIntgErrData]	127	1			T26	2		T27	6		T28	10
auto[TlIntgErrBoth]	103	1			T26	5		T27	9		T28	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30150635

1

T1

378

T2

372

T3

86705

auto[1]

35722962

1

T1

602

T2

595

T3

144857

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6413611	1			T1	375		T2	371		T3	7753
auto[TlIntgErrNone]	partial	auto[1]	6928080	1			T1	548		T2	540		T3	13113
auto[TlIntgErrNone]	full_word	auto[0]	23736874	1			T1	3		T2	1		T3	78952
auto[TlIntgErrNone]	full_word	auto[1]	28794712	1			T1	54		T2	55		T3	131744
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T26	1		T27	2		T28	2
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T26	2		T27	2		T28	3
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T45	1		T93	1		T92	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T27	1		T93	1		T92	1
auto[TlIntgErrData]	partial	auto[0]	59	1			T26	2		T27	3		T28	6
auto[TlIntgErrData]	partial	auto[1]	56	1			T27	2		T28	3		T50	1
auto[TlIntgErrData]	full_word	auto[0]	6	1			T27	1		T28	1		T44	2
auto[TlIntgErrData]	full_word	auto[1]	6	1			T96	2		T94	2		T91	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T26	1		T27	4		T28	3
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T26	4		T27	4		T28	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T55	1		T47	1		T90	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T27	1		T53	1		T91	2