Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	693276	1			T4	3327		T12	47		T13	605
auto[1]	9855054	1			T1	359		T2	357		T3	524
auto[2]	577527	1			T4	2221		T12	47		T13	525
auto[3]	9749884	1			T1	554		T2	571		T3	509

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13448085	1			T1	2		T2	5		T3	708
auto[1]	2003359	1			T1	55		T2	51		T3	155
auto[2]	1999273	1			T1	79		T2	92		T3	154
auto[3]	3425024	1			T1	777		T2	780		T3	16

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7674804

1

T1

912

T2

927

T3

1033

auto[1]

13200937

1

T1

1

T2

1

T10

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	275585	1			T4	2812		T13	511		T6	24
auto[0]	auto[0]	auto[1]	27988	1			T4	232		T13	46		T6	4
auto[0]	auto[0]	auto[2]	27973	1			T4	257		T13	43		T6	1
auto[0]	auto[0]	auto[3]	7059	1			T4	22		T12	46		T13	5
auto[0]	auto[1]	auto[0]	2891375	1			T3	353		T10	3		T4	1831
auto[0]	auto[1]	auto[1]	303929	1			T1	3		T2	1		T3	117
auto[0]	auto[1]	auto[2]	289375	1			T1	34		T2	43		T3	46
auto[0]	auto[1]	auto[3]	64243	1			T1	322		T2	312		T3	8
auto[0]	auto[2]	auto[0]	232984	1			T4	1698		T13	449		T6	29
auto[0]	auto[2]	auto[1]	23918	1			T4	174		T12	4		T13	45
auto[0]	auto[2]	auto[2]	22410	1			T4	306		T13	26		T6	3
auto[0]	auto[2]	auto[3]	5448	1			T4	41		T12	43		T13	4
auto[0]	auto[3]	auto[0]	2850077	1			T1	2		T2	5		T3	355
auto[0]	auto[3]	auto[1]	284873	1			T1	52		T2	50		T3	38
auto[0]	auto[3]	auto[2]	299784	1			T1	45		T2	49		T3	108
auto[0]	auto[3]	auto[3]	67783	1			T1	454		T2	467		T3	8
auto[1]	auto[0]	auto[0]	12028	1			T4	4		T7	5		T8	14
auto[1]	auto[0]	auto[1]	52760	1			T8	1		T98	1		T106	2361
auto[1]	auto[0]	auto[2]	52579	1			T7	1		T106	2340		T104	1
auto[1]	auto[0]	auto[3]	237304	1			T12	1		T106	10752		T70	1
auto[1]	auto[1]	auto[0]	3590149	1			T4	1		T5	100711		T11	49
auto[1]	auto[1]	auto[1]	646306	1			T5	10224		T11	7		T14	4
auto[1]	auto[1]	auto[2]	625838	1			T5	10128		T11	9		T14	7
auto[1]	auto[1]	auto[3]	1443839	1			T2	1		T5	1017		T11	1
auto[1]	auto[2]	auto[0]	10328	1			T4	1		T13	1		T7	3
auto[1]	auto[2]	auto[1]	45025	1			T106	2163		T107	5461		T102	1
auto[1]	auto[2]	auto[2]	43164	1			T4	1		T8	2		T106	1577
auto[1]	auto[2]	auto[3]	194250	1			T8	1		T106	7076		T107	18229
auto[1]	auto[3]	auto[0]	3585559	1			T5	101011		T11	63		T14	35
auto[1]	auto[3]	auto[1]	618560	1			T10	1		T5	10051		T11	5
auto[1]	auto[3]	auto[2]	638150	1			T5	10047		T11	5		T14	6
auto[1]	auto[3]	auto[3]	1405098	1			T1	1		T5	1002		T37	2