Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	322133777	7811	0	0
ctrl_regwen_rd_A	322133777	1235	0	0
exec_rd_A	322133777	1426	0	0
exec_regwen_rd_A	322133777	1352	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322133777	7811	0	0
T26	5956	1	0	0
T27	17453	1	0	0
T28	18498	3	0	0
T29	12357	621	0	0
T30	10484	288	0	0
T42	12895	522	0	0
T43	2830	263	0	0
T44	11580	2	0	0
T45	14871	2	0	0
T46	2592	355	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322133777	1235	0	0
T29	12357	64	0	0
T45	14871	49	0	0
T51	12300	39	0	0
T55	8439	23	0	0
T58	1128	2	0	0
T59	17043	405	0	0
T63	40579	21	0	0
T64	19991	29	0	0
T79	2292	44	0	0
T81	1166	3	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322133777	1426	0	0
T29	12357	74	0	0
T45	14871	30	0	0
T51	12300	23	0	0
T55	8439	21	0	0
T58	1128	2	0	0
T59	17043	431	0	0
T63	40579	34	0	0
T64	19991	61	0	0
T79	2292	40	0	0
T81	1166	5	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	322133777	1352	0	0
T29	12357	42	0	0
T45	14871	45	0	0
T55	8439	28	0	0
T58	1128	3	0	0
T59	17043	461	0	0
T61	1056	1	0	0
T63	40579	50	0	0
T64	19991	31	0	0
T79	2292	87	0	0
T81	1166	3	0	0