Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13987339	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

58414273

1

T1

38912

T2

58

T3

31079

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	36153282	1			T1	19456		T2	347		T3	17120
values[0x0]	16722544	1			T1	9772		T2	191		T3	8238
values[0x1]	19525786	1			T1	9684		T2	424		T3	8897

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6968629	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

65432983

1

T1

38912

T2

441

T3

32665

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	301725	1			T2	4		T3	114		T7	37
valid_sources[0x01]	254933	1			T2	4		T3	129		T7	43
valid_sources[0x02]	264069	1			T2	3		T3	120		T7	42
valid_sources[0x03]	279317	1			T2	9		T3	150		T7	44
valid_sources[0x04]	297017	1			T2	4		T3	118		T7	43
valid_sources[0x05]	435044	1			T2	1		T3	131		T7	37
valid_sources[0x06]	283330	1			T2	5		T3	135		T7	41
valid_sources[0x07]	279854	1			T2	2		T3	110		T7	52
valid_sources[0x08]	319191	1			T2	6		T3	129		T7	43
valid_sources[0x09]	281396	1			T2	2		T3	135		T4	54
valid_sources[0x0a]	298049	1			T2	6		T3	105		T7	38
valid_sources[0x0b]	282135	1			T2	3		T3	155		T4	71
valid_sources[0x0c]	337369	1			T2	2		T3	180		T7	37
valid_sources[0x0d]	313129	1			T1	38912		T2	11		T3	120
valid_sources[0x0e]	330356	1			T2	8		T3	164		T7	44
valid_sources[0x0f]	358576	1			T2	4		T3	181		T4	33
valid_sources[0x10]	335349	1			T2	3		T3	149		T4	84
valid_sources[0x11]	332875	1			T2	5		T3	149		T4	27
valid_sources[0x12]	332174	1			T3	107		T7	35		T8	1029
valid_sources[0x13]	262525	1			T2	3		T3	150		T7	42
valid_sources[0x14]	410092	1			T2	6		T3	171		T7	43
valid_sources[0x15]	285805	1			T2	5		T3	94		T7	42
valid_sources[0x16]	255301	1			T2	5		T3	108		T7	47
valid_sources[0x17]	288322	1			T2	1		T3	86		T7	35
valid_sources[0x18]	257408	1			T2	4		T3	124		T7	34
valid_sources[0x19]	250915	1			T2	2		T3	135		T7	43
valid_sources[0x1a]	265692	1			T2	2		T3	151		T7	48
valid_sources[0x1b]	238941	1			T2	4		T3	163		T7	33
valid_sources[0x1c]	253935	1			T2	8		T3	106		T4	238
valid_sources[0x1d]	273195	1			T2	6		T3	129		T7	48
valid_sources[0x1e]	248494	1			T2	4		T3	131		T4	27
valid_sources[0x1f]	270927	1			T2	2		T3	100		T4	42
valid_sources[0x20]	253546	1			T2	1		T3	106		T7	25
valid_sources[0x21]	322266	1			T2	3		T3	125		T7	43
valid_sources[0x22]	292334	1			T2	3		T3	158		T7	42
valid_sources[0x23]	276262	1			T2	2		T3	137		T4	84
valid_sources[0x24]	246248	1			T2	3		T3	126		T7	39
valid_sources[0x25]	249286	1			T2	4		T3	106		T7	39
valid_sources[0x26]	311866	1			T2	6		T3	132		T7	28
valid_sources[0x27]	283540	1			T2	5		T3	174		T4	116
valid_sources[0x28]	262894	1			T2	5		T3	117		T7	31
valid_sources[0x29]	329947	1			T2	2		T3	83		T7	50
valid_sources[0x2a]	287862	1			T2	6		T3	147		T7	38
valid_sources[0x2b]	270075	1			T2	1		T3	164		T7	41
valid_sources[0x2c]	282689	1			T2	4		T3	163		T7	45
valid_sources[0x2d]	248033	1			T2	1		T3	83		T7	48
valid_sources[0x2e]	247844	1			T2	1		T3	116		T7	30
valid_sources[0x2f]	279580	1			T2	2		T3	125		T4	46
valid_sources[0x30]	252051	1			T2	2		T3	129		T7	46
valid_sources[0x31]	287339	1			T2	7		T3	137		T7	38
valid_sources[0x32]	272639	1			T2	4		T3	110		T7	55
valid_sources[0x33]	270137	1			T2	2		T3	121		T4	41
valid_sources[0x34]	255739	1			T2	2		T3	127		T7	31
valid_sources[0x35]	253639	1			T2	1		T3	151		T7	51
valid_sources[0x36]	273776	1			T2	2		T3	162		T7	41
valid_sources[0x37]	278942	1			T2	6		T3	137		T4	29
valid_sources[0x38]	264563	1			T2	4		T3	132		T7	39
valid_sources[0x39]	296069	1			T2	2		T3	123		T4	114
valid_sources[0x3a]	269012	1			T2	5		T3	137		T7	41
valid_sources[0x3b]	265589	1			T3	93		T7	43		T8	1025
valid_sources[0x3c]	307984	1			T2	2		T3	125		T4	96
valid_sources[0x3d]	283232	1			T2	7		T3	131		T7	29
valid_sources[0x3e]	272835	1			T2	4		T3	128		T7	43
valid_sources[0x3f]	245782	1			T3	102		T7	38		T8	1029
valid_sources[0x40]	265271	1			T2	1		T3	128		T7	35
valid_sources[0x41]	258548	1			T2	3		T3	137		T7	35
valid_sources[0x42]	293605	1			T3	142		T7	30		T8	1036
valid_sources[0x43]	280510	1			T2	6		T3	136		T4	161
valid_sources[0x44]	265004	1			T2	3		T3	156		T7	36
valid_sources[0x45]	266553	1			T2	3		T3	139		T7	33
valid_sources[0x46]	283530	1			T2	6		T3	164		T7	34
valid_sources[0x47]	285412	1			T3	164		T7	33		T8	1057
valid_sources[0x48]	274794	1			T2	5		T3	156		T7	53
valid_sources[0x49]	277187	1			T2	7		T3	136		T7	43
valid_sources[0x4a]	319834	1			T2	1		T3	161		T7	43
valid_sources[0x4b]	257358	1			T2	2		T3	168		T7	40
valid_sources[0x4c]	255313	1			T2	3		T3	115		T7	39
valid_sources[0x4d]	357194	1			T2	1		T3	119		T7	41
valid_sources[0x4e]	265839	1			T2	6		T3	128		T4	33
valid_sources[0x4f]	355735	1			T2	4		T3	110		T7	37
valid_sources[0x50]	323657	1			T2	4		T3	98		T7	41
valid_sources[0x51]	265702	1			T2	3		T3	188		T7	36
valid_sources[0x52]	243517	1			T2	3		T3	123		T7	38
valid_sources[0x53]	267156	1			T2	5		T3	90		T7	42
valid_sources[0x54]	244204	1			T2	2		T3	112		T7	39
valid_sources[0x55]	311582	1			T2	3		T3	156		T7	58
valid_sources[0x56]	272201	1			T2	3		T3	130		T4	37
valid_sources[0x57]	265715	1			T2	4		T3	131		T7	30
valid_sources[0x58]	326963	1			T2	5		T3	119		T7	30
valid_sources[0x59]	268689	1			T2	4		T3	176		T7	32
valid_sources[0x5a]	264717	1			T2	3		T3	174		T7	40
valid_sources[0x5b]	307504	1			T2	4		T3	147		T7	43
valid_sources[0x5c]	245626	1			T2	1		T3	149		T7	39
valid_sources[0x5d]	298535	1			T2	7		T3	147		T7	40
valid_sources[0x5e]	240065	1			T2	2		T3	147		T7	39
valid_sources[0x5f]	379178	1			T2	1		T3	118		T7	27
valid_sources[0x60]	245559	1			T2	5		T3	111		T7	41
valid_sources[0x61]	258486	1			T2	1		T3	146		T4	234
valid_sources[0x62]	239945	1			T2	2		T3	183		T7	43
valid_sources[0x63]	363106	1			T2	7		T3	98		T7	40
valid_sources[0x64]	255908	1			T2	5		T3	92		T7	42
valid_sources[0x65]	345591	1			T2	5		T3	175		T4	28
valid_sources[0x66]	284921	1			T2	1		T3	109		T4	143
valid_sources[0x67]	309141	1			T2	4		T3	164		T7	29
valid_sources[0x68]	284818	1			T2	8		T3	151		T7	52
valid_sources[0x69]	254455	1			T2	5		T3	109		T4	39
valid_sources[0x6a]	288182	1			T2	3		T3	138		T7	50
valid_sources[0x6b]	295570	1			T2	6		T3	98		T4	113
valid_sources[0x6c]	240676	1			T2	2		T3	145		T7	30
valid_sources[0x6d]	265462	1			T2	1		T3	132		T4	76
valid_sources[0x6e]	259050	1			T2	1		T3	182		T4	5
valid_sources[0x6f]	242455	1			T2	2		T3	138		T7	28
valid_sources[0x70]	252214	1			T2	4		T3	154		T7	45
valid_sources[0x71]	258159	1			T2	5		T3	153		T7	27
valid_sources[0x72]	267405	1			T2	3		T3	125		T7	30
valid_sources[0x73]	268783	1			T2	5		T3	111		T4	22
valid_sources[0x74]	281865	1			T2	5		T3	77		T7	36
valid_sources[0x75]	335258	1			T2	2		T3	106		T7	56
valid_sources[0x76]	239837	1			T2	3		T3	113		T7	37
valid_sources[0x77]	269405	1			T2	7		T3	122		T7	47
valid_sources[0x78]	298658	1			T2	4		T3	132		T7	21
valid_sources[0x79]	327503	1			T2	4		T3	172		T7	31
valid_sources[0x7a]	255936	1			T2	7		T3	156		T7	34
valid_sources[0x7b]	242212	1			T2	5		T3	136		T4	20
valid_sources[0x7c]	255666	1			T2	6		T3	152		T4	35
valid_sources[0x7d]	265560	1			T2	5		T3	96		T7	35
valid_sources[0x7e]	294090	1			T2	5		T3	134		T4	38
valid_sources[0x7f]	281677	1			T2	5		T3	170		T7	38
valid_sources[0x80]	253809	1			T2	2		T3	109		T4	162

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

29164432

1

T1

19456

T2

2

T3

15505

values[0x0]

all_enables

biggest_size

14624146

1

T1

9772

T2

29

T3

7762

values[0x1]

all_enables

biggest_size

14625695

1

T1

9684

T2

27

T3

7812

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2278578	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

18228

1

T1

4

T2

1

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2268339	1			T1	687		T2	124		T3	554
values[0x0]	14025	1			T1	11		T2	1		T3	7
values[0x1]	14442	1			T1	8		T3	3		T4	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1524758	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

772048

1

T1

248

T2

38

T3

181

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7728	1			T1	1		T4	11		T7	9
valid_sources[0x01]	18728	1			T1	3		T4	4		T7	5
valid_sources[0x02]	6388	1			T1	3		T7	5		T10	48
valid_sources[0x03]	30177	1			T1	1		T4	25		T7	10
valid_sources[0x04]	7788	1			T1	1		T4	19		T7	8
valid_sources[0x05]	6597	1			T1	1		T4	53		T7	1
valid_sources[0x06]	8219	1			T1	1		T7	8		T9	1
valid_sources[0x07]	9670	1			T1	2		T4	25		T7	12
valid_sources[0x08]	6510	1			T1	6		T4	13		T7	2
valid_sources[0x09]	11569	1			T1	2		T4	2		T7	2
valid_sources[0x0a]	6477	1			T1	1		T4	17		T7	1
valid_sources[0x0b]	7131	1			T1	2		T7	7		T10	74
valid_sources[0x0c]	7381	1			T4	3		T7	6		T8	28
valid_sources[0x0d]	6605	1			T1	1		T4	14		T7	3
valid_sources[0x0e]	18531	1			T1	3		T4	11		T7	13
valid_sources[0x0f]	6642	1			T4	12		T7	3		T8	35
valid_sources[0x10]	17668	1			T4	11		T7	3		T10	104
valid_sources[0x11]	8608	1			T4	1		T7	5		T8	69
valid_sources[0x12]	6668	1			T1	5		T4	16		T7	8
valid_sources[0x13]	6537	1			T1	1		T4	18		T7	10
valid_sources[0x14]	8454	1			T1	2		T4	28		T7	4
valid_sources[0x15]	7111	1			T1	5		T2	4		T4	5
valid_sources[0x16]	8986	1			T1	1		T4	3		T7	8
valid_sources[0x17]	10744	1			T1	5		T4	51		T7	2
valid_sources[0x18]	7889	1			T1	2		T4	8		T7	6
valid_sources[0x19]	6780	1			T1	2		T4	1		T7	4
valid_sources[0x1a]	17303	1			T1	1		T4	23		T7	12
valid_sources[0x1b]	9497	1			T1	5		T4	20		T10	102
valid_sources[0x1c]	14200	1			T1	7		T4	12		T7	1
valid_sources[0x1d]	7057	1			T1	5		T2	1		T4	11
valid_sources[0x1e]	7551	1			T1	3		T4	2		T7	2
valid_sources[0x1f]	6686	1			T1	3		T4	8		T7	6
valid_sources[0x20]	11132	1			T1	6		T4	3		T7	1
valid_sources[0x21]	7310	1			T1	2		T4	14		T7	1
valid_sources[0x22]	8956	1			T1	6		T7	4		T8	2
valid_sources[0x23]	8173	1			T1	5		T4	6		T7	1
valid_sources[0x24]	6774	1			T1	2		T4	13		T7	4
valid_sources[0x25]	8793	1			T1	1		T4	2		T7	5
valid_sources[0x26]	6252	1			T1	2		T4	14		T7	5
valid_sources[0x27]	6841	1			T1	3		T4	6		T8	19
valid_sources[0x28]	6932	1			T1	1		T4	21		T7	6
valid_sources[0x29]	8577	1			T1	3		T4	3		T7	2
valid_sources[0x2a]	8689	1			T1	1		T4	11		T7	3
valid_sources[0x2b]	7049	1			T1	3		T4	13		T7	6
valid_sources[0x2c]	10538	1			T1	10		T4	3		T7	8
valid_sources[0x2d]	7872	1			T1	1		T4	2		T7	13
valid_sources[0x2e]	15581	1			T4	6		T7	5		T9	5
valid_sources[0x2f]	18825	1			T1	7		T4	17		T9	5
valid_sources[0x30]	7006	1			T7	2		T9	4		T10	108
valid_sources[0x31]	26200	1			T1	3		T4	12		T7	4
valid_sources[0x32]	7541	1			T1	1		T4	1		T7	4
valid_sources[0x33]	6652	1			T4	31		T7	10		T8	70
valid_sources[0x34]	6603	1			T1	2		T4	31		T7	8
valid_sources[0x35]	7713	1			T1	5		T2	12		T4	11
valid_sources[0x36]	6557	1			T1	3		T4	3		T7	3
valid_sources[0x37]	14825	1			T1	4		T4	4		T7	1
valid_sources[0x38]	6433	1			T4	15		T7	5		T9	1
valid_sources[0x39]	6964	1			T1	3		T7	3		T8	4
valid_sources[0x3a]	6649	1			T1	1		T4	2		T7	1
valid_sources[0x3b]	7611	1			T4	22		T7	3		T8	47
valid_sources[0x3c]	8122	1			T1	4		T4	31		T7	4
valid_sources[0x3d]	8343	1			T4	8		T7	4		T9	9
valid_sources[0x3e]	9272	1			T1	4		T4	8		T7	13
valid_sources[0x3f]	6795	1			T1	2		T4	13		T7	1
valid_sources[0x40]	15034	1			T1	5		T4	1		T7	4
valid_sources[0x41]	14904	1			T4	10		T7	8		T8	130
valid_sources[0x42]	6962	1			T1	4		T4	18		T7	4
valid_sources[0x43]	6238	1			T1	2		T4	12		T7	9
valid_sources[0x44]	7013	1			T1	3		T2	13		T4	9
valid_sources[0x45]	6560	1			T1	1		T4	7		T7	5
valid_sources[0x46]	9360	1			T1	2		T4	23		T7	1
valid_sources[0x47]	6579	1			T1	2		T4	5		T8	13
valid_sources[0x48]	6908	1			T1	6		T4	36		T8	51
valid_sources[0x49]	17745	1			T1	6		T4	12		T7	6
valid_sources[0x4a]	6735	1			T1	7		T4	8		T7	4
valid_sources[0x4b]	6509	1			T1	5		T2	27		T4	11
valid_sources[0x4c]	7880	1			T1	2		T4	14		T9	1
valid_sources[0x4d]	7051	1			T1	4		T4	8		T7	3
valid_sources[0x4e]	6952	1			T1	3		T4	6		T7	1
valid_sources[0x4f]	6497	1			T1	1		T4	8		T7	2
valid_sources[0x50]	6536	1			T1	7		T4	7		T7	5
valid_sources[0x51]	11338	1			T4	14		T7	12		T8	28
valid_sources[0x52]	6554	1			T1	1		T4	14		T7	3
valid_sources[0x53]	7112	1			T1	2		T4	25		T7	7
valid_sources[0x54]	6495	1			T1	2		T4	3		T7	1
valid_sources[0x55]	6757	1			T1	3		T4	3		T7	4
valid_sources[0x56]	9625	1			T1	2		T4	23		T7	5
valid_sources[0x57]	6541	1			T2	2		T4	9		T7	4
valid_sources[0x58]	6481	1			T1	8		T7	1		T9	6
valid_sources[0x59]	10775	1			T4	7		T7	2		T8	134
valid_sources[0x5a]	9150	1			T1	4		T4	17		T7	9
valid_sources[0x5b]	6426	1			T4	11		T7	11		T9	5
valid_sources[0x5c]	6597	1			T4	7		T7	10		T8	15
valid_sources[0x5d]	8234	1			T1	1		T4	39		T7	4
valid_sources[0x5e]	10522	1			T1	1		T4	18		T7	11
valid_sources[0x5f]	9076	1			T1	2		T4	10		T7	5
valid_sources[0x60]	6437	1			T4	28		T7	3		T9	6
valid_sources[0x61]	33898	1			T1	1		T4	7		T10	49
valid_sources[0x62]	8493	1			T1	3		T4	28		T7	2
valid_sources[0x63]	6722	1			T1	2		T4	31		T7	7
valid_sources[0x64]	7187	1			T1	1		T4	45		T7	2
valid_sources[0x65]	8058	1			T1	3		T4	21		T9	4
valid_sources[0x66]	6774	1			T1	4		T4	22		T7	9
valid_sources[0x67]	6397	1			T1	1		T4	37		T7	1
valid_sources[0x68]	6319	1			T1	1		T4	9		T9	5
valid_sources[0x69]	7384	1			T4	2		T7	5		T9	1
valid_sources[0x6a]	6945	1			T1	3		T4	13		T7	3
valid_sources[0x6b]	6992	1			T1	4		T4	10		T7	8
valid_sources[0x6c]	6468	1			T1	4		T4	17		T7	2
valid_sources[0x6d]	7494	1			T1	4		T4	9		T8	19
valid_sources[0x6e]	9434	1			T4	18		T9	1		T10	27
valid_sources[0x6f]	13460	1			T1	5		T4	4		T7	7
valid_sources[0x70]	6651	1			T1	6		T4	9		T7	4
valid_sources[0x71]	8177	1			T1	3		T4	23		T7	1
valid_sources[0x72]	6331	1			T1	1		T4	28		T7	12
valid_sources[0x73]	6574	1			T1	4		T4	16		T7	5
valid_sources[0x74]	6439	1			T1	8		T4	8		T7	2
valid_sources[0x75]	6373	1			T1	3		T4	4		T9	6
valid_sources[0x76]	8320	1			T4	27		T7	2		T9	5
valid_sources[0x77]	6351	1			T4	14		T7	4		T9	3
valid_sources[0x78]	6629	1			T1	6		T4	20		T7	7
valid_sources[0x79]	7118	1			T4	3		T9	2		T10	113
valid_sources[0x7a]	6714	1			T1	1		T4	12		T7	5
valid_sources[0x7b]	7008	1			T1	1		T4	18		T7	7
valid_sources[0x7c]	8722	1			T1	9		T4	9		T7	10
valid_sources[0x7d]	7165	1			T1	6		T4	12		T7	6
valid_sources[0x7e]	6660	1			T1	1		T4	15		T7	1
valid_sources[0x7f]	11867	1			T1	2		T4	4		T7	3
valid_sources[0x80]	6399	1			T4	24		T7	11		T10	58

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6775

1

T4

14

T10

7

T5

11

values[0x0]

all_enables

biggest_size

6699

1

T1

2

T2

1

T3

2

values[0x1]

all_enables

biggest_size

4754

1

T1

2

T3

1

T4

1