Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13488683

1

T2

904

T3

2530

T4

22

full_word

53307528

1

T1

38912

T2

58

T3

24918

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	66795891	1			T1	38912		T2	962		T3	27448
auto[TlIntgErrCmd]	104	1			T34	2		T35	2		T36	10
auto[TlIntgErrData]	105	1			T34	4		T35	2		T36	8
auto[TlIntgErrBoth]	111	1			T34	4		T35	6		T36	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30633527

1

T1

19456

T2

347

T3

10313

auto[1]

36162684

1

T1

19456

T2

615

T3

17135

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6489429	1			T2	345		T3	969		T4	12
auto[TlIntgErrNone]	partial	auto[1]	6998963	1			T2	559		T3	1561		T4	10
auto[TlIntgErrNone]	full_word	auto[0]	24143953	1			T1	19456		T2	2		T3	9344
auto[TlIntgErrNone]	full_word	auto[1]	29163546	1			T1	19456		T2	56		T3	15574
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T34	1		T36	2		T55	1
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T34	1		T35	2		T36	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T36	1		T112	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T36	2		T55	1		T112	2
auto[TlIntgErrData]	partial	auto[0]	50	1			T34	1		T36	3		T55	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T34	3		T35	1		T36	4
auto[TlIntgErrData]	full_word	auto[0]	7	1			T36	1		T61	1		T108	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T35	1		T55	1		T109	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T34	2		T35	3		T36	1
auto[TlIntgErrBoth]	partial	auto[1]	60	1			T34	2		T35	3		T36	1
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T110	1		T109	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T108	1		T106	1		T109	1