Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	645664	1			T2	88		T12	27284		T13	834
auto[1]	9949894	1			T2	103		T3	93		T4	10
auto[2]	548379	1			T2	79		T12	23710		T13	594
auto[3]	9860744	1			T2	194		T3	88		T4	5

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13495658	1			T3	126		T4	10		T7	9996
auto[1]	2030137	1			T2	8		T3	25		T4	3
auto[2]	2018805	1			T2	19		T3	27		T4	2
auto[3]	3460081	1			T2	437		T3	3		T8	1808

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7919144

1

T2

463

T3

181

T4

15

auto[1]

13085537

1

T2

1

T7

13

T8

225229

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	297106	1			T13	673		T117	9014		T23	898
auto[0]	auto[0]	auto[1]	30661	1			T2	1		T13	80		T117	847
auto[0]	auto[0]	auto[2]	30890	1			T2	1		T13	71		T117	894
auto[0]	auto[0]	auto[3]	9757	1			T2	85		T13	8		T117	82
auto[0]	auto[1]	auto[0]	2938983	1			T3	65		T4	6		T7	4972
auto[0]	auto[1]	auto[1]	319945	1			T3	20		T4	2		T10	1180
auto[0]	auto[1]	auto[2]	299138	1			T3	6		T4	2		T10	1316
auto[0]	auto[1]	auto[3]	75462	1			T2	103		T3	2		T10	126
auto[0]	auto[2]	auto[0]	263394	1			T12	1		T13	465		T117	8261
auto[0]	auto[2]	auto[1]	27121	1			T2	4		T13	45		T117	816
auto[0]	auto[2]	auto[2]	24089	1			T2	1		T13	75		T117	772
auto[0]	auto[2]	auto[3]	7760	1			T2	74		T12	2		T13	9
auto[0]	auto[3]	auto[0]	2906123	1			T3	61		T4	4		T7	5011
auto[0]	auto[3]	auto[1]	296359	1			T2	3		T3	5		T4	1
auto[0]	auto[3]	auto[2]	314674	1			T2	17		T3	21		T10	1242
auto[0]	auto[3]	auto[3]	77682	1			T2	174		T3	1		T10	128
auto[1]	auto[0]	auto[0]	9435	1			T12	905		T13	2		T117	11
auto[1]	auto[0]	auto[1]	40888	1			T12	4008		T117	1		T118	5078
auto[1]	auto[0]	auto[2]	41186	1			T12	4081		T114	1		T118	5017
auto[1]	auto[0]	auto[3]	185741	1			T2	1		T12	18290		T80	2
auto[1]	auto[1]	auto[0]	3538267	1			T7	8		T8	92987		T9	1
auto[1]	auto[1]	auto[1]	653971	1			T8	9140		T12	4090		T16	6797
auto[1]	auto[1]	auto[2]	630756	1			T8	9376		T10	1		T12	626
auto[1]	auto[1]	auto[3]	1493372	1			T8	895		T12	18634		T14	3
auto[1]	auto[2]	auto[0]	8116	1			T12	856		T117	2		T118	1044
auto[1]	auto[2]	auto[1]	35660	1			T12	3886		T118	4614		T107	3
auto[1]	auto[2]	auto[2]	32871	1			T12	3365		T117	1		T118	4358
auto[1]	auto[2]	auto[3]	149368	1			T12	15600		T119	1		T118	19141
auto[1]	auto[3]	auto[0]	3534234	1			T7	5		T8	93347		T10	16
auto[1]	auto[3]	auto[1]	625532	1			T8	9308		T12	326		T16	7011
auto[1]	auto[3]	auto[2]	645201	1			T8	9263		T12	3513		T16	6938
auto[1]	auto[3]	auto[3]	1460939	1			T8	913		T12	15843		T14	1