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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.26 100.00 97.48 100.00 100.00 99.14 99.70 98.52


Total test records in report: 958
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T803 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2093969700 Feb 25 02:48:11 PM PST 24 Feb 25 02:53:38 PM PST 24 10283043379 ps
T804 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3886454949 Feb 25 02:45:32 PM PST 24 Feb 25 02:51:18 PM PST 24 7239211031 ps
T805 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2106942029 Feb 25 02:46:01 PM PST 24 Feb 25 02:49:34 PM PST 24 34764485701 ps
T806 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3552132506 Feb 25 02:49:34 PM PST 24 Feb 25 03:02:39 PM PST 24 3243251005 ps
T807 /workspace/coverage/default/13.sram_ctrl_bijection.913525015 Feb 25 02:46:26 PM PST 24 Feb 25 02:47:26 PM PST 24 6181799763 ps
T808 /workspace/coverage/default/42.sram_ctrl_executable.2935223784 Feb 25 02:49:25 PM PST 24 Feb 25 03:10:58 PM PST 24 16776274132 ps
T809 /workspace/coverage/default/26.sram_ctrl_executable.3649787364 Feb 25 02:47:26 PM PST 24 Feb 25 03:09:44 PM PST 24 3283878192 ps
T810 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.719401102 Feb 25 02:49:19 PM PST 24 Feb 25 02:55:27 PM PST 24 5375622553 ps
T811 /workspace/coverage/default/9.sram_ctrl_smoke.3260788194 Feb 25 02:46:10 PM PST 24 Feb 25 02:46:26 PM PST 24 2366441988 ps
T812 /workspace/coverage/default/41.sram_ctrl_bijection.2631184953 Feb 25 02:49:13 PM PST 24 Feb 25 02:50:00 PM PST 24 745327225 ps
T813 /workspace/coverage/default/20.sram_ctrl_executable.2795501681 Feb 25 02:46:54 PM PST 24 Feb 25 03:02:08 PM PST 24 13965054147 ps
T814 /workspace/coverage/default/15.sram_ctrl_alert_test.186987041 Feb 25 02:46:31 PM PST 24 Feb 25 02:46:32 PM PST 24 13036925 ps
T815 /workspace/coverage/default/10.sram_ctrl_multiple_keys.3380624035 Feb 25 02:46:08 PM PST 24 Feb 25 02:57:59 PM PST 24 12587788546 ps
T816 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3523114431 Feb 25 02:45:50 PM PST 24 Feb 25 02:52:02 PM PST 24 21387649430 ps
T817 /workspace/coverage/default/38.sram_ctrl_stress_all.4224348028 Feb 25 02:49:11 PM PST 24 Feb 25 03:03:12 PM PST 24 17665905082 ps
T818 /workspace/coverage/default/24.sram_ctrl_partial_access.2729768484 Feb 25 02:47:15 PM PST 24 Feb 25 02:47:27 PM PST 24 568500771 ps
T819 /workspace/coverage/default/0.sram_ctrl_smoke.4053279789 Feb 25 02:45:50 PM PST 24 Feb 25 02:47:01 PM PST 24 2035016909 ps
T820 /workspace/coverage/default/1.sram_ctrl_max_throughput.1410039001 Feb 25 02:45:32 PM PST 24 Feb 25 02:46:43 PM PST 24 616362400 ps
T821 /workspace/coverage/default/5.sram_ctrl_ram_cfg.1307431281 Feb 25 02:45:59 PM PST 24 Feb 25 02:46:03 PM PST 24 90857325 ps
T822 /workspace/coverage/default/16.sram_ctrl_bijection.1068383596 Feb 25 02:46:33 PM PST 24 Feb 25 02:47:25 PM PST 24 18984447419 ps
T823 /workspace/coverage/default/30.sram_ctrl_executable.1769534860 Feb 25 02:48:04 PM PST 24 Feb 25 03:02:58 PM PST 24 48646488745 ps
T824 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2733780579 Feb 25 02:46:23 PM PST 24 Feb 25 02:50:41 PM PST 24 2827140105 ps
T825 /workspace/coverage/default/39.sram_ctrl_regwen.1769176055 Feb 25 02:49:06 PM PST 24 Feb 25 02:59:12 PM PST 24 24559481911 ps
T826 /workspace/coverage/default/40.sram_ctrl_multiple_keys.3735399363 Feb 25 02:49:05 PM PST 24 Feb 25 02:49:29 PM PST 24 919680905 ps
T827 /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1347146612 Feb 25 02:50:21 PM PST 24 Feb 25 03:09:37 PM PST 24 4082502292 ps
T828 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.357588586 Feb 25 02:50:22 PM PST 24 Feb 25 02:53:22 PM PST 24 3626109584 ps
T829 /workspace/coverage/default/47.sram_ctrl_alert_test.1299704971 Feb 25 02:50:12 PM PST 24 Feb 25 02:50:13 PM PST 24 14252635 ps
T830 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1702782217 Feb 25 02:47:33 PM PST 24 Feb 25 03:14:54 PM PST 24 7767847260 ps
T831 /workspace/coverage/default/18.sram_ctrl_mem_walk.3758526420 Feb 25 02:46:46 PM PST 24 Feb 25 02:46:56 PM PST 24 692328080 ps
T832 /workspace/coverage/default/31.sram_ctrl_smoke.3548633923 Feb 25 02:48:09 PM PST 24 Feb 25 02:48:26 PM PST 24 2304285484 ps
T833 /workspace/coverage/default/10.sram_ctrl_regwen.1126727161 Feb 25 02:46:27 PM PST 24 Feb 25 02:53:20 PM PST 24 2487153606 ps
T834 /workspace/coverage/default/4.sram_ctrl_multiple_keys.808170643 Feb 25 02:45:49 PM PST 24 Feb 25 02:57:07 PM PST 24 5401558699 ps
T835 /workspace/coverage/default/21.sram_ctrl_alert_test.3960020680 Feb 25 02:47:11 PM PST 24 Feb 25 02:47:12 PM PST 24 14608839 ps
T836 /workspace/coverage/default/36.sram_ctrl_partial_access.582643637 Feb 25 02:48:35 PM PST 24 Feb 25 02:48:39 PM PST 24 91959997 ps
T837 /workspace/coverage/default/39.sram_ctrl_executable.1885459837 Feb 25 02:49:07 PM PST 24 Feb 25 03:00:21 PM PST 24 18241164188 ps
T838 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3170432066 Feb 25 02:45:52 PM PST 24 Feb 25 02:54:37 PM PST 24 91262411791 ps
T839 /workspace/coverage/default/14.sram_ctrl_bijection.3145706483 Feb 25 02:46:23 PM PST 24 Feb 25 02:46:52 PM PST 24 1665964835 ps
T840 /workspace/coverage/default/47.sram_ctrl_mem_walk.1265017761 Feb 25 02:50:13 PM PST 24 Feb 25 02:50:20 PM PST 24 2056153979 ps
T841 /workspace/coverage/default/2.sram_ctrl_multiple_keys.2938580870 Feb 25 02:45:56 PM PST 24 Feb 25 03:07:21 PM PST 24 40794958065 ps
T842 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2383777195 Feb 25 02:46:10 PM PST 24 Feb 25 02:46:48 PM PST 24 380840054 ps
T843 /workspace/coverage/default/33.sram_ctrl_max_throughput.4115648510 Feb 25 02:48:23 PM PST 24 Feb 25 02:48:31 PM PST 24 105188156 ps
T844 /workspace/coverage/default/47.sram_ctrl_bijection.3815540005 Feb 25 02:50:12 PM PST 24 Feb 25 02:51:45 PM PST 24 34560118323 ps
T845 /workspace/coverage/default/7.sram_ctrl_lc_escalation.1181608383 Feb 25 02:46:00 PM PST 24 Feb 25 02:46:07 PM PST 24 228211406 ps
T846 /workspace/coverage/default/35.sram_ctrl_ram_cfg.2782686346 Feb 25 02:48:41 PM PST 24 Feb 25 02:48:42 PM PST 24 31505814 ps
T847 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3861172345 Feb 25 02:49:51 PM PST 24 Feb 25 02:52:00 PM PST 24 616267514 ps
T848 /workspace/coverage/default/19.sram_ctrl_lc_escalation.1810162639 Feb 25 02:46:55 PM PST 24 Feb 25 02:47:05 PM PST 24 799859665 ps
T849 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2359837789 Feb 25 02:48:19 PM PST 24 Feb 25 02:52:54 PM PST 24 24558654017 ps
T850 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2371901387 Feb 25 02:50:14 PM PST 24 Feb 25 02:54:11 PM PST 24 2466534405 ps
T851 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.766562510 Feb 25 02:45:37 PM PST 24 Feb 25 02:46:11 PM PST 24 326408678 ps
T852 /workspace/coverage/default/30.sram_ctrl_lc_escalation.765698162 Feb 25 02:47:59 PM PST 24 Feb 25 02:48:08 PM PST 24 1279000742 ps
T853 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.802228514 Feb 25 02:47:26 PM PST 24 Feb 25 02:47:31 PM PST 24 126876567 ps
T854 /workspace/coverage/default/44.sram_ctrl_regwen.3616169643 Feb 25 02:49:38 PM PST 24 Feb 25 02:53:29 PM PST 24 787296847 ps
T855 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2396597788 Feb 25 02:49:36 PM PST 24 Feb 25 02:49:53 PM PST 24 732881375 ps
T856 /workspace/coverage/default/31.sram_ctrl_alert_test.528715162 Feb 25 02:48:12 PM PST 24 Feb 25 02:48:13 PM PST 24 20120356 ps
T857 /workspace/coverage/default/31.sram_ctrl_partial_access.2601873379 Feb 25 02:48:12 PM PST 24 Feb 25 02:48:32 PM PST 24 4075932223 ps
T858 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3099564216 Feb 25 02:46:24 PM PST 24 Feb 25 02:48:29 PM PST 24 587276772 ps
T859 /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2518488481 Feb 25 02:46:26 PM PST 24 Feb 25 03:10:03 PM PST 24 6990731235 ps
T860 /workspace/coverage/default/0.sram_ctrl_mem_walk.879794131 Feb 25 02:45:39 PM PST 24 Feb 25 02:45:47 PM PST 24 137373749 ps
T861 /workspace/coverage/default/47.sram_ctrl_partial_access.1219023238 Feb 25 02:50:18 PM PST 24 Feb 25 02:51:40 PM PST 24 571040077 ps
T862 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1315283384 Feb 25 02:45:45 PM PST 24 Feb 25 02:50:56 PM PST 24 10158547115 ps
T863 /workspace/coverage/default/41.sram_ctrl_smoke.2968443166 Feb 25 02:49:21 PM PST 24 Feb 25 02:51:40 PM PST 24 1374387649 ps
T864 /workspace/coverage/default/24.sram_ctrl_alert_test.3990167450 Feb 25 02:47:18 PM PST 24 Feb 25 02:47:19 PM PST 24 86458707 ps
T865 /workspace/coverage/default/17.sram_ctrl_stress_all.3508449608 Feb 25 02:46:43 PM PST 24 Feb 25 03:57:56 PM PST 24 41851245603 ps
T866 /workspace/coverage/default/13.sram_ctrl_smoke.3056745819 Feb 25 02:46:23 PM PST 24 Feb 25 02:48:33 PM PST 24 1878531090 ps
T867 /workspace/coverage/default/8.sram_ctrl_bijection.1665536968 Feb 25 02:46:17 PM PST 24 Feb 25 02:46:59 PM PST 24 3892809377 ps
T868 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.859981939 Feb 25 02:46:44 PM PST 24 Feb 25 02:47:24 PM PST 24 213597307 ps
T869 /workspace/coverage/default/2.sram_ctrl_alert_test.2697340294 Feb 25 02:45:53 PM PST 24 Feb 25 02:45:54 PM PST 24 14728613 ps
T870 /workspace/coverage/default/42.sram_ctrl_mem_walk.318599664 Feb 25 02:49:29 PM PST 24 Feb 25 02:49:34 PM PST 24 87780412 ps
T871 /workspace/coverage/default/26.sram_ctrl_bijection.13931716 Feb 25 02:47:27 PM PST 24 Feb 25 02:48:11 PM PST 24 684827024 ps
T872 /workspace/coverage/default/9.sram_ctrl_multiple_keys.1233468242 Feb 25 02:46:04 PM PST 24 Feb 25 03:00:50 PM PST 24 3346682591 ps
T873 /workspace/coverage/default/45.sram_ctrl_access_during_key_req.226396246 Feb 25 02:49:50 PM PST 24 Feb 25 03:07:00 PM PST 24 3990866866 ps
T874 /workspace/coverage/default/16.sram_ctrl_stress_all.3504862528 Feb 25 02:46:41 PM PST 24 Feb 25 04:05:19 PM PST 24 46698642844 ps
T875 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.4033163380 Feb 25 02:49:06 PM PST 24 Feb 25 02:54:25 PM PST 24 6447856652 ps
T876 /workspace/coverage/default/47.sram_ctrl_max_throughput.965904897 Feb 25 02:50:14 PM PST 24 Feb 25 02:51:20 PM PST 24 113229813 ps
T877 /workspace/coverage/default/21.sram_ctrl_bijection.203683442 Feb 25 02:47:21 PM PST 24 Feb 25 02:47:39 PM PST 24 540380820 ps
T878 /workspace/coverage/default/23.sram_ctrl_ram_cfg.1389866102 Feb 25 02:47:12 PM PST 24 Feb 25 02:47:14 PM PST 24 71015244 ps
T879 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.1008687751 Feb 25 02:48:05 PM PST 24 Feb 25 02:58:17 PM PST 24 11119811097 ps
T880 /workspace/coverage/default/38.sram_ctrl_alert_test.3287561539 Feb 25 02:48:55 PM PST 24 Feb 25 02:48:56 PM PST 24 57296618 ps
T881 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3265844245 Feb 25 02:46:30 PM PST 24 Feb 25 02:47:05 PM PST 24 377253730 ps
T882 /workspace/coverage/default/42.sram_ctrl_lc_escalation.1587647815 Feb 25 02:49:30 PM PST 24 Feb 25 02:49:32 PM PST 24 298942928 ps
T883 /workspace/coverage/default/4.sram_ctrl_bijection.2185895656 Feb 25 02:45:53 PM PST 24 Feb 25 02:47:14 PM PST 24 18996345357 ps
T884 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2076246962 Feb 25 02:49:22 PM PST 24 Feb 25 02:49:30 PM PST 24 242514718 ps
T885 /workspace/coverage/default/12.sram_ctrl_max_throughput.1473514300 Feb 25 02:46:16 PM PST 24 Feb 25 02:47:49 PM PST 24 117761401 ps
T886 /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3390726132 Feb 25 02:46:44 PM PST 24 Feb 25 02:50:19 PM PST 24 8206741910 ps
T887 /workspace/coverage/default/28.sram_ctrl_executable.3815440304 Feb 25 02:48:04 PM PST 24 Feb 25 03:03:14 PM PST 24 12281921763 ps
T888 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2565577715 Feb 25 02:48:19 PM PST 24 Feb 25 02:48:23 PM PST 24 86224522 ps
T889 /workspace/coverage/default/35.sram_ctrl_regwen.472813977 Feb 25 02:48:40 PM PST 24 Feb 25 02:53:31 PM PST 24 2183660773 ps
T890 /workspace/coverage/default/32.sram_ctrl_stress_all.158498923 Feb 25 02:48:12 PM PST 24 Feb 25 03:13:10 PM PST 24 112905755273 ps
T891 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.3908809461 Feb 25 02:49:30 PM PST 24 Feb 25 02:56:14 PM PST 24 1952584995 ps
T892 /workspace/coverage/default/9.sram_ctrl_stress_all.2747761919 Feb 25 02:46:15 PM PST 24 Feb 25 04:07:09 PM PST 24 271080737242 ps
T893 /workspace/coverage/default/44.sram_ctrl_max_throughput.4217179532 Feb 25 02:49:43 PM PST 24 Feb 25 02:49:46 PM PST 24 71773859 ps
T894 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2548032921 Feb 25 02:45:48 PM PST 24 Feb 25 02:48:44 PM PST 24 7363527481 ps
T895 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3361671828 Feb 25 02:49:42 PM PST 24 Feb 25 02:54:15 PM PST 24 11127833580 ps
T102 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2839706957 Feb 25 01:46:47 PM PST 24 Feb 25 01:46:48 PM PST 24 48122529 ps
T34 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2250297082 Feb 25 01:46:45 PM PST 24 Feb 25 01:46:47 PM PST 24 756772319 ps
T62 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4082331557 Feb 25 01:46:31 PM PST 24 Feb 25 01:46:32 PM PST 24 12602397 ps
T63 /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2168777773 Feb 25 01:46:55 PM PST 24 Feb 25 01:47:02 PM PST 24 586612138 ps
T93 /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3713826161 Feb 25 01:46:45 PM PST 24 Feb 25 01:46:46 PM PST 24 20649848 ps
T94 /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1935724735 Feb 25 01:47:00 PM PST 24 Feb 25 01:47:01 PM PST 24 177424847 ps
T95 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1506176409 Feb 25 01:46:45 PM PST 24 Feb 25 01:46:46 PM PST 24 156579124 ps
T35 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2355936609 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:48 PM PST 24 180720192 ps
T96 /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1949257222 Feb 25 01:46:36 PM PST 24 Feb 25 01:46:39 PM PST 24 800371113 ps
T64 /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1234629861 Feb 25 01:46:41 PM PST 24 Feb 25 01:46:47 PM PST 24 1568900609 ps
T65 /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.624355251 Feb 25 01:46:42 PM PST 24 Feb 25 01:46:53 PM PST 24 3041767167 ps
T37 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4283763568 Feb 25 01:46:58 PM PST 24 Feb 25 01:47:02 PM PST 24 81462129 ps
T103 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.494899504 Feb 25 01:46:35 PM PST 24 Feb 25 01:46:35 PM PST 24 19133068 ps
T52 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1376338718 Feb 25 01:46:44 PM PST 24 Feb 25 01:46:47 PM PST 24 206291098 ps
T97 /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2786614840 Feb 25 01:46:39 PM PST 24 Feb 25 01:46:40 PM PST 24 47480576 ps
T36 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1833882157 Feb 25 01:46:59 PM PST 24 Feb 25 01:47:02 PM PST 24 270242463 ps
T66 /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1997503785 Feb 25 01:46:47 PM PST 24 Feb 25 01:46:50 PM PST 24 276336636 ps
T53 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1542690210 Feb 25 01:46:40 PM PST 24 Feb 25 01:46:44 PM PST 24 40516525 ps
T67 /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2128905679 Feb 25 01:46:44 PM PST 24 Feb 25 01:46:50 PM PST 24 446538965 ps
T54 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.782676769 Feb 25 01:46:45 PM PST 24 Feb 25 01:46:49 PM PST 24 44664845 ps
T896 /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2044143384 Feb 25 01:46:47 PM PST 24 Feb 25 01:46:48 PM PST 24 33330886 ps
T68 /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.614131330 Feb 25 01:46:58 PM PST 24 Feb 25 01:47:00 PM PST 24 21370917 ps
T897 /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3787481259 Feb 25 01:47:03 PM PST 24 Feb 25 01:47:04 PM PST 24 22626259 ps
T898 /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.499791276 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:47 PM PST 24 16690218 ps
T55 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2638723488 Feb 25 01:46:35 PM PST 24 Feb 25 01:46:37 PM PST 24 1012609582 ps
T69 /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4132573331 Feb 25 01:46:42 PM PST 24 Feb 25 01:46:43 PM PST 24 12811842 ps
T70 /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2113160490 Feb 25 01:46:44 PM PST 24 Feb 25 01:46:45 PM PST 24 12156312 ps
T71 /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1649850350 Feb 25 01:47:00 PM PST 24 Feb 25 01:47:01 PM PST 24 35048165 ps
T75 /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2539889879 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:47 PM PST 24 25101714 ps
T56 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3272628435 Feb 25 01:46:36 PM PST 24 Feb 25 01:46:39 PM PST 24 30335157 ps
T57 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3708085343 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:50 PM PST 24 2170996011 ps
T58 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3138949854 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:51 PM PST 24 439036079 ps
T61 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.287387948 Feb 25 01:46:40 PM PST 24 Feb 25 01:46:43 PM PST 24 232586064 ps
T899 /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1768121139 Feb 25 01:47:04 PM PST 24 Feb 25 01:47:05 PM PST 24 19535427 ps
T76 /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4095211450 Feb 25 01:46:48 PM PST 24 Feb 25 01:46:59 PM PST 24 1460760285 ps
T59 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4292705906 Feb 25 01:46:36 PM PST 24 Feb 25 01:46:41 PM PST 24 150405905 ps
T108 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3228093090 Feb 25 01:47:03 PM PST 24 Feb 25 01:47:05 PM PST 24 77475667 ps
T60 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.659128377 Feb 25 01:46:45 PM PST 24 Feb 25 01:46:49 PM PST 24 65790322 ps
T77 /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.879867581 Feb 25 01:47:00 PM PST 24 Feb 25 01:47:06 PM PST 24 777772702 ps
T900 /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1569093943 Feb 25 01:46:42 PM PST 24 Feb 25 01:46:46 PM PST 24 793377698 ps
T901 /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.866321450 Feb 25 01:46:42 PM PST 24 Feb 25 01:46:44 PM PST 24 13794768 ps
T902 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1422379749 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:48 PM PST 24 250741901 ps
T104 /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1105414443 Feb 25 01:46:42 PM PST 24 Feb 25 01:46:44 PM PST 24 42659738 ps
T903 /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.522248136 Feb 25 01:46:58 PM PST 24 Feb 25 01:47:00 PM PST 24 21021414 ps
T904 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4107554569 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:48 PM PST 24 207976932 ps
T78 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2487823415 Feb 25 01:46:42 PM PST 24 Feb 25 01:46:52 PM PST 24 1473704288 ps
T105 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1199370753 Feb 25 01:46:47 PM PST 24 Feb 25 01:46:51 PM PST 24 401244807 ps
T905 /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2073515763 Feb 25 01:46:40 PM PST 24 Feb 25 01:46:41 PM PST 24 46770483 ps
T106 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1939909020 Feb 25 01:46:45 PM PST 24 Feb 25 01:46:47 PM PST 24 96541530 ps
T79 /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4226680358 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:47 PM PST 24 27245151 ps
T906 /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3499227691 Feb 25 01:47:01 PM PST 24 Feb 25 01:47:02 PM PST 24 72269502 ps
T85 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1151878597 Feb 25 01:46:40 PM PST 24 Feb 25 01:46:46 PM PST 24 794799809 ps
T86 /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2897670521 Feb 25 01:46:40 PM PST 24 Feb 25 01:46:50 PM PST 24 416222946 ps
T907 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4018376942 Feb 25 01:46:33 PM PST 24 Feb 25 01:46:33 PM PST 24 30564626 ps
T908 /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.630960996 Feb 25 01:47:13 PM PST 24 Feb 25 01:47:25 PM PST 24 1152541020 ps
T110 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2553653210 Feb 25 01:46:44 PM PST 24 Feb 25 01:46:47 PM PST 24 252003907 ps
T909 /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2247203637 Feb 25 01:46:42 PM PST 24 Feb 25 01:46:43 PM PST 24 16586504 ps
T87 /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2974309629 Feb 25 01:46:59 PM PST 24 Feb 25 01:47:04 PM PST 24 1129404876 ps
T910 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.480015092 Feb 25 01:46:56 PM PST 24 Feb 25 01:46:59 PM PST 24 180678491 ps
T112 /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3636633012 Feb 25 01:47:00 PM PST 24 Feb 25 01:47:03 PM PST 24 304119123 ps
T911 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1614405403 Feb 25 01:47:11 PM PST 24 Feb 25 01:47:14 PM PST 24 74270532 ps
T912 /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1038958793 Feb 25 01:46:40 PM PST 24 Feb 25 01:46:41 PM PST 24 18005655 ps
T913 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2043000405 Feb 25 01:46:44 PM PST 24 Feb 25 01:46:46 PM PST 24 32200357 ps
T914 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1750288765 Feb 25 01:46:45 PM PST 24 Feb 25 01:46:45 PM PST 24 68588033 ps
T915 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3495789673 Feb 25 01:46:40 PM PST 24 Feb 25 01:46:42 PM PST 24 14458839 ps
T109 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1638246220 Feb 25 01:47:01 PM PST 24 Feb 25 01:47:03 PM PST 24 453032284 ps
T916 /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.885720345 Feb 25 01:47:04 PM PST 24 Feb 25 01:47:05 PM PST 24 40382983 ps
T917 /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4205707703 Feb 25 01:46:45 PM PST 24 Feb 25 01:46:46 PM PST 24 53022823 ps
T918 /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2173530146 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:47 PM PST 24 17170712 ps
T919 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1139085628 Feb 25 01:46:44 PM PST 24 Feb 25 01:46:46 PM PST 24 146378182 ps
T920 /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.162067 Feb 25 01:46:43 PM PST 24 Feb 25 01:46:44 PM PST 24 55979871 ps
T921 /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2394299964 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:52 PM PST 24 1639905671 ps
T89 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3750654934 Feb 25 01:46:34 PM PST 24 Feb 25 01:46:35 PM PST 24 42967177 ps
T88 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2379128009 Feb 25 01:46:39 PM PST 24 Feb 25 01:46:42 PM PST 24 679888204 ps
T922 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2631335413 Feb 25 01:46:38 PM PST 24 Feb 25 01:46:39 PM PST 24 422349595 ps
T923 /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3846452786 Feb 25 01:46:38 PM PST 24 Feb 25 01:46:39 PM PST 24 25707923 ps
T924 /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2018847426 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:47 PM PST 24 77866738 ps
T925 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2731166423 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:50 PM PST 24 36615480 ps
T926 /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1561420233 Feb 25 01:46:34 PM PST 24 Feb 25 01:46:34 PM PST 24 25925369 ps
T927 /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4161760225 Feb 25 01:46:42 PM PST 24 Feb 25 01:46:47 PM PST 24 2027071026 ps
T928 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3777226383 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:49 PM PST 24 294728135 ps
T929 /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3069574926 Feb 25 01:46:44 PM PST 24 Feb 25 01:46:45 PM PST 24 26312909 ps
T90 /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1069019555 Feb 25 01:46:31 PM PST 24 Feb 25 01:46:43 PM PST 24 847388468 ps
T91 /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1668939539 Feb 25 01:47:00 PM PST 24 Feb 25 01:47:05 PM PST 24 411018936 ps
T930 /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2930373710 Feb 25 01:47:03 PM PST 24 Feb 25 01:47:04 PM PST 24 14018378 ps
T931 /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1472944296 Feb 25 01:46:29 PM PST 24 Feb 25 01:46:34 PM PST 24 146276613 ps
T932 /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1934747212 Feb 25 01:46:42 PM PST 24 Feb 25 01:46:43 PM PST 24 11810487 ps
T933 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3317522377 Feb 25 01:46:40 PM PST 24 Feb 25 01:46:42 PM PST 24 295795379 ps
T934 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.158551557 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:49 PM PST 24 269047478 ps
T935 /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2246989667 Feb 25 01:46:45 PM PST 24 Feb 25 01:46:46 PM PST 24 30438645 ps
T936 /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3124802836 Feb 25 01:46:32 PM PST 24 Feb 25 01:46:32 PM PST 24 45506928 ps
T937 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1125322372 Feb 25 01:47:08 PM PST 24 Feb 25 01:47:13 PM PST 24 550299109 ps
T938 /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.822395539 Feb 25 01:46:58 PM PST 24 Feb 25 01:46:59 PM PST 24 99384248 ps
T939 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.335366873 Feb 25 01:46:57 PM PST 24 Feb 25 01:47:00 PM PST 24 56149038 ps
T111 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4118306954 Feb 25 01:46:33 PM PST 24 Feb 25 01:46:35 PM PST 24 164498706 ps
T940 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4040393982 Feb 25 01:46:33 PM PST 24 Feb 25 01:46:34 PM PST 24 19231625 ps
T941 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3935917479 Feb 25 01:46:36 PM PST 24 Feb 25 01:46:37 PM PST 24 25028535 ps
T942 /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2363973119 Feb 25 01:46:39 PM PST 24 Feb 25 01:46:41 PM PST 24 181350800 ps
T943 /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1981746810 Feb 25 01:46:39 PM PST 24 Feb 25 01:46:40 PM PST 24 138588557 ps
T944 /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3002341346 Feb 25 01:47:00 PM PST 24 Feb 25 01:47:00 PM PST 24 14385588 ps
T945 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1375676588 Feb 25 01:46:35 PM PST 24 Feb 25 01:46:36 PM PST 24 115613391 ps
T946 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2615018740 Feb 25 01:46:57 PM PST 24 Feb 25 01:46:59 PM PST 24 943386699 ps
T947 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.404059506 Feb 25 01:46:30 PM PST 24 Feb 25 01:46:30 PM PST 24 16859101 ps
T948 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1294977945 Feb 25 01:46:45 PM PST 24 Feb 25 01:46:56 PM PST 24 473565010 ps
T949 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2178422562 Feb 25 01:46:40 PM PST 24 Feb 25 01:46:42 PM PST 24 640928462 ps
T84 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2943374591 Feb 25 01:46:32 PM PST 24 Feb 25 01:46:32 PM PST 24 23386673 ps
T950 /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4230274503 Feb 25 01:46:46 PM PST 24 Feb 25 01:46:47 PM PST 24 90924403 ps
T951 /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3379211739 Feb 25 01:46:33 PM PST 24 Feb 25 01:46:34 PM PST 24 38260687 ps
T952 /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3763172862 Feb 25 01:46:58 PM PST 24 Feb 25 01:47:08 PM PST 24 1532971392 ps
T953 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3137722016 Feb 25 01:47:13 PM PST 24 Feb 25 01:47:14 PM PST 24 77799502 ps
T954 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1932854871 Feb 25 01:47:08 PM PST 24 Feb 25 01:47:12 PM PST 24 120049174 ps
T955 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4126857429 Feb 25 01:46:40 PM PST 24 Feb 25 01:46:42 PM PST 24 201922728 ps
T956 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2022990661 Feb 25 01:46:40 PM PST 24 Feb 25 01:46:41 PM PST 24 74971479 ps
T957 /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2351073774 Feb 25 01:47:00 PM PST 24 Feb 25 01:47:01 PM PST 24 54157843 ps
T958 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.950382919 Feb 25 01:46:42 PM PST 24 Feb 25 01:46:45 PM PST 24 209453670 ps

Test location /workspace/coverage/default/0.sram_ctrl_lc_escalation.2966841569
Short name T4
Test name
Test status
Simulation time 880679380 ps
CPU time 11.37 seconds
Started Feb 25 02:45:34 PM PST 24
Finished Feb 25 02:45:46 PM PST 24
Peak memory 210828 kb
Host smart-e702d76d-aa41-4463-8da2-b79cfdf94ef2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966841569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_lc_esc
alation.2966841569
Directory /workspace/0.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_all.2613271828
Short name T10
Test name
Test status
Simulation time 7896590465 ps
CPU time 2235.09 seconds
Started Feb 25 02:47:26 PM PST 24
Finished Feb 25 03:24:41 PM PST 24
Peak memory 373168 kb
Host smart-72444274-7aa0-457a-aaf6-07deff7db81f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613271828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 26.sram_ctrl_stress_all.2613271828
Directory /workspace/26.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1833882157
Short name T36
Test name
Test status
Simulation time 270242463 ps
CPU time 2.47 seconds
Started Feb 25 01:46:59 PM PST 24
Finished Feb 25 01:47:02 PM PST 24
Peak memory 202432 kb
Host smart-4d94efdb-690c-45aa-9f63-20e07338df20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833882157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_tl_intg_err.1833882157
Directory /workspace/19.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_all.2522185009
Short name T23
Test name
Test status
Simulation time 41957541455 ps
CPU time 1348.05 seconds
Started Feb 25 02:47:51 PM PST 24
Finished Feb 25 03:10:20 PM PST 24
Peak memory 374224 kb
Host smart-2d3b33a0-2f36-453c-8270-b7e4cd54152e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522185009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 28.sram_ctrl_stress_all.2522185009
Directory /workspace/28.sram_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.4292705906
Short name T59
Test name
Test status
Simulation time 150405905 ps
CPU time 4.51 seconds
Started Feb 25 01:46:36 PM PST 24
Finished Feb 25 01:46:41 PM PST 24
Peak memory 202456 kb
Host smart-6c0feedc-3c49-4f9d-ac84-211b85be0a90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292705906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 1.sram_ctrl_tl_errors.4292705906
Directory /workspace/1.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.sram_ctrl_sec_cm.1778454761
Short name T42
Test name
Test status
Simulation time 290947962 ps
CPU time 1.89 seconds
Started Feb 25 02:45:43 PM PST 24
Finished Feb 25 02:45:46 PM PST 24
Peak memory 220640 kb
Host smart-048f2f68-e18b-4407-b542-e7be444747bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778454761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_sec_cm.1778454761
Directory /workspace/0.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1528930064
Short name T12
Test name
Test status
Simulation time 34436802798 ps
CPU time 382.41 seconds
Started Feb 25 02:50:20 PM PST 24
Finished Feb 25 02:56:43 PM PST 24
Peak memory 202684 kb
Host smart-147a3549-54c3-4abd-86f4-ce12365cd2e7
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528930064 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 48.sram_ctrl_partial_access_b2b.1528930064
Directory /workspace/48.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_alert_test.2437740519
Short name T27
Test name
Test status
Simulation time 13100522 ps
CPU time 0.67 seconds
Started Feb 25 02:46:16 PM PST 24
Finished Feb 25 02:46:17 PM PST 24
Peak memory 201684 kb
Host smart-3c20f3dd-e314-457c-aba5-972f57ae5b19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437740519 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.sram_ctrl_alert_test.2437740519
Directory /workspace/13.sram_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2168777773
Short name T63
Test name
Test status
Simulation time 586612138 ps
CPU time 6.16 seconds
Started Feb 25 01:46:55 PM PST 24
Finished Feb 25 01:47:02 PM PST 24
Peak memory 202540 kb
Host smart-67b1d9e0-a58f-4b88-93eb-2d55441ac6d8
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168777773 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_passthru_mem_tl_intg_err.2168777773
Directory /workspace/19.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/default/20.sram_ctrl_access_during_key_req.1595304325
Short name T18
Test name
Test status
Simulation time 2368173010 ps
CPU time 781.86 seconds
Started Feb 25 02:46:57 PM PST 24
Finished Feb 25 03:00:00 PM PST 24
Peak memory 373332 kb
Host smart-c0744d7b-baf3-4661-b870-d2a428fa61dd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595304325 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 20.sram_ctrl_access_during_key_req.1595304325
Directory /workspace/20.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2638723488
Short name T55
Test name
Test status
Simulation time 1012609582 ps
CPU time 2.03 seconds
Started Feb 25 01:46:35 PM PST 24
Finished Feb 25 01:46:37 PM PST 24
Peak memory 202380 kb
Host smart-89f33d81-55b4-4ff4-b3f8-15d353c2c2b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638723488 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 2.sram_ctrl_tl_intg_err.2638723488
Directory /workspace/2.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.sram_ctrl_ram_cfg.2906720770
Short name T184
Test name
Test status
Simulation time 44497950 ps
CPU time 0.85 seconds
Started Feb 25 02:46:15 PM PST 24
Finished Feb 25 02:46:16 PM PST 24
Peak memory 202600 kb
Host smart-2f6eef6b-5762-4637-9070-e219f3a51ba1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906720770 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_ram_cfg.2906720770
Directory /workspace/11.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_all.805822263
Short name T180
Test name
Test status
Simulation time 45604925572 ps
CPU time 4797.54 seconds
Started Feb 25 02:46:23 PM PST 24
Finished Feb 25 04:06:21 PM PST 24
Peak memory 375724 kb
Host smart-4cdfadec-606f-4c98-a38a-5c6ba6b345f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805822263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_stress_all.805822263
Directory /workspace/13.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sram_ctrl_regwen.4112004533
Short name T225
Test name
Test status
Simulation time 2839185425 ps
CPU time 711.66 seconds
Started Feb 25 02:47:52 PM PST 24
Finished Feb 25 02:59:44 PM PST 24
Peak memory 372084 kb
Host smart-9be63481-5cf6-4527-918e-857668f0325d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112004533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_regwen.4112004533
Directory /workspace/28.sram_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1638246220
Short name T109
Test name
Test status
Simulation time 453032284 ps
CPU time 2.09 seconds
Started Feb 25 01:47:01 PM PST 24
Finished Feb 25 01:47:03 PM PST 24
Peak memory 202396 kb
Host smart-7798d32b-69b9-4905-bb61-a4b0a3041849
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638246220 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 17.sram_ctrl_tl_intg_err.1638246220
Directory /workspace/17.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4118306954
Short name T111
Test name
Test status
Simulation time 164498706 ps
CPU time 2.28 seconds
Started Feb 25 01:46:33 PM PST 24
Finished Feb 25 01:46:35 PM PST 24
Peak memory 202388 kb
Host smart-ffae6321-0a6e-4d68-a5d3-e1ac58152e0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118306954 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.sram_ctrl_tl_intg_err.4118306954
Directory /workspace/1.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.sram_ctrl_regwen.656702240
Short name T178
Test name
Test status
Simulation time 69137063154 ps
CPU time 527.26 seconds
Started Feb 25 02:46:30 PM PST 24
Finished Feb 25 02:55:18 PM PST 24
Peak memory 371628 kb
Host smart-497a9fac-9559-4b0c-a337-b8e90a5ed908
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656702240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_regwen.656702240
Directory /workspace/12.sram_ctrl_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3750654934
Short name T89
Test name
Test status
Simulation time 42967177 ps
CPU time 0.65 seconds
Started Feb 25 01:46:34 PM PST 24
Finished Feb 25 01:46:35 PM PST 24
Peak memory 202180 kb
Host smart-58caf458-ad59-4596-a9c2-78bf2b5303ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750654934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_csr_rw.3750654934
Directory /workspace/0.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4082331557
Short name T62
Test name
Test status
Simulation time 12602397 ps
CPU time 0.68 seconds
Started Feb 25 01:46:31 PM PST 24
Finished Feb 25 01:46:32 PM PST 24
Peak memory 202216 kb
Host smart-1594e3b8-7f54-435e-a6f3-fb24e2f038a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082331557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_aliasing.4082331557
Directory /workspace/0.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2022990661
Short name T956
Test name
Test status
Simulation time 74971479 ps
CPU time 1.32 seconds
Started Feb 25 01:46:40 PM PST 24
Finished Feb 25 01:46:41 PM PST 24
Peak memory 202252 kb
Host smart-ed4f9601-4ce5-4003-b260-351c029f0b6a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022990661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_bit_bash.2022990661
Directory /workspace/0.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.4018376942
Short name T907
Test name
Test status
Simulation time 30564626 ps
CPU time 0.65 seconds
Started Feb 25 01:46:33 PM PST 24
Finished Feb 25 01:46:33 PM PST 24
Peak memory 201420 kb
Host smart-250250bc-1915-4dc3-8226-138db505efdd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018376942 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.sram_ctrl_csr_hw_reset.4018376942
Directory /workspace/0.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2897670521
Short name T86
Test name
Test status
Simulation time 416222946 ps
CPU time 10.18 seconds
Started Feb 25 01:46:40 PM PST 24
Finished Feb 25 01:46:50 PM PST 24
Peak memory 202484 kb
Host smart-1adbc687-aebb-4ad9-8899-f10055633483
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897670521 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_passthru_mem_tl_intg_err.2897670521
Directory /workspace/0.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1561420233
Short name T926
Test name
Test status
Simulation time 25925369 ps
CPU time 0.74 seconds
Started Feb 25 01:46:34 PM PST 24
Finished Feb 25 01:46:34 PM PST 24
Peak memory 202180 kb
Host smart-052ef653-426f-4390-8e6e-f06072e3a656
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561420233 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.sram_ctrl_same_csr_outstanding.1561420233
Directory /workspace/0.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3272628435
Short name T56
Test name
Test status
Simulation time 30335157 ps
CPU time 2.31 seconds
Started Feb 25 01:46:36 PM PST 24
Finished Feb 25 01:46:39 PM PST 24
Peak memory 202464 kb
Host smart-acc2e234-5789-44f8-9b07-070662b26c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272628435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.sram_ctrl_tl_errors.3272628435
Directory /workspace/0.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1375676588
Short name T945
Test name
Test status
Simulation time 115613391 ps
CPU time 1.51 seconds
Started Feb 25 01:46:35 PM PST 24
Finished Feb 25 01:46:36 PM PST 24
Peak memory 202392 kb
Host smart-d213f937-b0f2-431e-8466-fd03221ea97f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375676588 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.sram_ctrl_tl_intg_err.1375676588
Directory /workspace/0.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3935917479
Short name T941
Test name
Test status
Simulation time 25028535 ps
CPU time 0.67 seconds
Started Feb 25 01:46:36 PM PST 24
Finished Feb 25 01:46:37 PM PST 24
Peak memory 202200 kb
Host smart-b1fcc6aa-0c4c-4e87-8eca-7ac87504430e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935917479 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_aliasing.3935917479
Directory /workspace/1.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2379128009
Short name T88
Test name
Test status
Simulation time 679888204 ps
CPU time 2.49 seconds
Started Feb 25 01:46:39 PM PST 24
Finished Feb 25 01:46:42 PM PST 24
Peak memory 202276 kb
Host smart-00ae7343-6f45-4de6-8d4c-c76681e11a1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379128009 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.sram_ctrl_csr_bit_bash.2379128009
Directory /workspace/1.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.494899504
Short name T103
Test name
Test status
Simulation time 19133068 ps
CPU time 0.65 seconds
Started Feb 25 01:46:35 PM PST 24
Finished Feb 25 01:46:35 PM PST 24
Peak memory 202184 kb
Host smart-7cab1817-5b18-40bf-b974-3e29f2581c14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494899504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.sram_ctrl_csr_hw_reset.494899504
Directory /workspace/1.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.404059506
Short name T947
Test name
Test status
Simulation time 16859101 ps
CPU time 0.66 seconds
Started Feb 25 01:46:30 PM PST 24
Finished Feb 25 01:46:30 PM PST 24
Peak memory 202156 kb
Host smart-899c8977-98a0-4b78-abed-b39d118ff584
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404059506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.sram_ctrl_csr_rw.404059506
Directory /workspace/1.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1069019555
Short name T90
Test name
Test status
Simulation time 847388468 ps
CPU time 11.46 seconds
Started Feb 25 01:46:31 PM PST 24
Finished Feb 25 01:46:43 PM PST 24
Peak memory 202576 kb
Host smart-c2cba9fc-1142-4acd-99da-0b77b9e01efb
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069019555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.sram_ctrl_passthru_mem_tl_intg_err.1069019555
Directory /workspace/1.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3124802836
Short name T936
Test name
Test status
Simulation time 45506928 ps
CPU time 0.64 seconds
Started Feb 25 01:46:32 PM PST 24
Finished Feb 25 01:46:32 PM PST 24
Peak memory 202100 kb
Host smart-1f7a9246-e56f-40cf-a45a-f923fecbfc26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124802836 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.sram_ctrl_same_csr_outstanding.3124802836
Directory /workspace/1.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4226680358
Short name T79
Test name
Test status
Simulation time 27245151 ps
CPU time 0.64 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:47 PM PST 24
Peak memory 202200 kb
Host smart-1cedc3cd-66dd-4e99-93fe-658b0015bddd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226680358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_csr_rw.4226680358
Directory /workspace/10.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4161760225
Short name T927
Test name
Test status
Simulation time 2027071026 ps
CPU time 4.81 seconds
Started Feb 25 01:46:42 PM PST 24
Finished Feb 25 01:46:47 PM PST 24
Peak memory 202108 kb
Host smart-7ac4fe6e-6ffb-4068-bd72-ec8fca4b4b7e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161760225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_passthru_mem_tl_intg_err.4161760225
Directory /workspace/10.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3069574926
Short name T929
Test name
Test status
Simulation time 26312909 ps
CPU time 0.75 seconds
Started Feb 25 01:46:44 PM PST 24
Finished Feb 25 01:46:45 PM PST 24
Peak memory 202172 kb
Host smart-0bda506c-d4fa-4749-aedf-041a59ef2c07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069574926 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.sram_ctrl_same_csr_outstanding.3069574926
Directory /workspace/10.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1376338718
Short name T52
Test name
Test status
Simulation time 206291098 ps
CPU time 2.22 seconds
Started Feb 25 01:46:44 PM PST 24
Finished Feb 25 01:46:47 PM PST 24
Peak memory 202492 kb
Host smart-ccd3d521-bab3-4dea-bb93-e48e7b40a38f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376338718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.sram_ctrl_tl_errors.1376338718
Directory /workspace/10.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1139085628
Short name T919
Test name
Test status
Simulation time 146378182 ps
CPU time 1.47 seconds
Started Feb 25 01:46:44 PM PST 24
Finished Feb 25 01:46:46 PM PST 24
Peak memory 202396 kb
Host smart-8131bf25-5995-4857-8237-dcb15aa18832
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139085628 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 10.sram_ctrl_tl_intg_err.1139085628
Directory /workspace/10.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.4132573331
Short name T69
Test name
Test status
Simulation time 12811842 ps
CPU time 0.66 seconds
Started Feb 25 01:46:42 PM PST 24
Finished Feb 25 01:46:43 PM PST 24
Peak memory 201880 kb
Host smart-00e23eae-67e0-4aff-bdba-552773ec52ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132573331 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_csr_rw.4132573331
Directory /workspace/11.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2128905679
Short name T67
Test name
Test status
Simulation time 446538965 ps
CPU time 5.93 seconds
Started Feb 25 01:46:44 PM PST 24
Finished Feb 25 01:46:50 PM PST 24
Peak memory 210744 kb
Host smart-4a002b0d-6e21-4dbc-b59f-c1da752629a3
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128905679 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_passthru_mem_tl_intg_err.2128905679
Directory /workspace/11.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.866321450
Short name T901
Test name
Test status
Simulation time 13794768 ps
CPU time 0.71 seconds
Started Feb 25 01:46:42 PM PST 24
Finished Feb 25 01:46:44 PM PST 24
Peak memory 202184 kb
Host smart-06b1c9d3-fb0b-443b-bd3a-ace2a83bb7ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866321450 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.sram_ctrl_same_csr_outstanding.866321450
Directory /workspace/11.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.782676769
Short name T54
Test name
Test status
Simulation time 44664845 ps
CPU time 4.02 seconds
Started Feb 25 01:46:45 PM PST 24
Finished Feb 25 01:46:49 PM PST 24
Peak memory 202444 kb
Host smart-9de1d5fc-4200-4248-875f-32f6e185cd3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782676769 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_tl_errors.782676769
Directory /workspace/11.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.287387948
Short name T61
Test name
Test status
Simulation time 232586064 ps
CPU time 2.51 seconds
Started Feb 25 01:46:40 PM PST 24
Finished Feb 25 01:46:43 PM PST 24
Peak memory 202436 kb
Host smart-90d0e37a-cf65-41b4-9925-33270eac643b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287387948 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.sram_ctrl_tl_intg_err.287387948
Directory /workspace/11.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2539889879
Short name T75
Test name
Test status
Simulation time 25101714 ps
CPU time 0.69 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:47 PM PST 24
Peak memory 202092 kb
Host smart-a2257d46-b69e-4788-892c-bac1571e52d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539889879 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_csr_rw.2539889879
Directory /workspace/12.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1569093943
Short name T900
Test name
Test status
Simulation time 793377698 ps
CPU time 3.33 seconds
Started Feb 25 01:46:42 PM PST 24
Finished Feb 25 01:46:46 PM PST 24
Peak memory 202540 kb
Host smart-72df23cb-2060-4664-a61f-a2d14bac030c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569093943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_passthru_mem_tl_intg_err.1569093943
Directory /workspace/12.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2246989667
Short name T935
Test name
Test status
Simulation time 30438645 ps
CPU time 0.65 seconds
Started Feb 25 01:46:45 PM PST 24
Finished Feb 25 01:46:46 PM PST 24
Peak memory 202224 kb
Host smart-34fb28f1-5212-45e0-8905-a701cae5ce5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246989667 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.sram_ctrl_same_csr_outstanding.2246989667
Directory /workspace/12.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2731166423
Short name T925
Test name
Test status
Simulation time 36615480 ps
CPU time 3.24 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:50 PM PST 24
Peak memory 202448 kb
Host smart-90154cad-187c-4299-bc19-e0df85e326e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731166423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.sram_ctrl_tl_errors.2731166423
Directory /workspace/12.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2355936609
Short name T35
Test name
Test status
Simulation time 180720192 ps
CPU time 1.54 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:48 PM PST 24
Peak memory 202256 kb
Host smart-a768d22d-826b-42f8-8620-8d879d17cea6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355936609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.sram_ctrl_tl_intg_err.2355936609
Directory /workspace/12.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1981746810
Short name T943
Test name
Test status
Simulation time 138588557 ps
CPU time 0.61 seconds
Started Feb 25 01:46:39 PM PST 24
Finished Feb 25 01:46:40 PM PST 24
Peak memory 201232 kb
Host smart-fd2c946b-03f8-4fdc-8c42-cceda7c4fa1e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981746810 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_csr_rw.1981746810
Directory /workspace/13.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2394299964
Short name T921
Test name
Test status
Simulation time 1639905671 ps
CPU time 5.52 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:52 PM PST 24
Peak memory 202456 kb
Host smart-a30e2fcf-20c7-40a1-aa9a-4d3960add930
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394299964 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_passthru_mem_tl_intg_err.2394299964
Directory /workspace/13.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3713826161
Short name T93
Test name
Test status
Simulation time 20649848 ps
CPU time 0.69 seconds
Started Feb 25 01:46:45 PM PST 24
Finished Feb 25 01:46:46 PM PST 24
Peak memory 202208 kb
Host smart-cc5edf12-6857-4e8b-81a5-14525b6d54a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713826161 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.sram_ctrl_same_csr_outstanding.3713826161
Directory /workspace/13.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3138949854
Short name T58
Test name
Test status
Simulation time 439036079 ps
CPU time 4.22 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:51 PM PST 24
Peak memory 202448 kb
Host smart-b9f883e2-8026-44b1-b2e9-d57fff34f0e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138949854 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.sram_ctrl_tl_errors.3138949854
Directory /workspace/13.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3777226383
Short name T928
Test name
Test status
Simulation time 294728135 ps
CPU time 2.03 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:49 PM PST 24
Peak memory 202296 kb
Host smart-3817917a-152e-456a-9907-3c1b160af677
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777226383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 13.sram_ctrl_tl_intg_err.3777226383
Directory /workspace/13.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.614131330
Short name T68
Test name
Test status
Simulation time 21370917 ps
CPU time 0.66 seconds
Started Feb 25 01:46:58 PM PST 24
Finished Feb 25 01:47:00 PM PST 24
Peak memory 202072 kb
Host smart-3236ada6-6d91-4a74-8c3d-4eae1d43ec63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614131330 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 14.sram_ctrl_csr_rw.614131330
Directory /workspace/14.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2974309629
Short name T87
Test name
Test status
Simulation time 1129404876 ps
CPU time 4.99 seconds
Started Feb 25 01:46:59 PM PST 24
Finished Feb 25 01:47:04 PM PST 24
Peak memory 202480 kb
Host smart-165bd957-da1d-47c4-bc01-0e779d97c35c
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974309629 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_passthru_mem_tl_intg_err.2974309629
Directory /workspace/14.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1649850350
Short name T71
Test name
Test status
Simulation time 35048165 ps
CPU time 0.67 seconds
Started Feb 25 01:47:00 PM PST 24
Finished Feb 25 01:47:01 PM PST 24
Peak memory 201696 kb
Host smart-4e4824b7-96bd-4848-b4dd-b743094e23d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649850350 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.sram_ctrl_same_csr_outstanding.1649850350
Directory /workspace/14.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.335366873
Short name T939
Test name
Test status
Simulation time 56149038 ps
CPU time 1.87 seconds
Started Feb 25 01:46:57 PM PST 24
Finished Feb 25 01:47:00 PM PST 24
Peak memory 202488 kb
Host smart-ec6363be-48c4-4408-8a96-377d1ef17498
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335366873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_tl_errors.335366873
Directory /workspace/14.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3137722016
Short name T953
Test name
Test status
Simulation time 77799502 ps
CPU time 1.4 seconds
Started Feb 25 01:47:13 PM PST 24
Finished Feb 25 01:47:14 PM PST 24
Peak memory 210588 kb
Host smart-e69a6d75-e9fa-4f9c-8a1a-26f27784e9d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137722016 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 14.sram_ctrl_tl_intg_err.3137722016
Directory /workspace/14.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.885720345
Short name T916
Test name
Test status
Simulation time 40382983 ps
CPU time 0.64 seconds
Started Feb 25 01:47:04 PM PST 24
Finished Feb 25 01:47:05 PM PST 24
Peak memory 201996 kb
Host smart-50b6a4e9-feb0-46f7-8231-44235129b287
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885720345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 15.sram_ctrl_csr_rw.885720345
Directory /workspace/15.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3763172862
Short name T952
Test name
Test status
Simulation time 1532971392 ps
CPU time 9.84 seconds
Started Feb 25 01:46:58 PM PST 24
Finished Feb 25 01:47:08 PM PST 24
Peak memory 202532 kb
Host smart-f0816287-bddd-4758-9127-a830e27c9871
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763172862 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_passthru_mem_tl_intg_err.3763172862
Directory /workspace/15.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2351073774
Short name T957
Test name
Test status
Simulation time 54157843 ps
CPU time 0.71 seconds
Started Feb 25 01:47:00 PM PST 24
Finished Feb 25 01:47:01 PM PST 24
Peak memory 202152 kb
Host smart-4ee4c915-cb2a-45ab-8785-515ead6a2562
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351073774 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.sram_ctrl_same_csr_outstanding.2351073774
Directory /workspace/15.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1614405403
Short name T911
Test name
Test status
Simulation time 74270532 ps
CPU time 1.95 seconds
Started Feb 25 01:47:11 PM PST 24
Finished Feb 25 01:47:14 PM PST 24
Peak memory 202456 kb
Host smart-a3c9d92e-8f98-452e-927c-58a876d0b86f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614405403 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.sram_ctrl_tl_errors.1614405403
Directory /workspace/15.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2615018740
Short name T946
Test name
Test status
Simulation time 943386699 ps
CPU time 2.53 seconds
Started Feb 25 01:46:57 PM PST 24
Finished Feb 25 01:46:59 PM PST 24
Peak memory 202368 kb
Host smart-8205578c-404a-42a0-94f9-4b0b8969dd16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615018740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 15.sram_ctrl_tl_intg_err.2615018740
Directory /workspace/15.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2930373710
Short name T930
Test name
Test status
Simulation time 14018378 ps
CPU time 0.66 seconds
Started Feb 25 01:47:03 PM PST 24
Finished Feb 25 01:47:04 PM PST 24
Peak memory 202180 kb
Host smart-be68ecf9-fea5-48d1-ab0a-85160ce5e466
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930373710 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_csr_rw.2930373710
Directory /workspace/16.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1668939539
Short name T91
Test name
Test status
Simulation time 411018936 ps
CPU time 4.66 seconds
Started Feb 25 01:47:00 PM PST 24
Finished Feb 25 01:47:05 PM PST 24
Peak memory 202488 kb
Host smart-d78bd941-0b9d-4bb0-a368-a2041ff69383
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668939539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_passthru_mem_tl_intg_err.1668939539
Directory /workspace/16.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1935724735
Short name T94
Test name
Test status
Simulation time 177424847 ps
CPU time 0.71 seconds
Started Feb 25 01:47:00 PM PST 24
Finished Feb 25 01:47:01 PM PST 24
Peak memory 201388 kb
Host smart-25c748e7-465e-4056-8581-d60788febe57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935724735 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.sram_ctrl_same_csr_outstanding.1935724735
Directory /workspace/16.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4283763568
Short name T37
Test name
Test status
Simulation time 81462129 ps
CPU time 3.89 seconds
Started Feb 25 01:46:58 PM PST 24
Finished Feb 25 01:47:02 PM PST 24
Peak memory 202456 kb
Host smart-58fdfffb-df8c-4d8a-83da-e8190a9eebc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283763568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.sram_ctrl_tl_errors.4283763568
Directory /workspace/16.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3636633012
Short name T112
Test name
Test status
Simulation time 304119123 ps
CPU time 2.52 seconds
Started Feb 25 01:47:00 PM PST 24
Finished Feb 25 01:47:03 PM PST 24
Peak memory 202328 kb
Host smart-41de6987-c592-4291-ba9d-6af113c4538d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636633012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 16.sram_ctrl_tl_intg_err.3636633012
Directory /workspace/16.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3499227691
Short name T906
Test name
Test status
Simulation time 72269502 ps
CPU time 0.67 seconds
Started Feb 25 01:47:01 PM PST 24
Finished Feb 25 01:47:02 PM PST 24
Peak memory 202140 kb
Host smart-4ad5ca39-10b9-4fe7-a164-c31f933b6e14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499227691 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_csr_rw.3499227691
Directory /workspace/17.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.630960996
Short name T908
Test name
Test status
Simulation time 1152541020 ps
CPU time 11.12 seconds
Started Feb 25 01:47:13 PM PST 24
Finished Feb 25 01:47:25 PM PST 24
Peak memory 202584 kb
Host smart-05dacdbb-0162-4f23-949f-ff70228dd32e
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630960996 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_passthru_mem_tl_intg_err.630960996
Directory /workspace/17.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.522248136
Short name T903
Test name
Test status
Simulation time 21021414 ps
CPU time 0.67 seconds
Started Feb 25 01:46:58 PM PST 24
Finished Feb 25 01:47:00 PM PST 24
Peak memory 202128 kb
Host smart-bf5abc2b-29c9-4473-9366-ff558a0cce38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522248136 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.sram_ctrl_same_csr_outstanding.522248136
Directory /workspace/17.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.480015092
Short name T910
Test name
Test status
Simulation time 180678491 ps
CPU time 2.61 seconds
Started Feb 25 01:46:56 PM PST 24
Finished Feb 25 01:46:59 PM PST 24
Peak memory 202424 kb
Host smart-a30fb32e-47f3-4c2e-8318-52a837cf7744
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480015092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_tl_errors.480015092
Directory /workspace/17.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3002341346
Short name T944
Test name
Test status
Simulation time 14385588 ps
CPU time 0.68 seconds
Started Feb 25 01:47:00 PM PST 24
Finished Feb 25 01:47:00 PM PST 24
Peak memory 202044 kb
Host smart-407f7426-0869-4cee-865c-ac2ed33702f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002341346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_csr_rw.3002341346
Directory /workspace/18.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.879867581
Short name T77
Test name
Test status
Simulation time 777772702 ps
CPU time 5.76 seconds
Started Feb 25 01:47:00 PM PST 24
Finished Feb 25 01:47:06 PM PST 24
Peak memory 210200 kb
Host smart-6c0f20ee-aacf-44ef-a3b0-2631c5220c33
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879867581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_passthru_mem_tl_intg_err.879867581
Directory /workspace/18.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3787481259
Short name T897
Test name
Test status
Simulation time 22626259 ps
CPU time 0.75 seconds
Started Feb 25 01:47:03 PM PST 24
Finished Feb 25 01:47:04 PM PST 24
Peak memory 202216 kb
Host smart-2ac8b697-0333-4726-a70c-12422a1176e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787481259 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.sram_ctrl_same_csr_outstanding.3787481259
Directory /workspace/18.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1932854871
Short name T954
Test name
Test status
Simulation time 120049174 ps
CPU time 3.92 seconds
Started Feb 25 01:47:08 PM PST 24
Finished Feb 25 01:47:12 PM PST 24
Peak memory 202468 kb
Host smart-920665c5-41d2-4bb8-b726-3cf756ab1c77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932854871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.sram_ctrl_tl_errors.1932854871
Directory /workspace/18.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3228093090
Short name T108
Test name
Test status
Simulation time 77475667 ps
CPU time 1.4 seconds
Started Feb 25 01:47:03 PM PST 24
Finished Feb 25 01:47:05 PM PST 24
Peak memory 202396 kb
Host smart-dd39657f-56e8-4657-8da7-4b13d6eab21a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228093090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 18.sram_ctrl_tl_intg_err.3228093090
Directory /workspace/18.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.822395539
Short name T938
Test name
Test status
Simulation time 99384248 ps
CPU time 0.71 seconds
Started Feb 25 01:46:58 PM PST 24
Finished Feb 25 01:46:59 PM PST 24
Peak memory 202184 kb
Host smart-3b2a5b82-e896-4e44-9683-73b4df6df015
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822395539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 19.sram_ctrl_csr_rw.822395539
Directory /workspace/19.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1768121139
Short name T899
Test name
Test status
Simulation time 19535427 ps
CPU time 0.69 seconds
Started Feb 25 01:47:04 PM PST 24
Finished Feb 25 01:47:05 PM PST 24
Peak memory 200892 kb
Host smart-044e5d99-403a-41fa-8680-7dd4bf292710
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768121139 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.sram_ctrl_same_csr_outstanding.1768121139
Directory /workspace/19.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1125322372
Short name T937
Test name
Test status
Simulation time 550299109 ps
CPU time 4.75 seconds
Started Feb 25 01:47:08 PM PST 24
Finished Feb 25 01:47:13 PM PST 24
Peak memory 202428 kb
Host smart-16cd650e-49e8-4675-96f6-471d9f23943d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125322372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 19.sram_ctrl_tl_errors.1125322372
Directory /workspace/19.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2943374591
Short name T84
Test name
Test status
Simulation time 23386673 ps
CPU time 0.71 seconds
Started Feb 25 01:46:32 PM PST 24
Finished Feb 25 01:46:32 PM PST 24
Peak memory 202160 kb
Host smart-e6a9ed1f-ad05-4dcc-aa00-f6b7ae2b226b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943374591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_aliasing.2943374591
Directory /workspace/2.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2631335413
Short name T922
Test name
Test status
Simulation time 422349595 ps
CPU time 1.39 seconds
Started Feb 25 01:46:38 PM PST 24
Finished Feb 25 01:46:39 PM PST 24
Peak memory 202408 kb
Host smart-a36a6cf4-5e56-4c37-adde-bc12bfc86a7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631335413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_bit_bash.2631335413
Directory /workspace/2.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3379211739
Short name T951
Test name
Test status
Simulation time 38260687 ps
CPU time 0.66 seconds
Started Feb 25 01:46:33 PM PST 24
Finished Feb 25 01:46:34 PM PST 24
Peak memory 201376 kb
Host smart-89cb34f0-2d5d-4e44-8b39-bc3584d8d01a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379211739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.sram_ctrl_csr_hw_reset.3379211739
Directory /workspace/2.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4040393982
Short name T940
Test name
Test status
Simulation time 19231625 ps
CPU time 0.68 seconds
Started Feb 25 01:46:33 PM PST 24
Finished Feb 25 01:46:34 PM PST 24
Peak memory 202120 kb
Host smart-b45967a0-ee00-4d39-93fa-e9362d1031eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040393982 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_csr_rw.4040393982
Directory /workspace/2.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1949257222
Short name T96
Test name
Test status
Simulation time 800371113 ps
CPU time 3.01 seconds
Started Feb 25 01:46:36 PM PST 24
Finished Feb 25 01:46:39 PM PST 24
Peak memory 210640 kb
Host smart-32371fe7-46a0-4ccc-b61d-587fea5ea6ee
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949257222 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_passthru_mem_tl_intg_err.1949257222
Directory /workspace/2.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3846452786
Short name T923
Test name
Test status
Simulation time 25707923 ps
CPU time 0.78 seconds
Started Feb 25 01:46:38 PM PST 24
Finished Feb 25 01:46:39 PM PST 24
Peak memory 202088 kb
Host smart-66e93cf1-ad1b-415a-9ef4-955fe43246d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846452786 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.sram_ctrl_same_csr_outstanding.3846452786
Directory /workspace/2.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1472944296
Short name T931
Test name
Test status
Simulation time 146276613 ps
CPU time 4.77 seconds
Started Feb 25 01:46:29 PM PST 24
Finished Feb 25 01:46:34 PM PST 24
Peak memory 202492 kb
Host smart-4d38c7fa-d4fe-4562-95aa-6561169a5f93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472944296 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.sram_ctrl_tl_errors.1472944296
Directory /workspace/2.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2839706957
Short name T102
Test name
Test status
Simulation time 48122529 ps
CPU time 0.74 seconds
Started Feb 25 01:46:47 PM PST 24
Finished Feb 25 01:46:48 PM PST 24
Peak memory 202024 kb
Host smart-a3ccaed7-e87a-4d17-806f-d3fc505f7fde
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839706957 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_aliasing.2839706957
Directory /workspace/3.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1422379749
Short name T902
Test name
Test status
Simulation time 250741901 ps
CPU time 1.43 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:48 PM PST 24
Peak memory 202356 kb
Host smart-d0eb34d7-05fa-44e4-a8d4-f984e7037f57
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422379749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_bit_bash.1422379749
Directory /workspace/3.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2018847426
Short name T924
Test name
Test status
Simulation time 77866738 ps
CPU time 0.63 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:47 PM PST 24
Peak memory 201992 kb
Host smart-a610ebe4-267e-4e22-a05e-004a9b0693d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018847426 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.sram_ctrl_csr_hw_reset.2018847426
Directory /workspace/3.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1506176409
Short name T95
Test name
Test status
Simulation time 156579124 ps
CPU time 0.72 seconds
Started Feb 25 01:46:45 PM PST 24
Finished Feb 25 01:46:46 PM PST 24
Peak memory 202048 kb
Host smart-27c5866c-bbc5-460d-878d-8f37b66b8dcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506176409 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.sram_ctrl_csr_rw.1506176409
Directory /workspace/3.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.624355251
Short name T65
Test name
Test status
Simulation time 3041767167 ps
CPU time 11.35 seconds
Started Feb 25 01:46:42 PM PST 24
Finished Feb 25 01:46:53 PM PST 24
Peak memory 202624 kb
Host smart-e2f3533b-df12-4b30-880f-1b9789cd169b
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624355251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.sram_ctrl_passthru_mem_tl_intg_err.624355251
Directory /workspace/3.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1105414443
Short name T104
Test name
Test status
Simulation time 42659738 ps
CPU time 0.72 seconds
Started Feb 25 01:46:42 PM PST 24
Finished Feb 25 01:46:44 PM PST 24
Peak memory 202120 kb
Host smart-3ccbd49a-6d3c-4ec0-aaea-ea996852975d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105414443 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.sram_ctrl_same_csr_outstanding.1105414443
Directory /workspace/3.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3708085343
Short name T57
Test name
Test status
Simulation time 2170996011 ps
CPU time 3.88 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:50 PM PST 24
Peak memory 202488 kb
Host smart-d8adbc51-9b23-44b8-906e-1933de704684
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708085343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.sram_ctrl_tl_errors.3708085343
Directory /workspace/3.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2178422562
Short name T949
Test name
Test status
Simulation time 640928462 ps
CPU time 1.67 seconds
Started Feb 25 01:46:40 PM PST 24
Finished Feb 25 01:46:42 PM PST 24
Peak memory 202408 kb
Host smart-936aebeb-62fa-4283-8ee5-af8ab1d4e451
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178422562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.sram_ctrl_tl_intg_err.2178422562
Directory /workspace/3.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2173530146
Short name T918
Test name
Test status
Simulation time 17170712 ps
CPU time 0.75 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:47 PM PST 24
Peak memory 202104 kb
Host smart-d5cf827e-adcb-4b28-a2b6-9845535de102
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173530146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_aliasing.2173530146
Directory /workspace/4.sram_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4107554569
Short name T904
Test name
Test status
Simulation time 207976932 ps
CPU time 1.78 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:48 PM PST 24
Peak memory 202232 kb
Host smart-8adb8eda-df92-4362-85c0-17e35597d0f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107554569 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_bit_bash.4107554569
Directory /workspace/4.sram_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1750288765
Short name T914
Test name
Test status
Simulation time 68588033 ps
CPU time 0.69 seconds
Started Feb 25 01:46:45 PM PST 24
Finished Feb 25 01:46:45 PM PST 24
Peak memory 202188 kb
Host smart-989620b2-9783-4272-ab2c-c9a0500a8b6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750288765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_tes
t +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.sram_ctrl_csr_hw_reset.1750288765
Directory /workspace/4.sram_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3495789673
Short name T915
Test name
Test status
Simulation time 14458839 ps
CPU time 0.71 seconds
Started Feb 25 01:46:40 PM PST 24
Finished Feb 25 01:46:42 PM PST 24
Peak memory 201100 kb
Host smart-e7183fab-78eb-419a-bd03-5d5264d1e6a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495789673 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_csr_rw.3495789673
Directory /workspace/4.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1151878597
Short name T85
Test name
Test status
Simulation time 794799809 ps
CPU time 5.87 seconds
Started Feb 25 01:46:40 PM PST 24
Finished Feb 25 01:46:46 PM PST 24
Peak memory 202516 kb
Host smart-12e323fd-844f-480c-856f-425aefacdda2
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151878597 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.sram_ctrl_passthru_mem_tl_intg_err.1151878597
Directory /workspace/4.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.162067
Short name T920
Test name
Test status
Simulation time 55979871 ps
CPU time 0.7 seconds
Started Feb 25 01:46:43 PM PST 24
Finished Feb 25 01:46:44 PM PST 24
Peak memory 202196 kb
Host smart-26871957-ac58-45b8-b69f-75f36225fa47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.sram_ctrl_same_csr_outstanding.162067
Directory /workspace/4.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2043000405
Short name T913
Test name
Test status
Simulation time 32200357 ps
CPU time 1.89 seconds
Started Feb 25 01:46:44 PM PST 24
Finished Feb 25 01:46:46 PM PST 24
Peak memory 202464 kb
Host smart-fc316082-9e08-400e-a68d-e72686b8d57d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043000405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.sram_ctrl_tl_errors.2043000405
Directory /workspace/4.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.2250297082
Short name T34
Test name
Test status
Simulation time 756772319 ps
CPU time 1.75 seconds
Started Feb 25 01:46:45 PM PST 24
Finished Feb 25 01:46:47 PM PST 24
Peak memory 202380 kb
Host smart-86b6f2e6-2d67-4408-9326-0dcecf9f77c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250297082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 4.sram_ctrl_tl_intg_err.2250297082
Directory /workspace/4.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2073515763
Short name T905
Test name
Test status
Simulation time 46770483 ps
CPU time 0.65 seconds
Started Feb 25 01:46:40 PM PST 24
Finished Feb 25 01:46:41 PM PST 24
Peak memory 201988 kb
Host smart-c98aa7e9-b699-445e-8f14-b2c8bcb2bdd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073515763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_csr_rw.2073515763
Directory /workspace/5.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.4095211450
Short name T76
Test name
Test status
Simulation time 1460760285 ps
CPU time 10.57 seconds
Started Feb 25 01:46:48 PM PST 24
Finished Feb 25 01:46:59 PM PST 24
Peak memory 210736 kb
Host smart-355db290-ee5c-4974-9bfa-91211b5e76d6
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095211450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.sram_ctrl_passthru_mem_tl_intg_err.4095211450
Directory /workspace/5.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2786614840
Short name T97
Test name
Test status
Simulation time 47480576 ps
CPU time 0.77 seconds
Started Feb 25 01:46:39 PM PST 24
Finished Feb 25 01:46:40 PM PST 24
Peak memory 202188 kb
Host smart-8928a01c-4a95-4881-bdf9-dfc380dfb308
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786614840 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.sram_ctrl_same_csr_outstanding.2786614840
Directory /workspace/5.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.659128377
Short name T60
Test name
Test status
Simulation time 65790322 ps
CPU time 3.24 seconds
Started Feb 25 01:46:45 PM PST 24
Finished Feb 25 01:46:49 PM PST 24
Peak memory 202472 kb
Host smart-12449a08-dd0c-440b-a386-ff1bf837711c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659128377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_tl_errors.659128377
Directory /workspace/5.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.950382919
Short name T958
Test name
Test status
Simulation time 209453670 ps
CPU time 2.6 seconds
Started Feb 25 01:46:42 PM PST 24
Finished Feb 25 01:46:45 PM PST 24
Peak memory 202028 kb
Host smart-dfeac784-7f77-4c09-b631-ee89b422183e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950382919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_t
est +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.sram_ctrl_tl_intg_err.950382919
Directory /workspace/5.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2113160490
Short name T70
Test name
Test status
Simulation time 12156312 ps
CPU time 0.64 seconds
Started Feb 25 01:46:44 PM PST 24
Finished Feb 25 01:46:45 PM PST 24
Peak memory 202176 kb
Host smart-c2c064b3-b0d9-41f0-a1b3-b884575a0162
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113160490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_csr_rw.2113160490
Directory /workspace/6.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2487823415
Short name T78
Test name
Test status
Simulation time 1473704288 ps
CPU time 10.34 seconds
Started Feb 25 01:46:42 PM PST 24
Finished Feb 25 01:46:52 PM PST 24
Peak memory 202564 kb
Host smart-a7f39f47-f20b-4e82-8197-037060d6c1ea
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487823415 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_passthru_mem_tl_intg_err.2487823415
Directory /workspace/6.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2247203637
Short name T909
Test name
Test status
Simulation time 16586504 ps
CPU time 0.76 seconds
Started Feb 25 01:46:42 PM PST 24
Finished Feb 25 01:46:43 PM PST 24
Peak memory 202212 kb
Host smart-3cb29c8a-32b9-4830-9798-7364dbeaaa4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247203637 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.sram_ctrl_same_csr_outstanding.2247203637
Directory /workspace/6.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.158551557
Short name T934
Test name
Test status
Simulation time 269047478 ps
CPU time 2.86 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:49 PM PST 24
Peak memory 210600 kb
Host smart-b8e21e82-226d-4ea7-8d2b-c6ab1b19497a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158551557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TES
T_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_tl_errors.158551557
Directory /workspace/6.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3317522377
Short name T933
Test name
Test status
Simulation time 295795379 ps
CPU time 2.55 seconds
Started Feb 25 01:46:40 PM PST 24
Finished Feb 25 01:46:42 PM PST 24
Peak memory 202396 kb
Host smart-2705f0f6-5e0b-4a21-bca9-ec13e98faa88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317522377 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 6.sram_ctrl_tl_intg_err.3317522377
Directory /workspace/6.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1934747212
Short name T932
Test name
Test status
Simulation time 11810487 ps
CPU time 0.65 seconds
Started Feb 25 01:46:42 PM PST 24
Finished Feb 25 01:46:43 PM PST 24
Peak memory 201088 kb
Host smart-c4811ee3-0932-4ece-bfa3-aee7e8ece0f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934747212 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_csr_rw.1934747212
Directory /workspace/7.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1294977945
Short name T948
Test name
Test status
Simulation time 473565010 ps
CPU time 11.18 seconds
Started Feb 25 01:46:45 PM PST 24
Finished Feb 25 01:46:56 PM PST 24
Peak memory 202564 kb
Host smart-6cd1d15f-f57b-47e5-813a-9f4fa06fd9ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294977945 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.sram_ctrl_passthru_mem_tl_intg_err.1294977945
Directory /workspace/7.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4230274503
Short name T950
Test name
Test status
Simulation time 90924403 ps
CPU time 0.82 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:47 PM PST 24
Peak memory 202092 kb
Host smart-04442696-75e0-4a82-955d-ecc4d02a1fe7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230274503 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.sram_ctrl_same_csr_outstanding.4230274503
Directory /workspace/7.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1542690210
Short name T53
Test name
Test status
Simulation time 40516525 ps
CPU time 3.52 seconds
Started Feb 25 01:46:40 PM PST 24
Finished Feb 25 01:46:44 PM PST 24
Peak memory 202412 kb
Host smart-f2079cd6-5ce8-4d48-9918-1db8bb036dc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542690210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.sram_ctrl_tl_errors.1542690210
Directory /workspace/7.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2553653210
Short name T110
Test name
Test status
Simulation time 252003907 ps
CPU time 2.41 seconds
Started Feb 25 01:46:44 PM PST 24
Finished Feb 25 01:46:47 PM PST 24
Peak memory 202380 kb
Host smart-712185a8-110a-4317-b213-eff050325009
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553653210 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 7.sram_ctrl_tl_intg_err.2553653210
Directory /workspace/7.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1038958793
Short name T912
Test name
Test status
Simulation time 18005655 ps
CPU time 0.66 seconds
Started Feb 25 01:46:40 PM PST 24
Finished Feb 25 01:46:41 PM PST 24
Peak memory 202120 kb
Host smart-38347f9e-2783-4055-aacd-422347cfa09b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038958793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_csr_rw.1038958793
Directory /workspace/8.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1997503785
Short name T66
Test name
Test status
Simulation time 276336636 ps
CPU time 3.37 seconds
Started Feb 25 01:46:47 PM PST 24
Finished Feb 25 01:46:50 PM PST 24
Peak memory 202564 kb
Host smart-6dee6206-389d-48ad-8e54-820825828f30
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997503785 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_passthru_mem_tl_intg_err.1997503785
Directory /workspace/8.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.499791276
Short name T898
Test name
Test status
Simulation time 16690218 ps
CPU time 0.74 seconds
Started Feb 25 01:46:46 PM PST 24
Finished Feb 25 01:46:47 PM PST 24
Peak memory 202144 kb
Host smart-563d84ae-1d6f-49fe-8176-98be218bfff1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499791276 -assert nopostproc +UVM_TESTNAME=sram_ct
rl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.sram_ctrl_same_csr_outstanding.499791276
Directory /workspace/8.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1199370753
Short name T105
Test name
Test status
Simulation time 401244807 ps
CPU time 3.32 seconds
Started Feb 25 01:46:47 PM PST 24
Finished Feb 25 01:46:51 PM PST 24
Peak memory 202492 kb
Host smart-ebbf4c6c-2073-4734-a632-f594ef261bba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199370753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 8.sram_ctrl_tl_errors.1199370753
Directory /workspace/8.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.4126857429
Short name T955
Test name
Test status
Simulation time 201922728 ps
CPU time 2.35 seconds
Started Feb 25 01:46:40 PM PST 24
Finished Feb 25 01:46:42 PM PST 24
Peak memory 202416 kb
Host smart-caec976a-5a29-40ba-abde-b0860a0fd037
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126857429 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.sram_ctrl_tl_intg_err.4126857429
Directory /workspace/8.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2044143384
Short name T896
Test name
Test status
Simulation time 33330886 ps
CPU time 0.66 seconds
Started Feb 25 01:46:47 PM PST 24
Finished Feb 25 01:46:48 PM PST 24
Peak memory 202172 kb
Host smart-401638dc-65ae-4d76-893d-ce1784781907
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044143384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_csr_rw.2044143384
Directory /workspace/9.sram_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1234629861
Short name T64
Test name
Test status
Simulation time 1568900609 ps
CPU time 5.39 seconds
Started Feb 25 01:46:41 PM PST 24
Finished Feb 25 01:46:47 PM PST 24
Peak memory 202588 kb
Host smart-c966ef1b-cf27-4e14-b92a-2225781e71ff
User root
Command /workspace/cover_reg_top/simv +run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY
=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234629861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_passthru_mem_tl_intg_err.1234629861
Directory /workspace/9.sram_ctrl_passthru_mem_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4205707703
Short name T917
Test name
Test status
Simulation time 53022823 ps
CPU time 0.71 seconds
Started Feb 25 01:46:45 PM PST 24
Finished Feb 25 01:46:46 PM PST 24
Peak memory 202132 kb
Host smart-fb16f303-f917-41ee-b5ad-a5386a28d1f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VER
BOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205707703 -assert nopostproc +UVM_TESTNAME=sram_c
trl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.sram_ctrl_same_csr_outstanding.4205707703
Directory /workspace/9.sram_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2363973119
Short name T942
Test name
Test status
Simulation time 181350800 ps
CPU time 1.96 seconds
Started Feb 25 01:46:39 PM PST 24
Finished Feb 25 01:46:41 PM PST 24
Peak memory 202388 kb
Host smart-3c9f05b6-6e9b-4b4e-aa8a-f4a169261d48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363973119 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.sram_ctrl_tl_errors.2363973119
Directory /workspace/9.sram_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1939909020
Short name T106
Test name
Test status
Simulation time 96541530 ps
CPU time 1.43 seconds
Started Feb 25 01:46:45 PM PST 24
Finished Feb 25 01:46:47 PM PST 24
Peak memory 202388 kb
Host smart-b172ce2f-2027-4d2b-b886-9800fa2029f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939909020 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_
test +UVM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.sram_ctrl_tl_intg_err.1939909020
Directory /workspace/9.sram_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1282500391
Short name T343
Test name
Test status
Simulation time 15945992875 ps
CPU time 649.56 seconds
Started Feb 25 02:45:32 PM PST 24
Finished Feb 25 02:56:22 PM PST 24
Peak memory 373484 kb
Host smart-f623c15e-886f-43aa-9b60-3cacba46ae03
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282500391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 0.sram_ctrl_access_during_key_req.1282500391
Directory /workspace/0.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/0.sram_ctrl_alert_test.2888824014
Short name T530
Test name
Test status
Simulation time 36709791 ps
CPU time 0.64 seconds
Started Feb 25 02:45:34 PM PST 24
Finished Feb 25 02:45:34 PM PST 24
Peak memory 202448 kb
Host smart-bee04893-c19d-49ec-bb04-3eda0c9a4818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888824014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.sram_ctrl_alert_test.2888824014
Directory /workspace/0.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sram_ctrl_bijection.3467913960
Short name T169
Test name
Test status
Simulation time 1794159888 ps
CPU time 57.44 seconds
Started Feb 25 02:45:38 PM PST 24
Finished Feb 25 02:46:35 PM PST 24
Peak memory 202588 kb
Host smart-f5863f21-f9f4-46be-960c-ec4ed07c7df9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467913960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_bijection.
3467913960
Directory /workspace/0.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/0.sram_ctrl_executable.3914549149
Short name T113
Test name
Test status
Simulation time 3757651940 ps
CPU time 963.67 seconds
Started Feb 25 02:45:31 PM PST 24
Finished Feb 25 03:01:35 PM PST 24
Peak memory 369264 kb
Host smart-22a09eb6-da0a-456c-b616-6cf925b440ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914549149 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_executabl
e.3914549149
Directory /workspace/0.sram_ctrl_executable/latest

Test location /workspace/coverage/default/0.sram_ctrl_max_throughput.2774461136
Short name T458
Test name
Test status
Simulation time 407970798 ps
CPU time 13.15 seconds
Started Feb 25 02:45:30 PM PST 24
Finished Feb 25 02:45:43 PM PST 24
Peak memory 253900 kb
Host smart-c55067be-17a2-427b-96ff-b942230b1a5c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774461136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 0.sram_ctrl_max_throughput.2774461136
Directory /workspace/0.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_partial_access.3731748530
Short name T346
Test name
Test status
Simulation time 373242347 ps
CPU time 4.81 seconds
Started Feb 25 02:45:30 PM PST 24
Finished Feb 25 02:45:35 PM PST 24
Peak memory 211792 kb
Host smart-30ce22d3-a720-44c2-93b5-039d40f20682
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731748530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_mem_partial_access.3731748530
Directory /workspace/0.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_mem_walk.879794131
Short name T860
Test name
Test status
Simulation time 137373749 ps
CPU time 7.92 seconds
Started Feb 25 02:45:39 PM PST 24
Finished Feb 25 02:45:47 PM PST 24
Peak memory 202564 kb
Host smart-f44272e4-f082-4397-b013-0d958d6bb213
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879794131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_
mem_walk.879794131
Directory /workspace/0.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/0.sram_ctrl_multiple_keys.4243824714
Short name T117
Test name
Test status
Simulation time 50531248204 ps
CPU time 975.74 seconds
Started Feb 25 02:45:47 PM PST 24
Finished Feb 25 03:02:05 PM PST 24
Peak memory 373416 kb
Host smart-a0616e4a-142b-4dc0-94dd-98bee31a4b26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243824714 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_multip
le_keys.4243824714
Directory /workspace/0.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access.1661260085
Short name T119
Test name
Test status
Simulation time 3075167650 ps
CPU time 33.02 seconds
Started Feb 25 02:45:39 PM PST 24
Finished Feb 25 02:46:12 PM PST 24
Peak memory 279212 kb
Host smart-1f9e27df-bc3a-4133-875d-afb3592ba342
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661260085 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.s
ram_ctrl_partial_access.1661260085
Directory /workspace/0.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.136782776
Short name T520
Test name
Test status
Simulation time 54473605074 ps
CPU time 362.18 seconds
Started Feb 25 02:45:46 PM PST 24
Finished Feb 25 02:51:50 PM PST 24
Peak memory 202656 kb
Host smart-afe39782-e896-4026-853f-bd7950d19f3e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136782776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 0.sram_ctrl_partial_access_b2b.136782776
Directory /workspace/0.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/0.sram_ctrl_ram_cfg.2905763126
Short name T736
Test name
Test status
Simulation time 29486648 ps
CPU time 1.12 seconds
Started Feb 25 02:45:30 PM PST 24
Finished Feb 25 02:45:32 PM PST 24
Peak memory 202820 kb
Host smart-a2b3a454-90c2-4682-b47f-14fc19621f6d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905763126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_ram_cfg.2905763126
Directory /workspace/0.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/0.sram_ctrl_regwen.3693069873
Short name T281
Test name
Test status
Simulation time 48262004720 ps
CPU time 1381.49 seconds
Started Feb 25 02:45:47 PM PST 24
Finished Feb 25 03:08:51 PM PST 24
Peak memory 374316 kb
Host smart-b9840b4b-ead6-402d-89c0-d1b7d7b5a08c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693069873 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_regwen.3693069873
Directory /workspace/0.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/0.sram_ctrl_smoke.4053279789
Short name T819
Test name
Test status
Simulation time 2035016909 ps
CPU time 70.74 seconds
Started Feb 25 02:45:50 PM PST 24
Finished Feb 25 02:47:01 PM PST 24
Peak memory 325700 kb
Host smart-b6cd6318-d6b2-428c-8cbd-09397fbe340a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053279789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sram_ctrl_smoke.4053279789
Directory /workspace/0.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sram_ctrl_stress_pipeline.4233655803
Short name T101
Test name
Test status
Simulation time 4875064745 ps
CPU time 210.63 seconds
Started Feb 25 02:45:32 PM PST 24
Finished Feb 25 02:49:03 PM PST 24
Peak memory 202704 kb
Host smart-59b164a4-82f3-4b04-978f-43011181fafd
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233655803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.sram_ctrl_stress_pipeline.4233655803
Directory /workspace/0.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1741619910
Short name T368
Test name
Test status
Simulation time 69521360 ps
CPU time 4.63 seconds
Started Feb 25 02:45:47 PM PST 24
Finished Feb 25 02:45:53 PM PST 24
Peak memory 218972 kb
Host smart-e81cc9c2-714f-4742-a3f8-139d37ef5aee
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741619910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sram_ctrl_throughput_w_partial_write.1741619910
Directory /workspace/0.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/1.sram_ctrl_access_during_key_req.310379255
Short name T149
Test name
Test status
Simulation time 2818215316 ps
CPU time 230.86 seconds
Started Feb 25 02:45:40 PM PST 24
Finished Feb 25 02:49:31 PM PST 24
Peak memory 370372 kb
Host smart-8e7f39e9-cdbd-489a-96c6-0e5d3bfe08db
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310379255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.sram_ctrl_access_during_key_req.310379255
Directory /workspace/1.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/1.sram_ctrl_alert_test.795562935
Short name T304
Test name
Test status
Simulation time 22286047 ps
CPU time 0.67 seconds
Started Feb 25 02:45:43 PM PST 24
Finished Feb 25 02:45:44 PM PST 24
Peak memory 201676 kb
Host smart-a7422e3f-fabc-4174-a68a-53a2a8105b44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795562935 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.sram_ctrl_alert_test.795562935
Directory /workspace/1.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sram_ctrl_bijection.2391708116
Short name T603
Test name
Test status
Simulation time 2650570895 ps
CPU time 43.14 seconds
Started Feb 25 02:45:50 PM PST 24
Finished Feb 25 02:46:34 PM PST 24
Peak memory 202672 kb
Host smart-0676ab38-dac0-40db-b557-0f910759a519
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391708116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_bijection.
2391708116
Directory /workspace/1.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/1.sram_ctrl_executable.2537918733
Short name T291
Test name
Test status
Simulation time 2642285687 ps
CPU time 263.49 seconds
Started Feb 25 02:45:35 PM PST 24
Finished Feb 25 02:49:59 PM PST 24
Peak memory 367096 kb
Host smart-a2dc07c5-188a-4452-8b8b-5a0d25838bec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537918733 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_executabl
e.2537918733
Directory /workspace/1.sram_ctrl_executable/latest

Test location /workspace/coverage/default/1.sram_ctrl_lc_escalation.2645330152
Short name T707
Test name
Test status
Simulation time 192936807 ps
CPU time 3.04 seconds
Started Feb 25 02:45:47 PM PST 24
Finished Feb 25 02:45:53 PM PST 24
Peak memory 213244 kb
Host smart-51f3b223-422d-453c-ae4d-38e2bfcea09b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645330152 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_lc_esc
alation.2645330152
Directory /workspace/1.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/1.sram_ctrl_max_throughput.1410039001
Short name T820
Test name
Test status
Simulation time 616362400 ps
CPU time 70.99 seconds
Started Feb 25 02:45:32 PM PST 24
Finished Feb 25 02:46:43 PM PST 24
Peak memory 317792 kb
Host smart-48e923ef-313b-4d32-9aa0-1a803e10f081
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410039001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_max_throughput.1410039001
Directory /workspace/1.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1874073102
Short name T276
Test name
Test status
Simulation time 293297860 ps
CPU time 5.25 seconds
Started Feb 25 02:45:29 PM PST 24
Finished Feb 25 02:45:35 PM PST 24
Peak memory 210836 kb
Host smart-9c148cfe-ca74-467c-a07b-3954920a2633
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874073102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_mem_partial_access.1874073102
Directory /workspace/1.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_mem_walk.3808981140
Short name T724
Test name
Test status
Simulation time 698833142 ps
CPU time 6.07 seconds
Started Feb 25 02:45:41 PM PST 24
Finished Feb 25 02:45:47 PM PST 24
Peak memory 202560 kb
Host smart-87a9dcb6-b269-46c6-bcd6-4937b6450b05
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808981140 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl
_mem_walk.3808981140
Directory /workspace/1.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/1.sram_ctrl_multiple_keys.1324755557
Short name T748
Test name
Test status
Simulation time 13182341718 ps
CPU time 1108.6 seconds
Started Feb 25 02:45:33 PM PST 24
Finished Feb 25 03:04:02 PM PST 24
Peak memory 375136 kb
Host smart-64abdc7d-3668-4d5f-9abe-c54422847b22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324755557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_multip
le_keys.1324755557
Directory /workspace/1.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access.2493100131
Short name T607
Test name
Test status
Simulation time 181119116 ps
CPU time 92.58 seconds
Started Feb 25 02:45:43 PM PST 24
Finished Feb 25 02:47:16 PM PST 24
Peak memory 340768 kb
Host smart-70daa335-851d-4cbf-b1a0-b98b26789234
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493100131 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.s
ram_ctrl_partial_access.2493100131
Directory /workspace/1.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.932319176
Short name T561
Test name
Test status
Simulation time 38055511271 ps
CPU time 514.63 seconds
Started Feb 25 02:45:33 PM PST 24
Finished Feb 25 02:54:08 PM PST 24
Peak memory 202692 kb
Host smart-0be69bcb-94cf-4728-8a5d-41fbcb8e54ea
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932319176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 1.sram_ctrl_partial_access_b2b.932319176
Directory /workspace/1.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/1.sram_ctrl_ram_cfg.1458114503
Short name T386
Test name
Test status
Simulation time 37275687 ps
CPU time 0.88 seconds
Started Feb 25 02:45:30 PM PST 24
Finished Feb 25 02:45:31 PM PST 24
Peak memory 202564 kb
Host smart-92fdb45f-b2ba-47c8-b5a7-2e7acb486326
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458114503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_ram_cfg.1458114503
Directory /workspace/1.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/1.sram_ctrl_regwen.3669901815
Short name T604
Test name
Test status
Simulation time 11626808803 ps
CPU time 779.11 seconds
Started Feb 25 02:45:41 PM PST 24
Finished Feb 25 02:58:40 PM PST 24
Peak memory 373692 kb
Host smart-a4a1c891-06ed-485e-a033-bfd067647bde
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669901815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_regwen.3669901815
Directory /workspace/1.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/1.sram_ctrl_sec_cm.442355656
Short name T21
Test name
Test status
Simulation time 681401406 ps
CPU time 2.76 seconds
Started Feb 25 02:45:48 PM PST 24
Finished Feb 25 02:45:53 PM PST 24
Peak memory 220844 kb
Host smart-5cb4e91e-9419-481f-a8ad-16b45f176e86
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442355656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_sec_cm.442355656
Directory /workspace/1.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sram_ctrl_smoke.307976558
Short name T359
Test name
Test status
Simulation time 155332385 ps
CPU time 12.94 seconds
Started Feb 25 02:45:31 PM PST 24
Finished Feb 25 02:45:44 PM PST 24
Peak memory 254188 kb
Host smart-d77843fc-d387-41ba-b5b2-be7fc4b713cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307976558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sram_ctrl_smoke.307976558
Directory /workspace/1.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_all.1645641080
Short name T699
Test name
Test status
Simulation time 40549389181 ps
CPU time 2736.22 seconds
Started Feb 25 02:45:34 PM PST 24
Finished Feb 25 03:31:11 PM PST 24
Peak memory 373428 kb
Host smart-c83163d4-a949-4021-abaa-323b83cf04c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645641080 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 1.sram_ctrl_stress_all.1645641080
Directory /workspace/1.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3886454949
Short name T804
Test name
Test status
Simulation time 7239211031 ps
CPU time 345.29 seconds
Started Feb 25 02:45:32 PM PST 24
Finished Feb 25 02:51:18 PM PST 24
Peak memory 202628 kb
Host smart-9998f0a8-ac8a-4325-96f3-63d238e1bb65
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886454949 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.sram_ctrl_stress_pipeline.3886454949
Directory /workspace/1.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.766562510
Short name T851
Test name
Test status
Simulation time 326408678 ps
CPU time 34.13 seconds
Started Feb 25 02:45:37 PM PST 24
Finished Feb 25 02:46:11 PM PST 24
Peak memory 283576 kb
Host smart-458ba0fc-367a-479c-9ac3-bfdc99ad9642
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766562510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sram_ctrl_throughput_w_partial_write.766562510
Directory /workspace/1.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/10.sram_ctrl_access_during_key_req.3862399793
Short name T229
Test name
Test status
Simulation time 4189912582 ps
CPU time 285.68 seconds
Started Feb 25 02:46:16 PM PST 24
Finished Feb 25 02:51:02 PM PST 24
Peak memory 347752 kb
Host smart-1fe9fb10-a131-47ec-a975-5d9979dfa13f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862399793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 10.sram_ctrl_access_during_key_req.3862399793
Directory /workspace/10.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/10.sram_ctrl_alert_test.18110711
Short name T419
Test name
Test status
Simulation time 18564784 ps
CPU time 0.67 seconds
Started Feb 25 02:46:08 PM PST 24
Finished Feb 25 02:46:09 PM PST 24
Peak memory 201724 kb
Host smart-56f84bee-db20-4f13-bf00-e6092c2c1cf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18110711 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_alert_test.18110711
Directory /workspace/10.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sram_ctrl_bijection.2636772041
Short name T788
Test name
Test status
Simulation time 2219964720 ps
CPU time 35.08 seconds
Started Feb 25 02:46:16 PM PST 24
Finished Feb 25 02:46:51 PM PST 24
Peak memory 202680 kb
Host smart-6818f105-4b39-4b90-94d5-6a69eb0381d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636772041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_bijection
.2636772041
Directory /workspace/10.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/10.sram_ctrl_executable.1853805088
Short name T321
Test name
Test status
Simulation time 12708307308 ps
CPU time 944.66 seconds
Started Feb 25 02:46:10 PM PST 24
Finished Feb 25 03:01:55 PM PST 24
Peak memory 372340 kb
Host smart-cdc2b160-356f-4e68-957a-3863c6d06316
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853805088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_executab
le.1853805088
Directory /workspace/10.sram_ctrl_executable/latest

Test location /workspace/coverage/default/10.sram_ctrl_lc_escalation.3248595036
Short name T437
Test name
Test status
Simulation time 1101211883 ps
CPU time 6.86 seconds
Started Feb 25 02:46:11 PM PST 24
Finished Feb 25 02:46:18 PM PST 24
Peak memory 210776 kb
Host smart-ea5c428f-c70a-4c7f-b66c-eace6672131f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248595036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_lc_es
calation.3248595036
Directory /workspace/10.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/10.sram_ctrl_max_throughput.3741606997
Short name T152
Test name
Test status
Simulation time 206184053 ps
CPU time 5.6 seconds
Started Feb 25 02:46:11 PM PST 24
Finished Feb 25 02:46:17 PM PST 24
Peak memory 224620 kb
Host smart-194e9698-3c87-4046-8210-f9e609ea28bf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741606997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sram_ctrl_max_throughput.3741606997
Directory /workspace/10.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_partial_access.4084875014
Short name T645
Test name
Test status
Simulation time 299015728 ps
CPU time 4.97 seconds
Started Feb 25 02:46:05 PM PST 24
Finished Feb 25 02:46:10 PM PST 24
Peak memory 210820 kb
Host smart-e2b9d7c1-83a4-4af2-ac85-560ea5b6359c
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084875014 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_mem_partial_access.4084875014
Directory /workspace/10.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_mem_walk.1291563042
Short name T570
Test name
Test status
Simulation time 3254839026 ps
CPU time 11.37 seconds
Started Feb 25 02:46:12 PM PST 24
Finished Feb 25 02:46:23 PM PST 24
Peak memory 202608 kb
Host smart-c5148b35-9f8b-4f1c-b5de-087f675ade3a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291563042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctr
l_mem_walk.1291563042
Directory /workspace/10.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/10.sram_ctrl_multiple_keys.3380624035
Short name T815
Test name
Test status
Simulation time 12587788546 ps
CPU time 711.01 seconds
Started Feb 25 02:46:08 PM PST 24
Finished Feb 25 02:57:59 PM PST 24
Peak memory 354996 kb
Host smart-7709b5cf-afdc-45fb-b65c-df4b85bd30e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380624035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_multi
ple_keys.3380624035
Directory /workspace/10.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access.1225828514
Short name T777
Test name
Test status
Simulation time 1081757767 ps
CPU time 48.56 seconds
Started Feb 25 02:46:10 PM PST 24
Finished Feb 25 02:46:59 PM PST 24
Peak memory 298612 kb
Host smart-c4faf826-ac2d-4556-96e9-be9826b72933
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225828514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
sram_ctrl_partial_access.1225828514
Directory /workspace/10.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.667537878
Short name T395
Test name
Test status
Simulation time 18494602987 ps
CPU time 249.36 seconds
Started Feb 25 02:46:06 PM PST 24
Finished Feb 25 02:50:15 PM PST 24
Peak memory 202692 kb
Host smart-dc1d426f-8dad-4acf-ba25-92faf04d61de
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667537878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 10.sram_ctrl_partial_access_b2b.667537878
Directory /workspace/10.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/10.sram_ctrl_ram_cfg.807517974
Short name T522
Test name
Test status
Simulation time 38791304 ps
CPU time 0.88 seconds
Started Feb 25 02:46:15 PM PST 24
Finished Feb 25 02:46:16 PM PST 24
Peak memory 202616 kb
Host smart-6b246d86-0f02-4bcf-b891-0109762a9ff2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807517974 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_ram_cfg.807517974
Directory /workspace/10.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/10.sram_ctrl_regwen.1126727161
Short name T833
Test name
Test status
Simulation time 2487153606 ps
CPU time 411.85 seconds
Started Feb 25 02:46:27 PM PST 24
Finished Feb 25 02:53:20 PM PST 24
Peak memory 371976 kb
Host smart-3b3cef46-c3de-4837-b378-212ca8194ede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126727161 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_regwen.1126727161
Directory /workspace/10.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/10.sram_ctrl_smoke.329139792
Short name T242
Test name
Test status
Simulation time 364829746 ps
CPU time 155.93 seconds
Started Feb 25 02:46:18 PM PST 24
Finished Feb 25 02:48:54 PM PST 24
Peak memory 363876 kb
Host smart-90835d72-c33c-4f06-80c4-8862c38a49ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329139792 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sram_ctrl_smoke.329139792
Directory /workspace/10.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_all.778895279
Short name T597
Test name
Test status
Simulation time 66908170347 ps
CPU time 5515.53 seconds
Started Feb 25 02:46:10 PM PST 24
Finished Feb 25 04:18:06 PM PST 24
Peak memory 375544 kb
Host smart-ac210cbf-f2b8-4e2d-8ea4-5569e777c302
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778895279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 10.sram_ctrl_stress_all.778895279
Directory /workspace/10.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sram_ctrl_stress_pipeline.2688020536
Short name T599
Test name
Test status
Simulation time 8483641033 ps
CPU time 210.33 seconds
Started Feb 25 02:46:11 PM PST 24
Finished Feb 25 02:49:41 PM PST 24
Peak memory 202688 kb
Host smart-9296ace9-fc0c-4478-8214-c704b7f8b697
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688020536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.sram_ctrl_stress_pipeline.2688020536
Directory /workspace/10.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2838757089
Short name T497
Test name
Test status
Simulation time 292311005 ps
CPU time 155.17 seconds
Started Feb 25 02:46:10 PM PST 24
Finished Feb 25 02:48:45 PM PST 24
Peak memory 354920 kb
Host smart-150211b6-a110-4f1c-ba6d-fc686ef33adf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838757089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sram_ctrl_throughput_w_partial_write.2838757089
Directory /workspace/10.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1796179717
Short name T406
Test name
Test status
Simulation time 3170144452 ps
CPU time 1372.59 seconds
Started Feb 25 02:46:16 PM PST 24
Finished Feb 25 03:09:09 PM PST 24
Peak memory 373444 kb
Host smart-fe0ea3de-c090-4c5d-adaa-fae93e678438
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796179717 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 11.sram_ctrl_access_during_key_req.1796179717
Directory /workspace/11.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/11.sram_ctrl_alert_test.3701310121
Short name T283
Test name
Test status
Simulation time 14373274 ps
CPU time 0.64 seconds
Started Feb 25 02:46:14 PM PST 24
Finished Feb 25 02:46:15 PM PST 24
Peak memory 201504 kb
Host smart-fd11471e-1e40-4885-b45f-6bb1c7f3a14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701310121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.sram_ctrl_alert_test.3701310121
Directory /workspace/11.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.sram_ctrl_bijection.708921399
Short name T712
Test name
Test status
Simulation time 1049052255 ps
CPU time 61.71 seconds
Started Feb 25 02:46:12 PM PST 24
Finished Feb 25 02:47:14 PM PST 24
Peak memory 202540 kb
Host smart-221fb983-6679-4b60-bf6d-a0b73018fc06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708921399 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_bijection.
708921399
Directory /workspace/11.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/11.sram_ctrl_executable.1438912517
Short name T622
Test name
Test status
Simulation time 2609993442 ps
CPU time 845.51 seconds
Started Feb 25 02:46:18 PM PST 24
Finished Feb 25 03:00:23 PM PST 24
Peak memory 358116 kb
Host smart-50a781a8-9669-40ea-938c-1ed32f3abf26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438912517 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_executab
le.1438912517
Directory /workspace/11.sram_ctrl_executable/latest

Test location /workspace/coverage/default/11.sram_ctrl_lc_escalation.2199297608
Short name T661
Test name
Test status
Simulation time 1253655050 ps
CPU time 9.61 seconds
Started Feb 25 02:46:27 PM PST 24
Finished Feb 25 02:46:37 PM PST 24
Peak memory 202640 kb
Host smart-0faf2b4d-a2da-4ec9-b963-4249ed790fb1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199297608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_lc_es
calation.2199297608
Directory /workspace/11.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/11.sram_ctrl_max_throughput.3974828719
Short name T287
Test name
Test status
Simulation time 1756775654 ps
CPU time 84.58 seconds
Started Feb 25 02:46:15 PM PST 24
Finished Feb 25 02:47:39 PM PST 24
Peak memory 326996 kb
Host smart-ac371a6a-4770-4f55-9108-b72613c5e7a3
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974828719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sram_ctrl_max_throughput.3974828719
Directory /workspace/11.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_partial_access.700549354
Short name T72
Test name
Test status
Simulation time 92490521 ps
CPU time 3.05 seconds
Started Feb 25 02:46:23 PM PST 24
Finished Feb 25 02:46:26 PM PST 24
Peak memory 210760 kb
Host smart-96348eaa-e682-45ae-912b-4f40f85a4b13
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700549354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.sram_ctrl_mem_partial_access.700549354
Directory /workspace/11.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_mem_walk.3742751611
Short name T429
Test name
Test status
Simulation time 223625510 ps
CPU time 8.23 seconds
Started Feb 25 02:46:18 PM PST 24
Finished Feb 25 02:46:27 PM PST 24
Peak memory 202556 kb
Host smart-f6e83b0e-20c6-45cb-8d19-fc3962bf37f3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742751611 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctr
l_mem_walk.3742751611
Directory /workspace/11.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/11.sram_ctrl_multiple_keys.2967904599
Short name T360
Test name
Test status
Simulation time 13740923043 ps
CPU time 1280.85 seconds
Started Feb 25 02:46:19 PM PST 24
Finished Feb 25 03:07:40 PM PST 24
Peak memory 369092 kb
Host smart-64d89529-b124-4c77-b20a-ed8363ef3ceb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967904599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_multi
ple_keys.2967904599
Directory /workspace/11.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access.3511987892
Short name T48
Test name
Test status
Simulation time 1055575184 ps
CPU time 42.37 seconds
Started Feb 25 02:46:18 PM PST 24
Finished Feb 25 02:47:00 PM PST 24
Peak memory 306708 kb
Host smart-f6dba99f-0730-494a-bd31-f1bbcf53ea59
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511987892 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
sram_ctrl_partial_access.3511987892
Directory /workspace/11.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.178369359
Short name T440
Test name
Test status
Simulation time 44279319820 ps
CPU time 443.53 seconds
Started Feb 25 02:46:19 PM PST 24
Finished Feb 25 02:53:43 PM PST 24
Peak memory 202604 kb
Host smart-0ebb4236-b0e6-4937-b557-5eb79a6ffb0e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178369359 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 11.sram_ctrl_partial_access_b2b.178369359
Directory /workspace/11.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/11.sram_ctrl_regwen.1285998624
Short name T286
Test name
Test status
Simulation time 12211809861 ps
CPU time 1040.09 seconds
Started Feb 25 02:46:30 PM PST 24
Finished Feb 25 03:03:51 PM PST 24
Peak memory 370164 kb
Host smart-967748b6-aae7-4f63-956d-75bfaefca15b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285998624 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_regwen.1285998624
Directory /workspace/11.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/11.sram_ctrl_smoke.2936671799
Short name T473
Test name
Test status
Simulation time 2055902700 ps
CPU time 9.64 seconds
Started Feb 25 02:46:09 PM PST 24
Finished Feb 25 02:46:19 PM PST 24
Peak memory 202600 kb
Host smart-49a74dcb-1d6b-4f9a-8133-9529eae358db
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936671799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sram_ctrl_smoke.2936671799
Directory /workspace/11.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sram_ctrl_stress_pipeline.583751697
Short name T535
Test name
Test status
Simulation time 8262491790 ps
CPU time 192.65 seconds
Started Feb 25 02:46:12 PM PST 24
Finished Feb 25 02:49:25 PM PST 24
Peak memory 202704 kb
Host smart-9eeab5dc-d6f1-480d-a29e-4dbca58acc60
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583751697 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.sram_ctrl_stress_pipeline.583751697
Directory /workspace/11.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2383777195
Short name T842
Test name
Test status
Simulation time 380840054 ps
CPU time 37.73 seconds
Started Feb 25 02:46:10 PM PST 24
Finished Feb 25 02:46:48 PM PST 24
Peak memory 287500 kb
Host smart-148b7d29-019f-462d-a490-50d6abfe7cc0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383777195 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sram_ctrl_throughput_w_partial_write.2383777195
Directory /workspace/11.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2097242435
Short name T176
Test name
Test status
Simulation time 10483328526 ps
CPU time 1219.63 seconds
Started Feb 25 02:46:14 PM PST 24
Finished Feb 25 03:06:34 PM PST 24
Peak memory 370008 kb
Host smart-851beb7a-0462-4a31-a248-da9cc42ec431
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097242435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 12.sram_ctrl_access_during_key_req.2097242435
Directory /workspace/12.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/12.sram_ctrl_alert_test.3547049322
Short name T461
Test name
Test status
Simulation time 16710141 ps
CPU time 0.65 seconds
Started Feb 25 02:46:13 PM PST 24
Finished Feb 25 02:46:14 PM PST 24
Peak memory 202436 kb
Host smart-595eb711-fa69-4eee-9442-e7355330d08e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547049322 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.sram_ctrl_alert_test.3547049322
Directory /workspace/12.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sram_ctrl_bijection.3649830203
Short name T504
Test name
Test status
Simulation time 2986165286 ps
CPU time 47.7 seconds
Started Feb 25 02:46:17 PM PST 24
Finished Feb 25 02:47:05 PM PST 24
Peak memory 202688 kb
Host smart-3af0b6e2-fa08-4d3e-8c98-09459ed2b746
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649830203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_bijection
.3649830203
Directory /workspace/12.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/12.sram_ctrl_executable.2820617425
Short name T673
Test name
Test status
Simulation time 12432125813 ps
CPU time 939.61 seconds
Started Feb 25 02:46:30 PM PST 24
Finished Feb 25 03:02:10 PM PST 24
Peak memory 373368 kb
Host smart-a14ce270-2fd7-47b6-9bcb-1ab52191153c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820617425 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_executab
le.2820617425
Directory /workspace/12.sram_ctrl_executable/latest

Test location /workspace/coverage/default/12.sram_ctrl_lc_escalation.345535695
Short name T289
Test name
Test status
Simulation time 311990467 ps
CPU time 4.3 seconds
Started Feb 25 02:46:17 PM PST 24
Finished Feb 25 02:46:21 PM PST 24
Peak memory 202628 kb
Host smart-cc7ea6e9-98c4-4d01-b79c-7b4b473ff087
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345535695 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_lc_esc
alation.345535695
Directory /workspace/12.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/12.sram_ctrl_max_throughput.1473514300
Short name T885
Test name
Test status
Simulation time 117761401 ps
CPU time 92.95 seconds
Started Feb 25 02:46:16 PM PST 24
Finished Feb 25 02:47:49 PM PST 24
Peak memory 326452 kb
Host smart-ab5b517c-9e1b-4629-ad4a-39f741840862
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473514300 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 12.sram_ctrl_max_throughput.1473514300
Directory /workspace/12.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1127011526
Short name T80
Test name
Test status
Simulation time 154781740 ps
CPU time 5.39 seconds
Started Feb 25 02:46:16 PM PST 24
Finished Feb 25 02:46:22 PM PST 24
Peak memory 210856 kb
Host smart-17802a4e-7203-4c9e-bd9a-4e1b74531a1b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127011526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_mem_partial_access.1127011526
Directory /workspace/12.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_mem_walk.718825952
Short name T385
Test name
Test status
Simulation time 153852931 ps
CPU time 7.66 seconds
Started Feb 25 02:46:30 PM PST 24
Finished Feb 25 02:46:38 PM PST 24
Peak memory 202572 kb
Host smart-37acd5af-f640-4229-9d37-b2320fa1d3ec
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718825952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl
_mem_walk.718825952
Directory /workspace/12.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/12.sram_ctrl_multiple_keys.438926406
Short name T493
Test name
Test status
Simulation time 46984626941 ps
CPU time 437.74 seconds
Started Feb 25 02:46:14 PM PST 24
Finished Feb 25 02:53:32 PM PST 24
Peak memory 368836 kb
Host smart-7f6738b9-3fb1-46a3-8493-e955454ccb2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438926406 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_multip
le_keys.438926406
Directory /workspace/12.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access.3401502997
Short name T672
Test name
Test status
Simulation time 430710924 ps
CPU time 53.81 seconds
Started Feb 25 02:46:13 PM PST 24
Finished Feb 25 02:47:06 PM PST 24
Peak memory 302836 kb
Host smart-c213ae05-e3f5-41e5-bd8c-344fd46b46e2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401502997 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
sram_ctrl_partial_access.3401502997
Directory /workspace/12.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.832977580
Short name T335
Test name
Test status
Simulation time 3108949559 ps
CPU time 217 seconds
Started Feb 25 02:46:22 PM PST 24
Finished Feb 25 02:49:59 PM PST 24
Peak memory 202700 kb
Host smart-e318a3fb-a920-4b20-9308-f1f39e975698
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832977580 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 12.sram_ctrl_partial_access_b2b.832977580
Directory /workspace/12.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/12.sram_ctrl_ram_cfg.3123752347
Short name T188
Test name
Test status
Simulation time 75378426 ps
CPU time 1.07 seconds
Started Feb 25 02:46:29 PM PST 24
Finished Feb 25 02:46:30 PM PST 24
Peak memory 202836 kb
Host smart-5d383736-cc3d-4d80-a649-12ccbe08e82d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123752347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_ram_cfg.3123752347
Directory /workspace/12.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/12.sram_ctrl_smoke.2583711639
Short name T612
Test name
Test status
Simulation time 3730339274 ps
CPU time 17.37 seconds
Started Feb 25 02:46:16 PM PST 24
Finished Feb 25 02:46:34 PM PST 24
Peak memory 202664 kb
Host smart-f35ffe46-955b-4c2f-9cd0-27a32b98c2e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583711639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sram_ctrl_smoke.2583711639
Directory /workspace/12.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_all.2374540500
Short name T745
Test name
Test status
Simulation time 199639145847 ps
CPU time 4453.88 seconds
Started Feb 25 02:46:18 PM PST 24
Finished Feb 25 04:00:32 PM PST 24
Peak memory 382620 kb
Host smart-c69e3696-2142-4079-b1ba-c2f7659fc9dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374540500 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 12.sram_ctrl_stress_all.2374540500
Directory /workspace/12.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2082213267
Short name T302
Test name
Test status
Simulation time 877011258 ps
CPU time 79.32 seconds
Started Feb 25 02:46:16 PM PST 24
Finished Feb 25 02:47:35 PM PST 24
Peak memory 202624 kb
Host smart-5eaadd18-2ead-40ed-a93c-257d757519ff
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082213267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.sram_ctrl_stress_pipeline.2082213267
Directory /workspace/12.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3265844245
Short name T881
Test name
Test status
Simulation time 377253730 ps
CPU time 34.76 seconds
Started Feb 25 02:46:30 PM PST 24
Finished Feb 25 02:47:05 PM PST 24
Peak memory 284324 kb
Host smart-fd0bc61c-875f-4330-bb04-14cace46d666
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265844245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sram_ctrl_throughput_w_partial_write.3265844245
Directory /workspace/12.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/13.sram_ctrl_access_during_key_req.2518488481
Short name T859
Test name
Test status
Simulation time 6990731235 ps
CPU time 1416.77 seconds
Started Feb 25 02:46:26 PM PST 24
Finished Feb 25 03:10:03 PM PST 24
Peak memory 369776 kb
Host smart-31a178c2-b198-4d50-8bba-a9968d198c21
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518488481 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 13.sram_ctrl_access_during_key_req.2518488481
Directory /workspace/13.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/13.sram_ctrl_bijection.913525015
Short name T807
Test name
Test status
Simulation time 6181799763 ps
CPU time 59.51 seconds
Started Feb 25 02:46:26 PM PST 24
Finished Feb 25 02:47:26 PM PST 24
Peak memory 202560 kb
Host smart-0be878ac-762b-44c0-bac0-f90998e74614
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913525015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_bijection.
913525015
Directory /workspace/13.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/13.sram_ctrl_executable.3167976317
Short name T605
Test name
Test status
Simulation time 10966801059 ps
CPU time 962.4 seconds
Started Feb 25 02:46:29 PM PST 24
Finished Feb 25 03:02:31 PM PST 24
Peak memory 374452 kb
Host smart-abbaf8f6-d5a5-4d3a-9468-296eefc1bbd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167976317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_executab
le.3167976317
Directory /workspace/13.sram_ctrl_executable/latest

Test location /workspace/coverage/default/13.sram_ctrl_max_throughput.462888760
Short name T710
Test name
Test status
Simulation time 402366769 ps
CPU time 58.47 seconds
Started Feb 25 02:46:19 PM PST 24
Finished Feb 25 02:47:17 PM PST 24
Peak memory 320108 kb
Host smart-772d468d-5908-46dc-9718-03431f244c2a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462888760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.sram_ctrl_max_throughput.462888760
Directory /workspace/13.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_partial_access.1585708512
Short name T2
Test name
Test status
Simulation time 195873685 ps
CPU time 2.99 seconds
Started Feb 25 02:46:26 PM PST 24
Finished Feb 25 02:46:30 PM PST 24
Peak memory 210608 kb
Host smart-94e4d15a-6aea-40cf-a8f7-e467d51b2a71
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585708512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_mem_partial_access.1585708512
Directory /workspace/13.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_mem_walk.860809440
Short name T197
Test name
Test status
Simulation time 485858439 ps
CPU time 8.67 seconds
Started Feb 25 02:46:27 PM PST 24
Finished Feb 25 02:46:36 PM PST 24
Peak memory 202556 kb
Host smart-1232d628-7648-4509-ab41-b734762aeedf
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860809440 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl
_mem_walk.860809440
Directory /workspace/13.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/13.sram_ctrl_multiple_keys.3873055536
Short name T709
Test name
Test status
Simulation time 81863325745 ps
CPU time 864.85 seconds
Started Feb 25 02:46:30 PM PST 24
Finished Feb 25 03:00:56 PM PST 24
Peak memory 374064 kb
Host smart-258d6089-ec75-450e-9491-d610bbbed874
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873055536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_multi
ple_keys.3873055536
Directory /workspace/13.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access.218335289
Short name T619
Test name
Test status
Simulation time 1302788637 ps
CPU time 17.26 seconds
Started Feb 25 02:46:26 PM PST 24
Finished Feb 25 02:46:44 PM PST 24
Peak memory 202532 kb
Host smart-67b51f80-b532-4249-9889-f07f67f5172f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218335289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.s
ram_ctrl_partial_access.218335289
Directory /workspace/13.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3379898469
Short name T118
Test name
Test status
Simulation time 41218253072 ps
CPU time 469.82 seconds
Started Feb 25 02:46:13 PM PST 24
Finished Feb 25 02:54:03 PM PST 24
Peak memory 202628 kb
Host smart-3ad5aa0f-d41e-4b46-98b9-c7b0fffeb751
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379898469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 13.sram_ctrl_partial_access_b2b.3379898469
Directory /workspace/13.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/13.sram_ctrl_ram_cfg.3736659596
Short name T164
Test name
Test status
Simulation time 31072905 ps
CPU time 0.9 seconds
Started Feb 25 02:46:14 PM PST 24
Finished Feb 25 02:46:15 PM PST 24
Peak memory 202600 kb
Host smart-00c5525c-219d-4317-8e6e-a67e74b29692
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736659596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_ram_cfg.3736659596
Directory /workspace/13.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/13.sram_ctrl_regwen.2946486000
Short name T688
Test name
Test status
Simulation time 2702501660 ps
CPU time 374.64 seconds
Started Feb 25 02:46:29 PM PST 24
Finished Feb 25 02:52:44 PM PST 24
Peak memory 349880 kb
Host smart-9e2d389e-ea77-4cc0-a0b4-0a07f50fce35
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946486000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_regwen.2946486000
Directory /workspace/13.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/13.sram_ctrl_smoke.3056745819
Short name T866
Test name
Test status
Simulation time 1878531090 ps
CPU time 129.06 seconds
Started Feb 25 02:46:23 PM PST 24
Finished Feb 25 02:48:33 PM PST 24
Peak memory 365104 kb
Host smart-e55f7364-315c-4627-b924-0560a9a64881
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056745819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sram_ctrl_smoke.3056745819
Directory /workspace/13.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sram_ctrl_stress_pipeline.2733780579
Short name T824
Test name
Test status
Simulation time 2827140105 ps
CPU time 257.88 seconds
Started Feb 25 02:46:23 PM PST 24
Finished Feb 25 02:50:41 PM PST 24
Peak memory 202396 kb
Host smart-8b45891a-ce42-4c87-ac7f-ef5fd319a311
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733780579 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.sram_ctrl_stress_pipeline.2733780579
Directory /workspace/13.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1212606176
Short name T378
Test name
Test status
Simulation time 35588098 ps
CPU time 1.77 seconds
Started Feb 25 02:46:26 PM PST 24
Finished Feb 25 02:46:28 PM PST 24
Peak memory 210728 kb
Host smart-682fa0c1-5e6b-4b7b-9b9b-a07e892595fe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212606176 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sram_ctrl_throughput_w_partial_write.1212606176
Directory /workspace/13.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1358373865
Short name T435
Test name
Test status
Simulation time 1988363644 ps
CPU time 658.69 seconds
Started Feb 25 02:46:25 PM PST 24
Finished Feb 25 02:57:24 PM PST 24
Peak memory 370236 kb
Host smart-09a55e45-3f30-419a-864c-9f3e2c7e1a50
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358373865 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 14.sram_ctrl_access_during_key_req.1358373865
Directory /workspace/14.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/14.sram_ctrl_alert_test.397719800
Short name T274
Test name
Test status
Simulation time 40649906 ps
CPU time 0.64 seconds
Started Feb 25 02:46:27 PM PST 24
Finished Feb 25 02:46:28 PM PST 24
Peak memory 201504 kb
Host smart-85d9d705-a08b-4abd-80dd-b8b80ee3f460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397719800 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.sram_ctrl_alert_test.397719800
Directory /workspace/14.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sram_ctrl_bijection.3145706483
Short name T839
Test name
Test status
Simulation time 1665964835 ps
CPU time 28.84 seconds
Started Feb 25 02:46:23 PM PST 24
Finished Feb 25 02:46:52 PM PST 24
Peak memory 202580 kb
Host smart-4a7c2396-4531-4d7d-910a-7b4bb04d2d5a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145706483 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_bijection
.3145706483
Directory /workspace/14.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/14.sram_ctrl_executable.4149024928
Short name T602
Test name
Test status
Simulation time 30855947983 ps
CPU time 551.35 seconds
Started Feb 25 02:46:23 PM PST 24
Finished Feb 25 02:55:34 PM PST 24
Peak memory 355324 kb
Host smart-13d7e405-9365-4ffc-80f1-b74362df2b05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149024928 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_executab
le.4149024928
Directory /workspace/14.sram_ctrl_executable/latest

Test location /workspace/coverage/default/14.sram_ctrl_lc_escalation.2077413855
Short name T223
Test name
Test status
Simulation time 1049849839 ps
CPU time 7.69 seconds
Started Feb 25 02:46:22 PM PST 24
Finished Feb 25 02:46:30 PM PST 24
Peak memory 202628 kb
Host smart-a3616a6d-8863-4a06-b2ff-43a6a1a64331
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077413855 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_lc_es
calation.2077413855
Directory /workspace/14.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/14.sram_ctrl_max_throughput.564377249
Short name T486
Test name
Test status
Simulation time 582954213 ps
CPU time 127.09 seconds
Started Feb 25 02:46:22 PM PST 24
Finished Feb 25 02:48:29 PM PST 24
Peak memory 364400 kb
Host smart-630cb752-0133-47ab-b7e7-03a2b23fe718
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564377249 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.sram_ctrl_max_throughput.564377249
Directory /workspace/14.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2705802404
Short name T235
Test name
Test status
Simulation time 174975628 ps
CPU time 5.01 seconds
Started Feb 25 02:46:27 PM PST 24
Finished Feb 25 02:46:33 PM PST 24
Peak memory 218928 kb
Host smart-d2c5f193-927b-4f44-96f9-c745ae32758b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705802404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_mem_partial_access.2705802404
Directory /workspace/14.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_mem_walk.4025001404
Short name T512
Test name
Test status
Simulation time 2402459744 ps
CPU time 10.85 seconds
Started Feb 25 02:46:23 PM PST 24
Finished Feb 25 02:46:34 PM PST 24
Peak memory 202640 kb
Host smart-3acdb0fa-d96d-4a70-b238-3c7d4e112b42
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025001404 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctr
l_mem_walk.4025001404
Directory /workspace/14.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/14.sram_ctrl_multiple_keys.1798184315
Short name T358
Test name
Test status
Simulation time 13031711328 ps
CPU time 426.53 seconds
Started Feb 25 02:46:26 PM PST 24
Finished Feb 25 02:53:33 PM PST 24
Peak memory 333904 kb
Host smart-a73a5470-cb1c-4a58-b1f2-de9886a5074c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798184315 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_multi
ple_keys.1798184315
Directory /workspace/14.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access.182825861
Short name T307
Test name
Test status
Simulation time 1138209046 ps
CPU time 9.88 seconds
Started Feb 25 02:46:33 PM PST 24
Finished Feb 25 02:46:44 PM PST 24
Peak memory 202568 kb
Host smart-83dc6e6e-0c19-4499-8320-0a004d6df634
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182825861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.s
ram_ctrl_partial_access.182825861
Directory /workspace/14.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2155878462
Short name T731
Test name
Test status
Simulation time 10396973306 ps
CPU time 358.66 seconds
Started Feb 25 02:46:30 PM PST 24
Finished Feb 25 02:52:29 PM PST 24
Peak memory 202676 kb
Host smart-993e1009-beb5-449b-9264-4893b45a69bd
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155878462 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 14.sram_ctrl_partial_access_b2b.2155878462
Directory /workspace/14.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/14.sram_ctrl_ram_cfg.422135155
Short name T769
Test name
Test status
Simulation time 26759203 ps
CPU time 1.11 seconds
Started Feb 25 02:46:21 PM PST 24
Finished Feb 25 02:46:22 PM PST 24
Peak memory 202820 kb
Host smart-e8586012-92ba-4926-bb4d-d53014263551
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422135155 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_ram_cfg.422135155
Directory /workspace/14.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/14.sram_ctrl_regwen.2955417473
Short name T718
Test name
Test status
Simulation time 1512047761 ps
CPU time 441.04 seconds
Started Feb 25 02:46:22 PM PST 24
Finished Feb 25 02:53:43 PM PST 24
Peak memory 372488 kb
Host smart-c454eadb-7090-4b0f-8744-e4a6e6121fec
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955417473 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_regwen.2955417473
Directory /workspace/14.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/14.sram_ctrl_smoke.826542342
Short name T337
Test name
Test status
Simulation time 193792847 ps
CPU time 5.65 seconds
Started Feb 25 02:46:30 PM PST 24
Finished Feb 25 02:46:36 PM PST 24
Peak memory 202644 kb
Host smart-faa0302e-acba-4353-8d84-ebce5fa2235b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826542342 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sram_ctrl_smoke.826542342
Directory /workspace/14.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_all.3591344145
Short name T689
Test name
Test status
Simulation time 14477437023 ps
CPU time 533.52 seconds
Started Feb 25 02:46:34 PM PST 24
Finished Feb 25 02:55:28 PM PST 24
Peak memory 359284 kb
Host smart-b1cecffb-9d82-49b2-8635-a0ddb4464625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591344145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 14.sram_ctrl_stress_all.3591344145
Directory /workspace/14.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2816113848
Short name T451
Test name
Test status
Simulation time 2028319162 ps
CPU time 186.59 seconds
Started Feb 25 02:46:31 PM PST 24
Finished Feb 25 02:49:39 PM PST 24
Peak memory 202640 kb
Host smart-be23b64c-0185-4870-8bec-5b2b008ddd75
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816113848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.sram_ctrl_stress_pipeline.2816113848
Directory /workspace/14.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.3099564216
Short name T858
Test name
Test status
Simulation time 587276772 ps
CPU time 124.85 seconds
Started Feb 25 02:46:24 PM PST 24
Finished Feb 25 02:48:29 PM PST 24
Peak memory 359932 kb
Host smart-0db5d917-18e9-4c6f-a589-578c51fc72ab
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099564216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 14.sram_ctrl_throughput_w_partial_write.3099564216
Directory /workspace/14.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/15.sram_ctrl_access_during_key_req.403646674
Short name T338
Test name
Test status
Simulation time 3332525357 ps
CPU time 548.6 seconds
Started Feb 25 02:46:24 PM PST 24
Finished Feb 25 02:55:33 PM PST 24
Peak memory 341740 kb
Host smart-9d2c9c93-a2a2-4316-a6cb-5542aa0b546e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403646674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 15.sram_ctrl_access_during_key_req.403646674
Directory /workspace/15.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/15.sram_ctrl_alert_test.186987041
Short name T814
Test name
Test status
Simulation time 13036925 ps
CPU time 0.66 seconds
Started Feb 25 02:46:31 PM PST 24
Finished Feb 25 02:46:32 PM PST 24
Peak memory 201680 kb
Host smart-2f44ac50-fc66-427b-99b3-370491be8a15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186987041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.sram_ctrl_alert_test.186987041
Directory /workspace/15.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sram_ctrl_bijection.2314051182
Short name T1
Test name
Test status
Simulation time 3343354021 ps
CPU time 54.58 seconds
Started Feb 25 02:46:24 PM PST 24
Finished Feb 25 02:47:19 PM PST 24
Peak memory 202724 kb
Host smart-50a800d9-c88f-47bb-88e2-bcd371dc90ca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314051182 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_bijection
.2314051182
Directory /workspace/15.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/15.sram_ctrl_executable.3684576574
Short name T319
Test name
Test status
Simulation time 12231782670 ps
CPU time 1509.53 seconds
Started Feb 25 02:46:23 PM PST 24
Finished Feb 25 03:11:33 PM PST 24
Peak memory 364204 kb
Host smart-e04c02a0-793d-49ef-b4fb-606820ce7b8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684576574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_executab
le.3684576574
Directory /workspace/15.sram_ctrl_executable/latest

Test location /workspace/coverage/default/15.sram_ctrl_lc_escalation.3182538830
Short name T484
Test name
Test status
Simulation time 748114491 ps
CPU time 4.83 seconds
Started Feb 25 02:46:28 PM PST 24
Finished Feb 25 02:46:33 PM PST 24
Peak memory 202568 kb
Host smart-546c9db2-55fe-4a12-9a74-8492d37e8679
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182538830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_lc_es
calation.3182538830
Directory /workspace/15.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/15.sram_ctrl_max_throughput.540362392
Short name T750
Test name
Test status
Simulation time 1232536566 ps
CPU time 27.31 seconds
Started Feb 25 02:46:30 PM PST 24
Finished Feb 25 02:46:59 PM PST 24
Peak memory 273756 kb
Host smart-74ebf03d-1680-4835-8d54-a5571aa935d9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540362392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.sram_ctrl_max_throughput.540362392
Directory /workspace/15.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_partial_access.552893405
Short name T740
Test name
Test status
Simulation time 174205143 ps
CPU time 5.5 seconds
Started Feb 25 02:46:32 PM PST 24
Finished Feb 25 02:46:39 PM PST 24
Peak memory 210816 kb
Host smart-7873fd08-b54a-4814-8321-1daf3676ab89
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552893405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.sram_ctrl_mem_partial_access.552893405
Directory /workspace/15.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_mem_walk.3580160203
Short name T243
Test name
Test status
Simulation time 215584086 ps
CPU time 4.43 seconds
Started Feb 25 02:46:23 PM PST 24
Finished Feb 25 02:46:27 PM PST 24
Peak memory 202604 kb
Host smart-3fc20b4d-5b33-4dd9-9143-297e09f1c009
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580160203 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctr
l_mem_walk.3580160203
Directory /workspace/15.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/15.sram_ctrl_multiple_keys.685768482
Short name T630
Test name
Test status
Simulation time 13357192892 ps
CPU time 915.37 seconds
Started Feb 25 02:46:27 PM PST 24
Finished Feb 25 03:01:44 PM PST 24
Peak memory 375460 kb
Host smart-c9804836-ce10-4d7c-9fb3-8abb35b2b212
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685768482 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_multip
le_keys.685768482
Directory /workspace/15.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access.3989991551
Short name T659
Test name
Test status
Simulation time 1352607183 ps
CPU time 6.84 seconds
Started Feb 25 02:46:23 PM PST 24
Finished Feb 25 02:46:31 PM PST 24
Peak memory 202600 kb
Host smart-3278e32f-6f75-4daa-9760-72214548eec1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989991551 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
sram_ctrl_partial_access.3989991551
Directory /workspace/15.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.4291299507
Short name T228
Test name
Test status
Simulation time 37355419461 ps
CPU time 344.26 seconds
Started Feb 25 02:46:22 PM PST 24
Finished Feb 25 02:52:07 PM PST 24
Peak memory 202652 kb
Host smart-ff5fc00a-359b-488a-bfe5-dc317d4c965e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291299507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 15.sram_ctrl_partial_access_b2b.4291299507
Directory /workspace/15.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/15.sram_ctrl_ram_cfg.2500047924
Short name T303
Test name
Test status
Simulation time 27238689 ps
CPU time 0.85 seconds
Started Feb 25 02:46:25 PM PST 24
Finished Feb 25 02:46:26 PM PST 24
Peak memory 202580 kb
Host smart-8fd4cfbd-566f-492f-999e-edc886a75ea2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500047924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_ram_cfg.2500047924
Directory /workspace/15.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/15.sram_ctrl_regwen.502844807
Short name T157
Test name
Test status
Simulation time 11373012314 ps
CPU time 584.14 seconds
Started Feb 25 02:46:23 PM PST 24
Finished Feb 25 02:56:07 PM PST 24
Peak memory 373500 kb
Host smart-8c85b7ec-a66c-4bb4-9bfc-c91646ad7004
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502844807 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_regwen.502844807
Directory /workspace/15.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/15.sram_ctrl_smoke.2566946558
Short name T277
Test name
Test status
Simulation time 211542340 ps
CPU time 34.29 seconds
Started Feb 25 02:46:22 PM PST 24
Finished Feb 25 02:46:56 PM PST 24
Peak memory 293704 kb
Host smart-1d934f9e-a90a-4c4f-855b-edbf5b3928e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566946558 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sram_ctrl_smoke.2566946558
Directory /workspace/15.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_all.1183759556
Short name T388
Test name
Test status
Simulation time 59372652163 ps
CPU time 4008.54 seconds
Started Feb 25 02:46:32 PM PST 24
Finished Feb 25 03:53:22 PM PST 24
Peak memory 382628 kb
Host smart-f7365cbc-8909-43ca-a9cf-fea3466621e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183759556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 15.sram_ctrl_stress_all.1183759556
Directory /workspace/15.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sram_ctrl_stress_pipeline.1215491752
Short name T282
Test name
Test status
Simulation time 4175614948 ps
CPU time 390.76 seconds
Started Feb 25 02:46:24 PM PST 24
Finished Feb 25 02:52:55 PM PST 24
Peak memory 202696 kb
Host smart-ed44e8be-d0d5-46eb-82f4-b243c4ae532f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215491752 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.sram_ctrl_stress_pipeline.1215491752
Directory /workspace/15.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2157429319
Short name T502
Test name
Test status
Simulation time 354995249 ps
CPU time 22.25 seconds
Started Feb 25 02:46:27 PM PST 24
Finished Feb 25 02:46:50 PM PST 24
Peak memory 284340 kb
Host smart-d8f8c350-f70b-42dd-89d9-856462b21baa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157429319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sram_ctrl_throughput_w_partial_write.2157429319
Directory /workspace/15.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/16.sram_ctrl_access_during_key_req.2472515763
Short name T305
Test name
Test status
Simulation time 2777168983 ps
CPU time 1102.19 seconds
Started Feb 25 02:46:33 PM PST 24
Finished Feb 25 03:04:56 PM PST 24
Peak memory 372408 kb
Host smart-5fdc0fe3-3d40-4d3d-a88d-3e0cba83593e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472515763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_access_during_key_req.2472515763
Directory /workspace/16.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/16.sram_ctrl_alert_test.1628547746
Short name T259
Test name
Test status
Simulation time 76071790 ps
CPU time 0.66 seconds
Started Feb 25 02:46:34 PM PST 24
Finished Feb 25 02:46:35 PM PST 24
Peak memory 201680 kb
Host smart-d96f3997-3c8e-4bb3-b5fa-3555d22efec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628547746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.sram_ctrl_alert_test.1628547746
Directory /workspace/16.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sram_ctrl_bijection.1068383596
Short name T822
Test name
Test status
Simulation time 18984447419 ps
CPU time 50.78 seconds
Started Feb 25 02:46:33 PM PST 24
Finished Feb 25 02:47:25 PM PST 24
Peak memory 202612 kb
Host smart-5abb852d-2cd6-4eec-9dc3-93fc0e41f666
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068383596 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_bijection
.1068383596
Directory /workspace/16.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/16.sram_ctrl_executable.127237725
Short name T3
Test name
Test status
Simulation time 8454662307 ps
CPU time 205.68 seconds
Started Feb 25 02:46:30 PM PST 24
Finished Feb 25 02:49:57 PM PST 24
Peak memory 339888 kb
Host smart-c69297e8-1d00-44cb-b6bb-6de28a356d37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127237725 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_executabl
e.127237725
Directory /workspace/16.sram_ctrl_executable/latest

Test location /workspace/coverage/default/16.sram_ctrl_lc_escalation.4261415277
Short name T326
Test name
Test status
Simulation time 2050178517 ps
CPU time 7.96 seconds
Started Feb 25 02:46:33 PM PST 24
Finished Feb 25 02:46:42 PM PST 24
Peak memory 210796 kb
Host smart-8ce2d34c-f1ad-4f96-b2a2-03b7d14bde22
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261415277 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_lc_es
calation.4261415277
Directory /workspace/16.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/16.sram_ctrl_max_throughput.1729935173
Short name T646
Test name
Test status
Simulation time 239755121 ps
CPU time 59 seconds
Started Feb 25 02:46:38 PM PST 24
Finished Feb 25 02:47:37 PM PST 24
Peak memory 348124 kb
Host smart-66e5fe64-558b-4878-95e9-343c81a2de39
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729935173 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 16.sram_ctrl_max_throughput.1729935173
Directory /workspace/16.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_partial_access.3881964787
Short name T739
Test name
Test status
Simulation time 270516717 ps
CPU time 2.86 seconds
Started Feb 25 02:46:31 PM PST 24
Finished Feb 25 02:46:35 PM PST 24
Peak memory 211756 kb
Host smart-05d672eb-47bb-4fd8-b958-9dd6054231ea
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881964787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_mem_partial_access.3881964787
Directory /workspace/16.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_mem_walk.2839012625
Short name T313
Test name
Test status
Simulation time 2617180005 ps
CPU time 10.97 seconds
Started Feb 25 02:46:31 PM PST 24
Finished Feb 25 02:46:43 PM PST 24
Peak memory 202596 kb
Host smart-af172e79-bc6a-4fe5-8642-9396c0a57bfc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839012625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctr
l_mem_walk.2839012625
Directory /workspace/16.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/16.sram_ctrl_multiple_keys.2746956609
Short name T394
Test name
Test status
Simulation time 12552409952 ps
CPU time 363.65 seconds
Started Feb 25 02:46:34 PM PST 24
Finished Feb 25 02:52:38 PM PST 24
Peak memory 348960 kb
Host smart-86ef43b0-779b-4f81-88f0-1843764480c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746956609 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_multi
ple_keys.2746956609
Directory /workspace/16.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access.2819477372
Short name T649
Test name
Test status
Simulation time 607785916 ps
CPU time 57.06 seconds
Started Feb 25 02:46:31 PM PST 24
Finished Feb 25 02:47:28 PM PST 24
Peak memory 307828 kb
Host smart-da925d19-86f9-4205-aa23-dfa83611e563
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819477372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
sram_ctrl_partial_access.2819477372
Directory /workspace/16.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.50883177
Short name T143
Test name
Test status
Simulation time 29239560768 ps
CPU time 193.6 seconds
Started Feb 25 02:46:30 PM PST 24
Finished Feb 25 02:49:45 PM PST 24
Peak memory 202652 kb
Host smart-66e1ead9-f056-473a-b6bf-f3acb2c83c60
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50883177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TE
ST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 16.sram_ctrl_partial_access_b2b.50883177
Directory /workspace/16.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/16.sram_ctrl_ram_cfg.1339643937
Short name T781
Test name
Test status
Simulation time 54725612 ps
CPU time 0.86 seconds
Started Feb 25 02:46:33 PM PST 24
Finished Feb 25 02:46:35 PM PST 24
Peak memory 202572 kb
Host smart-92c154da-8754-46ce-90d7-da3a34f2c1cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339643937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_ram_cfg.1339643937
Directory /workspace/16.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/16.sram_ctrl_regwen.1954594383
Short name T601
Test name
Test status
Simulation time 2813200581 ps
CPU time 1307.36 seconds
Started Feb 25 02:46:31 PM PST 24
Finished Feb 25 03:08:19 PM PST 24
Peak memory 374068 kb
Host smart-a5553c51-f96f-4921-a39c-5ef792cb700d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954594383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_regwen.1954594383
Directory /workspace/16.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/16.sram_ctrl_smoke.3506670930
Short name T269
Test name
Test status
Simulation time 111419442 ps
CPU time 45.85 seconds
Started Feb 25 02:46:35 PM PST 24
Finished Feb 25 02:47:21 PM PST 24
Peak memory 311500 kb
Host smart-639b806e-20d8-49a5-86ae-094564443be8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506670930 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sram_ctrl_smoke.3506670930
Directory /workspace/16.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_all.3504862528
Short name T874
Test name
Test status
Simulation time 46698642844 ps
CPU time 4717.94 seconds
Started Feb 25 02:46:41 PM PST 24
Finished Feb 25 04:05:19 PM PST 24
Peak memory 374116 kb
Host smart-dc506af6-004d-4bcd-9277-15f59990fbdd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504862528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 16.sram_ctrl_stress_all.3504862528
Directory /workspace/16.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sram_ctrl_stress_pipeline.2025883834
Short name T227
Test name
Test status
Simulation time 7196779400 ps
CPU time 171.64 seconds
Started Feb 25 02:46:31 PM PST 24
Finished Feb 25 02:49:24 PM PST 24
Peak memory 202696 kb
Host smart-b182ede1-e71c-4bcd-be2d-e5a13f23b75e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025883834 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.sram_ctrl_stress_pipeline.2025883834
Directory /workspace/16.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1747645390
Short name T421
Test name
Test status
Simulation time 801801756 ps
CPU time 107.44 seconds
Started Feb 25 02:46:33 PM PST 24
Finished Feb 25 02:48:21 PM PST 24
Peak memory 353856 kb
Host smart-89168ba7-e15e-4824-871e-d0699ada3efd
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747645390 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sram_ctrl_throughput_w_partial_write.1747645390
Directory /workspace/16.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/17.sram_ctrl_access_during_key_req.3840220871
Short name T389
Test name
Test status
Simulation time 4451016948 ps
CPU time 1229.78 seconds
Started Feb 25 02:46:33 PM PST 24
Finished Feb 25 03:07:04 PM PST 24
Peak memory 374388 kb
Host smart-94859013-6965-4c31-8aa6-3959d12b1b8a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840220871 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 17.sram_ctrl_access_during_key_req.3840220871
Directory /workspace/17.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/17.sram_ctrl_alert_test.2059373934
Short name T49
Test name
Test status
Simulation time 14275154 ps
CPU time 0.68 seconds
Started Feb 25 02:46:45 PM PST 24
Finished Feb 25 02:46:46 PM PST 24
Peak memory 201684 kb
Host smart-c3c2a247-1dcc-4360-ad9b-43a3f06efaf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059373934 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.sram_ctrl_alert_test.2059373934
Directory /workspace/17.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sram_ctrl_bijection.3917871116
Short name T726
Test name
Test status
Simulation time 270580955 ps
CPU time 17.72 seconds
Started Feb 25 02:46:36 PM PST 24
Finished Feb 25 02:46:54 PM PST 24
Peak memory 202628 kb
Host smart-19515b2a-f97b-4f92-a535-ec8d39684c91
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917871116 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_bijection
.3917871116
Directory /workspace/17.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/17.sram_ctrl_executable.3021359824
Short name T114
Test name
Test status
Simulation time 8835861757 ps
CPU time 312.82 seconds
Started Feb 25 02:46:33 PM PST 24
Finished Feb 25 02:51:47 PM PST 24
Peak memory 328432 kb
Host smart-e0e801a6-3d6a-4355-ae93-362bd1b3f043
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021359824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_executab
le.3021359824
Directory /workspace/17.sram_ctrl_executable/latest

Test location /workspace/coverage/default/17.sram_ctrl_max_throughput.2903871486
Short name T575
Test name
Test status
Simulation time 183900703 ps
CPU time 38.57 seconds
Started Feb 25 02:46:41 PM PST 24
Finished Feb 25 02:47:21 PM PST 24
Peak memory 290788 kb
Host smart-11848b19-55cc-46d4-a1c0-e0b5ef108399
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903871486 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_max_throughput.2903871486
Directory /workspace/17.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_partial_access.1091952225
Short name T320
Test name
Test status
Simulation time 81853893 ps
CPU time 3.6 seconds
Started Feb 25 02:46:45 PM PST 24
Finished Feb 25 02:46:49 PM PST 24
Peak memory 215424 kb
Host smart-ce2ec174-0e91-40f8-9cc9-0c9bfd9c01f0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091952225 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_mem_partial_access.1091952225
Directory /workspace/17.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_mem_walk.214176652
Short name T376
Test name
Test status
Simulation time 2593178740 ps
CPU time 10.84 seconds
Started Feb 25 02:46:43 PM PST 24
Finished Feb 25 02:46:55 PM PST 24
Peak memory 202624 kb
Host smart-1ea63414-3782-4e5b-b2d8-ec66dff94a27
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214176652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl
_mem_walk.214176652
Directory /workspace/17.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/17.sram_ctrl_multiple_keys.84022281
Short name T161
Test name
Test status
Simulation time 76784889042 ps
CPU time 1434.54 seconds
Started Feb 25 02:46:32 PM PST 24
Finished Feb 25 03:10:28 PM PST 24
Peak memory 367356 kb
Host smart-47a474b0-c004-418c-a748-f91fa0b3f0a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84022281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_multipl
e_keys.84022281
Directory /workspace/17.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access.529407627
Short name T578
Test name
Test status
Simulation time 648844969 ps
CPU time 14.67 seconds
Started Feb 25 02:46:33 PM PST 24
Finished Feb 25 02:46:48 PM PST 24
Peak memory 202612 kb
Host smart-8615f783-0c4f-48a6-af2d-9ab1372066d0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529407627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.s
ram_ctrl_partial_access.529407627
Directory /workspace/17.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/17.sram_ctrl_partial_access_b2b.481136557
Short name T679
Test name
Test status
Simulation time 41670097812 ps
CPU time 419.9 seconds
Started Feb 25 02:46:39 PM PST 24
Finished Feb 25 02:53:39 PM PST 24
Peak memory 202688 kb
Host smart-16599aa3-9dbb-46fe-9153-41facc245ce9
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481136557 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 17.sram_ctrl_partial_access_b2b.481136557
Directory /workspace/17.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/17.sram_ctrl_ram_cfg.138365753
Short name T588
Test name
Test status
Simulation time 84159741 ps
CPU time 0.87 seconds
Started Feb 25 02:46:33 PM PST 24
Finished Feb 25 02:46:35 PM PST 24
Peak memory 202564 kb
Host smart-427eaed9-8a38-4f24-8714-9838195ef16c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138365753 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_ram_cfg.138365753
Directory /workspace/17.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/17.sram_ctrl_regwen.1980923811
Short name T698
Test name
Test status
Simulation time 42166801778 ps
CPU time 814.46 seconds
Started Feb 25 02:46:32 PM PST 24
Finished Feb 25 03:00:08 PM PST 24
Peak memory 374472 kb
Host smart-3e128b5c-2d51-4444-93d4-207b34c31c7d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980923811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_regwen.1980923811
Directory /workspace/17.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/17.sram_ctrl_smoke.3909522226
Short name T126
Test name
Test status
Simulation time 1907636217 ps
CPU time 11.02 seconds
Started Feb 25 02:46:33 PM PST 24
Finished Feb 25 02:46:45 PM PST 24
Peak memory 202584 kb
Host smart-4679998f-9b8d-488a-a5ca-741b67977a82
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909522226 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sram_ctrl_smoke.3909522226
Directory /workspace/17.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_all.3508449608
Short name T865
Test name
Test status
Simulation time 41851245603 ps
CPU time 4271.68 seconds
Started Feb 25 02:46:43 PM PST 24
Finished Feb 25 03:57:56 PM PST 24
Peak memory 374440 kb
Host smart-26a2a5df-e665-4dff-b0aa-958a20f3db90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508449608 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 17.sram_ctrl_stress_all.3508449608
Directory /workspace/17.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3883037660
Short name T74
Test name
Test status
Simulation time 3533433510 ps
CPU time 163.95 seconds
Started Feb 25 02:46:34 PM PST 24
Finished Feb 25 02:49:19 PM PST 24
Peak memory 202692 kb
Host smart-8f1cc866-1081-479b-ab15-bd7cd57f6413
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883037660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.sram_ctrl_stress_pipeline.3883037660
Directory /workspace/17.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.449695799
Short name T222
Test name
Test status
Simulation time 159339623 ps
CPU time 161.7 seconds
Started Feb 25 02:46:33 PM PST 24
Finished Feb 25 02:49:15 PM PST 24
Peak memory 373116 kb
Host smart-efe20ef6-6b86-4b56-8a58-2d7d67c3bae8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449695799 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 17.sram_ctrl_throughput_w_partial_write.449695799
Directory /workspace/17.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2429934379
Short name T175
Test name
Test status
Simulation time 2542817678 ps
CPU time 910.43 seconds
Started Feb 25 02:46:44 PM PST 24
Finished Feb 25 03:01:55 PM PST 24
Peak memory 368072 kb
Host smart-0f53fcba-252f-43c0-8bfa-21dd938a67d5
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429934379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 18.sram_ctrl_access_during_key_req.2429934379
Directory /workspace/18.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/18.sram_ctrl_alert_test.3213702994
Short name T295
Test name
Test status
Simulation time 14513169 ps
CPU time 0.65 seconds
Started Feb 25 02:46:44 PM PST 24
Finished Feb 25 02:46:45 PM PST 24
Peak memory 201688 kb
Host smart-65cb0f11-8aca-4df3-a916-62872b74e356
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213702994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.sram_ctrl_alert_test.3213702994
Directory /workspace/18.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sram_ctrl_bijection.4030867830
Short name T232
Test name
Test status
Simulation time 3770030448 ps
CPU time 76.63 seconds
Started Feb 25 02:46:44 PM PST 24
Finished Feb 25 02:48:00 PM PST 24
Peak memory 202652 kb
Host smart-8a7b1493-fd09-4bea-a88f-41c334aa9e93
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030867830 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_bijection
.4030867830
Directory /workspace/18.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/18.sram_ctrl_executable.412264924
Short name T567
Test name
Test status
Simulation time 23911598701 ps
CPU time 1947.2 seconds
Started Feb 25 02:46:43 PM PST 24
Finished Feb 25 03:19:10 PM PST 24
Peak memory 373408 kb
Host smart-aefe0889-ef0c-4dfb-87c0-93dc6d0ce6b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412264924 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_executabl
e.412264924
Directory /workspace/18.sram_ctrl_executable/latest

Test location /workspace/coverage/default/18.sram_ctrl_max_throughput.2631034718
Short name T132
Test name
Test status
Simulation time 82968012 ps
CPU time 19.11 seconds
Started Feb 25 02:46:45 PM PST 24
Finished Feb 25 02:47:04 PM PST 24
Peak memory 270084 kb
Host smart-22cae992-acfd-4a7f-8231-9901e33de10c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631034718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_max_throughput.2631034718
Directory /workspace/18.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_partial_access.3713778659
Short name T82
Test name
Test status
Simulation time 1006994192 ps
CPU time 3.12 seconds
Started Feb 25 02:46:44 PM PST 24
Finished Feb 25 02:46:48 PM PST 24
Peak memory 210772 kb
Host smart-ee2f602d-e00c-476f-b3d8-c5013cb81664
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713778659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_mem_partial_access.3713778659
Directory /workspace/18.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_mem_walk.3758526420
Short name T831
Test name
Test status
Simulation time 692328080 ps
CPU time 10.03 seconds
Started Feb 25 02:46:46 PM PST 24
Finished Feb 25 02:46:56 PM PST 24
Peak memory 202516 kb
Host smart-8afb3527-d225-47ba-a15c-dbce2a53d3e2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758526420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctr
l_mem_walk.3758526420
Directory /workspace/18.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/18.sram_ctrl_multiple_keys.1737015745
Short name T270
Test name
Test status
Simulation time 7377275594 ps
CPU time 1646.45 seconds
Started Feb 25 02:46:46 PM PST 24
Finished Feb 25 03:14:13 PM PST 24
Peak memory 374464 kb
Host smart-ba75e8d5-52d5-4ab9-bf86-7202e78b2b7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737015745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_multi
ple_keys.1737015745
Directory /workspace/18.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access.245547344
Short name T572
Test name
Test status
Simulation time 702641397 ps
CPU time 11.21 seconds
Started Feb 25 02:46:46 PM PST 24
Finished Feb 25 02:46:58 PM PST 24
Peak memory 202596 kb
Host smart-b15b37a8-8aa4-4447-adb5-013de5b662c4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245547344 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.s
ram_ctrl_partial_access.245547344
Directory /workspace/18.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3390726132
Short name T886
Test name
Test status
Simulation time 8206741910 ps
CPU time 214.78 seconds
Started Feb 25 02:46:44 PM PST 24
Finished Feb 25 02:50:19 PM PST 24
Peak memory 202624 kb
Host smart-fe210e36-3d7f-41fb-a38b-85c991c2d419
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390726132 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 18.sram_ctrl_partial_access_b2b.3390726132
Directory /workspace/18.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/18.sram_ctrl_ram_cfg.4289540067
Short name T40
Test name
Test status
Simulation time 28623454 ps
CPU time 1.06 seconds
Started Feb 25 02:46:44 PM PST 24
Finished Feb 25 02:46:45 PM PST 24
Peak memory 202852 kb
Host smart-97e3ab6b-fd7a-4479-a271-38892727e318
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289540067 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_ram_cfg.4289540067
Directory /workspace/18.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/18.sram_ctrl_regwen.3143994451
Short name T423
Test name
Test status
Simulation time 53018123341 ps
CPU time 643.36 seconds
Started Feb 25 02:46:45 PM PST 24
Finished Feb 25 02:57:29 PM PST 24
Peak memory 363068 kb
Host smart-6da4c668-17c9-46a8-84f9-925510d824dd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143994451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_regwen.3143994451
Directory /workspace/18.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/18.sram_ctrl_smoke.141646563
Short name T692
Test name
Test status
Simulation time 500846310 ps
CPU time 12.62 seconds
Started Feb 25 02:46:46 PM PST 24
Finished Feb 25 02:46:58 PM PST 24
Peak memory 202616 kb
Host smart-1a8cbceb-e7c5-4571-8f37-66a58c838ca9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141646563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sram_ctrl_smoke.141646563
Directory /workspace/18.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sram_ctrl_stress_pipeline.2944621625
Short name T8
Test name
Test status
Simulation time 7131225998 ps
CPU time 317.13 seconds
Started Feb 25 02:46:46 PM PST 24
Finished Feb 25 02:52:03 PM PST 24
Peak memory 202676 kb
Host smart-80f92a85-ac03-48fe-80eb-aa82e03ef89a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944621625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.sram_ctrl_stress_pipeline.2944621625
Directory /workspace/18.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.859981939
Short name T868
Test name
Test status
Simulation time 213597307 ps
CPU time 39.63 seconds
Started Feb 25 02:46:44 PM PST 24
Finished Feb 25 02:47:24 PM PST 24
Peak memory 293292 kb
Host smart-b6e89b06-fe88-43a9-95ba-bbc72efc6bee
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859981939 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 18.sram_ctrl_throughput_w_partial_write.859981939
Directory /workspace/18.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/19.sram_ctrl_access_during_key_req.2590153658
Short name T732
Test name
Test status
Simulation time 4999888065 ps
CPU time 730.95 seconds
Started Feb 25 02:46:59 PM PST 24
Finished Feb 25 02:59:11 PM PST 24
Peak memory 360040 kb
Host smart-1798d21c-2d65-43e1-b26c-3e5fce3443aa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590153658 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 19.sram_ctrl_access_during_key_req.2590153658
Directory /workspace/19.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/19.sram_ctrl_alert_test.1178808705
Short name T444
Test name
Test status
Simulation time 13984539 ps
CPU time 0.71 seconds
Started Feb 25 02:46:56 PM PST 24
Finished Feb 25 02:46:57 PM PST 24
Peak memory 202420 kb
Host smart-57aef89c-1c1f-4cfd-922f-008937181113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178808705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.sram_ctrl_alert_test.1178808705
Directory /workspace/19.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sram_ctrl_bijection.2304711899
Short name T260
Test name
Test status
Simulation time 1027152553 ps
CPU time 15.62 seconds
Started Feb 25 02:46:47 PM PST 24
Finished Feb 25 02:47:03 PM PST 24
Peak memory 202616 kb
Host smart-b83ca393-0aff-4f94-9c9d-7c2cb7e6e037
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304711899 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_bijection
.2304711899
Directory /workspace/19.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/19.sram_ctrl_executable.177521253
Short name T743
Test name
Test status
Simulation time 2451484834 ps
CPU time 1210.23 seconds
Started Feb 25 02:46:58 PM PST 24
Finished Feb 25 03:07:08 PM PST 24
Peak memory 368272 kb
Host smart-5a2dea65-af63-429a-b70f-ab4bed55e3c5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177521253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_executabl
e.177521253
Directory /workspace/19.sram_ctrl_executable/latest

Test location /workspace/coverage/default/19.sram_ctrl_lc_escalation.1810162639
Short name T848
Test name
Test status
Simulation time 799859665 ps
CPU time 9.95 seconds
Started Feb 25 02:46:55 PM PST 24
Finished Feb 25 02:47:05 PM PST 24
Peak memory 213384 kb
Host smart-1a6ba3a7-247e-47bf-8b1e-776909dd5dd6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810162639 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_lc_es
calation.1810162639
Directory /workspace/19.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/19.sram_ctrl_max_throughput.35160917
Short name T384
Test name
Test status
Simulation time 88891755 ps
CPU time 33 seconds
Started Feb 25 02:46:57 PM PST 24
Finished Feb 25 02:47:31 PM PST 24
Peak memory 285096 kb
Host smart-e12cd9cf-c7c0-4d46-8c3e-c4d41ae22a78
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35160917 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.sram_ctrl_max_throughput.35160917
Directory /workspace/19.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_partial_access.243860216
Short name T81
Test name
Test status
Simulation time 578362876 ps
CPU time 5.65 seconds
Started Feb 25 02:46:55 PM PST 24
Finished Feb 25 02:47:02 PM PST 24
Peak memory 210836 kb
Host smart-37e4ddf5-8f1a-4a8b-8e51-1d723cacb082
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243860216 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.sram_ctrl_mem_partial_access.243860216
Directory /workspace/19.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_mem_walk.745286037
Short name T580
Test name
Test status
Simulation time 1315945990 ps
CPU time 6.01 seconds
Started Feb 25 02:46:55 PM PST 24
Finished Feb 25 02:47:01 PM PST 24
Peak memory 202572 kb
Host smart-cd6501b8-db36-4350-9c7e-b94da1b24933
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745286037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl
_mem_walk.745286037
Directory /workspace/19.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/19.sram_ctrl_multiple_keys.102182749
Short name T579
Test name
Test status
Simulation time 14500762968 ps
CPU time 1010.83 seconds
Started Feb 25 02:46:44 PM PST 24
Finished Feb 25 03:03:35 PM PST 24
Peak memory 374716 kb
Host smart-a60b5ddf-3076-476a-b35d-5c2b01b46884
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102182749 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_multip
le_keys.102182749
Directory /workspace/19.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access.1663228758
Short name T571
Test name
Test status
Simulation time 431126209 ps
CPU time 8.27 seconds
Started Feb 25 02:46:55 PM PST 24
Finished Feb 25 02:47:03 PM PST 24
Peak memory 202608 kb
Host smart-3320f73b-f324-467e-aaf1-56488f0a565c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663228758 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
sram_ctrl_partial_access.1663228758
Directory /workspace/19.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1734904750
Short name T156
Test name
Test status
Simulation time 15708974957 ps
CPU time 404.9 seconds
Started Feb 25 02:46:58 PM PST 24
Finished Feb 25 02:53:45 PM PST 24
Peak memory 202680 kb
Host smart-ae92bce6-347d-47dc-8ab9-26ea57abcd84
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734904750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 19.sram_ctrl_partial_access_b2b.1734904750
Directory /workspace/19.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/19.sram_ctrl_ram_cfg.3614389648
Short name T39
Test name
Test status
Simulation time 179072790 ps
CPU time 1.14 seconds
Started Feb 25 02:46:56 PM PST 24
Finished Feb 25 02:46:58 PM PST 24
Peak memory 202844 kb
Host smart-4fb91f62-63d7-4170-a36c-6fd903030119
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614389648 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_ram_cfg.3614389648
Directory /workspace/19.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/19.sram_ctrl_regwen.2973579032
Short name T275
Test name
Test status
Simulation time 4020162000 ps
CPU time 1265.82 seconds
Started Feb 25 02:46:59 PM PST 24
Finished Feb 25 03:08:06 PM PST 24
Peak memory 371356 kb
Host smart-1a57b3ab-90b9-40e5-9f61-7a86df2aa509
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973579032 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_regwen.2973579032
Directory /workspace/19.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/19.sram_ctrl_smoke.3233366507
Short name T163
Test name
Test status
Simulation time 2707990892 ps
CPU time 100.73 seconds
Started Feb 25 02:46:42 PM PST 24
Finished Feb 25 02:48:24 PM PST 24
Peak memory 325956 kb
Host smart-21762f0f-bf49-466a-9f44-8967490d2a7b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233366507 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sram_ctrl_smoke.3233366507
Directory /workspace/19.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_all.2650732627
Short name T799
Test name
Test status
Simulation time 80155368229 ps
CPU time 6997.42 seconds
Started Feb 25 02:46:55 PM PST 24
Finished Feb 25 04:43:34 PM PST 24
Peak memory 383708 kb
Host smart-c473242e-bbd8-412f-982b-a4c1add00d8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650732627 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 19.sram_ctrl_stress_all.2650732627
Directory /workspace/19.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sram_ctrl_stress_pipeline.3404717199
Short name T717
Test name
Test status
Simulation time 12856455128 ps
CPU time 190.47 seconds
Started Feb 25 02:46:43 PM PST 24
Finished Feb 25 02:49:54 PM PST 24
Peak memory 202696 kb
Host smart-26338140-df95-4a71-822a-51211b242dd0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404717199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.sram_ctrl_stress_pipeline.3404717199
Directory /workspace/19.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3752628123
Short name T207
Test name
Test status
Simulation time 251270933 ps
CPU time 9.31 seconds
Started Feb 25 02:47:01 PM PST 24
Finished Feb 25 02:47:11 PM PST 24
Peak memory 238320 kb
Host smart-d60a009c-1c25-4cc0-8964-4ebe66716a0d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752628123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sram_ctrl_throughput_w_partial_write.3752628123
Directory /workspace/19.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/2.sram_ctrl_access_during_key_req.2010485668
Short name T446
Test name
Test status
Simulation time 1352179156 ps
CPU time 104.56 seconds
Started Feb 25 02:45:56 PM PST 24
Finished Feb 25 02:47:41 PM PST 24
Peak memory 283208 kb
Host smart-907b28d1-c535-4f4c-a97d-1af51096cad9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010485668 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 2.sram_ctrl_access_during_key_req.2010485668
Directory /workspace/2.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/2.sram_ctrl_alert_test.2697340294
Short name T869
Test name
Test status
Simulation time 14728613 ps
CPU time 0.66 seconds
Started Feb 25 02:45:53 PM PST 24
Finished Feb 25 02:45:54 PM PST 24
Peak memory 201564 kb
Host smart-f33cc2a6-9ed7-4047-bed4-6fb942a4c413
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697340294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_alert_test.2697340294
Directory /workspace/2.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sram_ctrl_bijection.2131563211
Short name T367
Test name
Test status
Simulation time 3948287657 ps
CPU time 60.69 seconds
Started Feb 25 02:45:54 PM PST 24
Finished Feb 25 02:46:56 PM PST 24
Peak memory 202664 kb
Host smart-00f1964e-e2ce-404c-aefb-ca2c235707a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131563211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_bijection.
2131563211
Directory /workspace/2.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/2.sram_ctrl_executable.3547845258
Short name T507
Test name
Test status
Simulation time 11727938414 ps
CPU time 1264.67 seconds
Started Feb 25 02:45:48 PM PST 24
Finished Feb 25 03:06:55 PM PST 24
Peak memory 370296 kb
Host smart-5e00aec6-d056-4310-8fd4-e2f9d48d2585
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547845258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_executabl
e.3547845258
Directory /workspace/2.sram_ctrl_executable/latest

Test location /workspace/coverage/default/2.sram_ctrl_lc_escalation.3046497245
Short name T224
Test name
Test status
Simulation time 1098548448 ps
CPU time 7.67 seconds
Started Feb 25 02:45:53 PM PST 24
Finished Feb 25 02:46:01 PM PST 24
Peak memory 210804 kb
Host smart-458d7cdf-e206-4392-b44c-0abd93bd7168
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046497245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_lc_esc
alation.3046497245
Directory /workspace/2.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/2.sram_ctrl_max_throughput.4049704124
Short name T463
Test name
Test status
Simulation time 161412477 ps
CPU time 2.95 seconds
Started Feb 25 02:45:48 PM PST 24
Finished Feb 25 02:45:53 PM PST 24
Peak memory 214908 kb
Host smart-b16048a5-fb6d-47a4-b7ae-397a6a13ac31
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049704124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 2.sram_ctrl_max_throughput.4049704124
Directory /workspace/2.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_partial_access.1428959358
Short name T165
Test name
Test status
Simulation time 244000645 ps
CPU time 5.29 seconds
Started Feb 25 02:45:47 PM PST 24
Finished Feb 25 02:45:54 PM PST 24
Peak memory 211996 kb
Host smart-083ab82f-d09c-4326-a297-86ca22af72e2
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428959358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_mem_partial_access.1428959358
Directory /workspace/2.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_mem_walk.2937295347
Short name T784
Test name
Test status
Simulation time 2194576859 ps
CPU time 9.65 seconds
Started Feb 25 02:45:49 PM PST 24
Finished Feb 25 02:46:00 PM PST 24
Peak memory 202620 kb
Host smart-038e4a3d-ed7b-41a2-93aa-ffd4a2626cc1
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937295347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl
_mem_walk.2937295347
Directory /workspace/2.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/2.sram_ctrl_multiple_keys.2938580870
Short name T841
Test name
Test status
Simulation time 40794958065 ps
CPU time 1285.13 seconds
Started Feb 25 02:45:56 PM PST 24
Finished Feb 25 03:07:21 PM PST 24
Peak memory 362332 kb
Host smart-6d5e3664-e4f2-4ab5-9c8f-3d6a17c09906
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938580870 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_multip
le_keys.2938580870
Directory /workspace/2.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access.1952700378
Short name T514
Test name
Test status
Simulation time 198378745 ps
CPU time 108.09 seconds
Started Feb 25 02:45:52 PM PST 24
Finished Feb 25 02:47:41 PM PST 24
Peak memory 344276 kb
Host smart-1c32718f-6f62-4122-8363-971a7fab1041
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952700378 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.s
ram_ctrl_partial_access.1952700378
Directory /workspace/2.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1315283384
Short name T862
Test name
Test status
Simulation time 10158547115 ps
CPU time 310.88 seconds
Started Feb 25 02:45:45 PM PST 24
Finished Feb 25 02:50:56 PM PST 24
Peak memory 202712 kb
Host smart-f79eeb54-c0f5-4a3b-894f-0a13b1f9bf14
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315283384 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 2.sram_ctrl_partial_access_b2b.1315283384
Directory /workspace/2.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/2.sram_ctrl_ram_cfg.3804036734
Short name T341
Test name
Test status
Simulation time 42577837 ps
CPU time 1.1 seconds
Started Feb 25 02:45:51 PM PST 24
Finished Feb 25 02:45:53 PM PST 24
Peak memory 202836 kb
Host smart-a3973108-ddf0-4c01-9bb9-eb3e0b2710cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804036734 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_ram_cfg.3804036734
Directory /workspace/2.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/2.sram_ctrl_regwen.2462908547
Short name T364
Test name
Test status
Simulation time 11907562506 ps
CPU time 663.78 seconds
Started Feb 25 02:45:54 PM PST 24
Finished Feb 25 02:56:58 PM PST 24
Peak memory 360852 kb
Host smart-4df7a3e8-517b-4029-b706-84c1d580bafc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462908547 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_regwen.2462908547
Directory /workspace/2.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/2.sram_ctrl_sec_cm.3505530199
Short name T20
Test name
Test status
Simulation time 481876040 ps
CPU time 1.9 seconds
Started Feb 25 02:45:48 PM PST 24
Finished Feb 25 02:45:52 PM PST 24
Peak memory 221304 kb
Host smart-d2474d20-98b4-419e-b917-2b41a4d6d9eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505530199 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.sram_ctrl_sec_cm.3505530199
Directory /workspace/2.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sram_ctrl_smoke.1844808128
Short name T802
Test name
Test status
Simulation time 505547613 ps
CPU time 72.81 seconds
Started Feb 25 02:45:50 PM PST 24
Finished Feb 25 02:47:04 PM PST 24
Peak memory 323712 kb
Host smart-958cc19c-88f8-4284-ba71-34844889ff87
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844808128 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sram_ctrl_smoke.1844808128
Directory /workspace/2.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_all.3588793103
Short name T500
Test name
Test status
Simulation time 33988628725 ps
CPU time 2755.73 seconds
Started Feb 25 02:45:51 PM PST 24
Finished Feb 25 03:31:49 PM PST 24
Peak memory 374504 kb
Host smart-08d94ad5-aac0-4a57-83a0-d1685fc00a82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588793103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 2.sram_ctrl_stress_all.3588793103
Directory /workspace/2.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.sram_ctrl_stress_pipeline.2711332652
Short name T211
Test name
Test status
Simulation time 11272664897 ps
CPU time 238.29 seconds
Started Feb 25 02:45:47 PM PST 24
Finished Feb 25 02:49:48 PM PST 24
Peak memory 202704 kb
Host smart-7d12f268-4111-4f16-953d-bbc92f0a2382
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711332652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.sram_ctrl_stress_pipeline.2711332652
Directory /workspace/2.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2580787420
Short name T151
Test name
Test status
Simulation time 197374925 ps
CPU time 149.86 seconds
Started Feb 25 02:45:54 PM PST 24
Finished Feb 25 02:48:24 PM PST 24
Peak memory 369124 kb
Host smart-42e449ae-0801-4d0d-8f0a-91b175522c6a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580787420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sram_ctrl_throughput_w_partial_write.2580787420
Directory /workspace/2.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/20.sram_ctrl_alert_test.1513241574
Short name T316
Test name
Test status
Simulation time 13295159 ps
CPU time 0.66 seconds
Started Feb 25 02:47:21 PM PST 24
Finished Feb 25 02:47:22 PM PST 24
Peak memory 201728 kb
Host smart-7734b53e-899e-4e2f-b2ca-e93c74273053
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513241574 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.sram_ctrl_alert_test.1513241574
Directory /workspace/20.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sram_ctrl_bijection.2492270607
Short name T776
Test name
Test status
Simulation time 5814756548 ps
CPU time 75.81 seconds
Started Feb 25 02:46:56 PM PST 24
Finished Feb 25 02:48:14 PM PST 24
Peak memory 202652 kb
Host smart-c32133dd-ab4f-4742-98ba-d9d965d16e48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492270607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_bijection
.2492270607
Directory /workspace/20.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/20.sram_ctrl_executable.2795501681
Short name T813
Test name
Test status
Simulation time 13965054147 ps
CPU time 913.1 seconds
Started Feb 25 02:46:54 PM PST 24
Finished Feb 25 03:02:08 PM PST 24
Peak memory 372296 kb
Host smart-b8633c5b-d018-42c3-b226-ed62c7b912d8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795501681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_executab
le.2795501681
Directory /workspace/20.sram_ctrl_executable/latest

Test location /workspace/coverage/default/20.sram_ctrl_lc_escalation.956819794
Short name T549
Test name
Test status
Simulation time 5124572247 ps
CPU time 12.75 seconds
Started Feb 25 02:47:00 PM PST 24
Finished Feb 25 02:47:14 PM PST 24
Peak memory 213992 kb
Host smart-03bfd80a-bcf2-446a-866f-6a039719fd19
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956819794 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_lc_esc
alation.956819794
Directory /workspace/20.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/20.sram_ctrl_max_throughput.3228496804
Short name T347
Test name
Test status
Simulation time 550531845 ps
CPU time 88.31 seconds
Started Feb 25 02:46:58 PM PST 24
Finished Feb 25 02:48:26 PM PST 24
Peak memory 352612 kb
Host smart-ce0fcee5-3d5f-4acd-9672-d299984bd39a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228496804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 20.sram_ctrl_max_throughput.3228496804
Directory /workspace/20.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_partial_access.2593897072
Short name T553
Test name
Test status
Simulation time 166363955 ps
CPU time 5.79 seconds
Started Feb 25 02:47:12 PM PST 24
Finished Feb 25 02:47:18 PM PST 24
Peak memory 210780 kb
Host smart-b8023521-1d11-4947-ab49-de5ac1cc74a8
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593897072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.sram_ctrl_mem_partial_access.2593897072
Directory /workspace/20.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_mem_walk.1566250336
Short name T683
Test name
Test status
Simulation time 1813923193 ps
CPU time 10.3 seconds
Started Feb 25 02:46:56 PM PST 24
Finished Feb 25 02:47:07 PM PST 24
Peak memory 202548 kb
Host smart-7cb87326-bc58-4a56-a741-a2a1814c78f8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566250336 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctr
l_mem_walk.1566250336
Directory /workspace/20.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/20.sram_ctrl_multiple_keys.1043444819
Short name T705
Test name
Test status
Simulation time 8699820834 ps
CPU time 1363.37 seconds
Started Feb 25 02:46:56 PM PST 24
Finished Feb 25 03:09:40 PM PST 24
Peak memory 374148 kb
Host smart-7ff38885-5339-44e0-9be6-299f06959b37
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043444819 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_multi
ple_keys.1043444819
Directory /workspace/20.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access.2072189126
Short name T382
Test name
Test status
Simulation time 1973419272 ps
CPU time 66.69 seconds
Started Feb 25 02:46:56 PM PST 24
Finished Feb 25 02:48:03 PM PST 24
Peak memory 298700 kb
Host smart-581a91e1-305e-43bd-9004-261f5cf96ee0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072189126 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
sram_ctrl_partial_access.2072189126
Directory /workspace/20.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.144483771
Short name T402
Test name
Test status
Simulation time 30343274303 ps
CPU time 277.68 seconds
Started Feb 25 02:46:53 PM PST 24
Finished Feb 25 02:51:31 PM PST 24
Peak memory 202692 kb
Host smart-20c6797b-97d2-445f-8567-de4b81ef98d8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144483771 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 20.sram_ctrl_partial_access_b2b.144483771
Directory /workspace/20.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/20.sram_ctrl_ram_cfg.120386676
Short name T47
Test name
Test status
Simulation time 47003168 ps
CPU time 1.08 seconds
Started Feb 25 02:46:53 PM PST 24
Finished Feb 25 02:46:54 PM PST 24
Peak memory 202844 kb
Host smart-67d07022-7044-452e-9e96-16d18a5756b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120386676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_ram_cfg.120386676
Directory /workspace/20.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/20.sram_ctrl_regwen.659279528
Short name T357
Test name
Test status
Simulation time 47722526135 ps
CPU time 771.64 seconds
Started Feb 25 02:46:57 PM PST 24
Finished Feb 25 02:59:50 PM PST 24
Peak memory 373364 kb
Host smart-b1b87c1a-2918-4d65-8b43-d1150e418f10
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659279528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_regwen.659279528
Directory /workspace/20.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/20.sram_ctrl_smoke.761347071
Short name T208
Test name
Test status
Simulation time 2595071490 ps
CPU time 89.39 seconds
Started Feb 25 02:47:02 PM PST 24
Finished Feb 25 02:48:32 PM PST 24
Peak memory 341988 kb
Host smart-ab8889ec-a8f0-465f-b2ee-6fa1110560f5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761347071 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sram_ctrl_smoke.761347071
Directory /workspace/20.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_all.3795367169
Short name T325
Test name
Test status
Simulation time 119313745819 ps
CPU time 3929.78 seconds
Started Feb 25 02:47:09 PM PST 24
Finished Feb 25 03:52:39 PM PST 24
Peak memory 375460 kb
Host smart-11b8720f-90fb-4dea-a4e6-2156517ea863
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795367169 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 20.sram_ctrl_stress_all.3795367169
Directory /workspace/20.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sram_ctrl_stress_pipeline.657482073
Short name T99
Test name
Test status
Simulation time 2154106180 ps
CPU time 176.96 seconds
Started Feb 25 02:46:57 PM PST 24
Finished Feb 25 02:49:55 PM PST 24
Peak memory 202088 kb
Host smart-3de56a69-e181-404e-be3a-897e8528e983
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657482073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.sram_ctrl_stress_pipeline.657482073
Directory /workspace/20.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.4068187413
Short name T534
Test name
Test status
Simulation time 57664409 ps
CPU time 5.48 seconds
Started Feb 25 02:47:00 PM PST 24
Finished Feb 25 02:47:06 PM PST 24
Peak memory 222900 kb
Host smart-716dd4e9-8aff-439e-8e2a-00fce4bbbc9b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068187413 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sram_ctrl_throughput_w_partial_write.4068187413
Directory /workspace/20.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/21.sram_ctrl_access_during_key_req.2663836593
Short name T701
Test name
Test status
Simulation time 1187320544 ps
CPU time 147.24 seconds
Started Feb 25 02:47:17 PM PST 24
Finished Feb 25 02:49:45 PM PST 24
Peak memory 319764 kb
Host smart-12bdc993-ee55-4327-abf7-700723b72f31
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663836593 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 21.sram_ctrl_access_during_key_req.2663836593
Directory /workspace/21.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/21.sram_ctrl_alert_test.3960020680
Short name T835
Test name
Test status
Simulation time 14608839 ps
CPU time 0.62 seconds
Started Feb 25 02:47:11 PM PST 24
Finished Feb 25 02:47:12 PM PST 24
Peak memory 201504 kb
Host smart-63b15188-64de-451f-8ef6-50448bf812a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960020680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.sram_ctrl_alert_test.3960020680
Directory /workspace/21.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sram_ctrl_bijection.203683442
Short name T877
Test name
Test status
Simulation time 540380820 ps
CPU time 18 seconds
Started Feb 25 02:47:21 PM PST 24
Finished Feb 25 02:47:39 PM PST 24
Peak memory 202648 kb
Host smart-293e8077-3d8b-4405-8aa9-03a2dc3d6b36
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203683442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_bijection.
203683442
Directory /workspace/21.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/21.sram_ctrl_executable.699043698
Short name T680
Test name
Test status
Simulation time 12310240471 ps
CPU time 1145.08 seconds
Started Feb 25 02:47:09 PM PST 24
Finished Feb 25 03:06:14 PM PST 24
Peak memory 373472 kb
Host smart-99177516-3622-4f80-9693-7b22cce69b26
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699043698 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_executabl
e.699043698
Directory /workspace/21.sram_ctrl_executable/latest

Test location /workspace/coverage/default/21.sram_ctrl_lc_escalation.1209769375
Short name T192
Test name
Test status
Simulation time 2495769418 ps
CPU time 7.68 seconds
Started Feb 25 02:47:06 PM PST 24
Finished Feb 25 02:47:13 PM PST 24
Peak memory 210876 kb
Host smart-562f51b8-8789-41e4-b8d0-a7b70b964793
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209769375 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_lc_es
calation.1209769375
Directory /workspace/21.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/21.sram_ctrl_max_throughput.3075632664
Short name T155
Test name
Test status
Simulation time 415189209 ps
CPU time 80.62 seconds
Started Feb 25 02:47:13 PM PST 24
Finished Feb 25 02:48:34 PM PST 24
Peak memory 322168 kb
Host smart-1cbea4e0-7be4-4e37-a7d0-279129527c53
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075632664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_max_throughput.3075632664
Directory /workspace/21.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_partial_access.1140325358
Short name T528
Test name
Test status
Simulation time 263875497 ps
CPU time 2.99 seconds
Started Feb 25 02:47:08 PM PST 24
Finished Feb 25 02:47:11 PM PST 24
Peak memory 210792 kb
Host smart-12a0970f-9286-40bb-b65f-668d79196fe7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140325358 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.sram_ctrl_mem_partial_access.1140325358
Directory /workspace/21.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_mem_walk.566457894
Short name T219
Test name
Test status
Simulation time 1334729961 ps
CPU time 10.71 seconds
Started Feb 25 02:47:10 PM PST 24
Finished Feb 25 02:47:21 PM PST 24
Peak memory 202564 kb
Host smart-af13b2aa-7143-40d0-9324-f801ab55d459
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566457894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl
_mem_walk.566457894
Directory /workspace/21.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/21.sram_ctrl_multiple_keys.3261438555
Short name T652
Test name
Test status
Simulation time 19448678985 ps
CPU time 986.66 seconds
Started Feb 25 02:47:14 PM PST 24
Finished Feb 25 03:03:41 PM PST 24
Peak memory 370344 kb
Host smart-67024047-d039-45ab-8484-6257f831172e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261438555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_multi
ple_keys.3261438555
Directory /workspace/21.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access.747127952
Short name T252
Test name
Test status
Simulation time 699929811 ps
CPU time 13.36 seconds
Started Feb 25 02:47:16 PM PST 24
Finished Feb 25 02:47:30 PM PST 24
Peak memory 202636 kb
Host smart-2eecced9-cec1-4ea2-828f-77e2c6540dd0
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747127952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.s
ram_ctrl_partial_access.747127952
Directory /workspace/21.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.2923433205
Short name T525
Test name
Test status
Simulation time 12730132709 ps
CPU time 233.49 seconds
Started Feb 25 02:47:10 PM PST 24
Finished Feb 25 02:51:04 PM PST 24
Peak memory 202664 kb
Host smart-1e629da6-72fa-4138-82b6-3e9b31f8ef81
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923433205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 21.sram_ctrl_partial_access_b2b.2923433205
Directory /workspace/21.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/21.sram_ctrl_ram_cfg.941647563
Short name T576
Test name
Test status
Simulation time 74513733 ps
CPU time 0.83 seconds
Started Feb 25 02:47:11 PM PST 24
Finished Feb 25 02:47:12 PM PST 24
Peak memory 202580 kb
Host smart-3914a13c-19fc-45d2-a984-7cc42d804aa7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941647563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_ram_cfg.941647563
Directory /workspace/21.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/21.sram_ctrl_regwen.2804464240
Short name T778
Test name
Test status
Simulation time 86060991708 ps
CPU time 2003.87 seconds
Started Feb 25 02:47:13 PM PST 24
Finished Feb 25 03:20:38 PM PST 24
Peak memory 373384 kb
Host smart-b4d33fcb-b9e5-430d-8e5f-3b414338f4ce
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804464240 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_regwen.2804464240
Directory /workspace/21.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/21.sram_ctrl_smoke.3185675092
Short name T292
Test name
Test status
Simulation time 65066084 ps
CPU time 1.62 seconds
Started Feb 25 02:47:14 PM PST 24
Finished Feb 25 02:47:16 PM PST 24
Peak memory 202604 kb
Host smart-5576f9e3-5fd5-4312-ad45-79ce8db415a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185675092 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sram_ctrl_smoke.3185675092
Directory /workspace/21.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_all.1268091099
Short name T667
Test name
Test status
Simulation time 72587130538 ps
CPU time 1575.23 seconds
Started Feb 25 02:47:08 PM PST 24
Finished Feb 25 03:13:24 PM PST 24
Peak memory 375284 kb
Host smart-a216b752-0d42-404a-b935-19782d3ad8b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268091099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 21.sram_ctrl_stress_all.1268091099
Directory /workspace/21.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.sram_ctrl_stress_pipeline.114459568
Short name T574
Test name
Test status
Simulation time 13286787985 ps
CPU time 356.96 seconds
Started Feb 25 02:47:13 PM PST 24
Finished Feb 25 02:53:10 PM PST 24
Peak memory 202696 kb
Host smart-ecf702bf-2aed-427b-a27a-3cbca5f9a99a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114459568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.sram_ctrl_stress_pipeline.114459568
Directory /workspace/21.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.491925421
Short name T294
Test name
Test status
Simulation time 140095669 ps
CPU time 127.42 seconds
Started Feb 25 02:47:11 PM PST 24
Finished Feb 25 02:49:18 PM PST 24
Peak memory 345524 kb
Host smart-ad719b9d-c631-49f2-a0eb-0f33b4672aa8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491925421 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 21.sram_ctrl_throughput_w_partial_write.491925421
Directory /workspace/21.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/22.sram_ctrl_access_during_key_req.2146056620
Short name T428
Test name
Test status
Simulation time 8773891198 ps
CPU time 938.19 seconds
Started Feb 25 02:47:15 PM PST 24
Finished Feb 25 03:02:54 PM PST 24
Peak memory 369996 kb
Host smart-ff20fdf3-ea97-444f-ae17-45fe27eb7449
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146056620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 22.sram_ctrl_access_during_key_req.2146056620
Directory /workspace/22.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/22.sram_ctrl_alert_test.874383562
Short name T595
Test name
Test status
Simulation time 24948565 ps
CPU time 0.66 seconds
Started Feb 25 02:47:15 PM PST 24
Finished Feb 25 02:47:16 PM PST 24
Peak memory 202476 kb
Host smart-b81249ef-5d5c-48f0-8800-431c8202b5f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874383562 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.sram_ctrl_alert_test.874383562
Directory /workspace/22.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sram_ctrl_bijection.3682454312
Short name T445
Test name
Test status
Simulation time 240036528 ps
CPU time 14.79 seconds
Started Feb 25 02:47:10 PM PST 24
Finished Feb 25 02:47:25 PM PST 24
Peak memory 202620 kb
Host smart-f4bb3cdf-3ad5-4ece-8156-b54cef38bd01
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682454312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_bijection
.3682454312
Directory /workspace/22.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/22.sram_ctrl_executable.3640805285
Short name T544
Test name
Test status
Simulation time 14740065893 ps
CPU time 1475.98 seconds
Started Feb 25 02:47:13 PM PST 24
Finished Feb 25 03:11:50 PM PST 24
Peak memory 373424 kb
Host smart-7bedf8d8-c3a7-4c13-9455-e8342a8e8f5d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640805285 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_executab
le.3640805285
Directory /workspace/22.sram_ctrl_executable/latest

Test location /workspace/coverage/default/22.sram_ctrl_lc_escalation.1712425323
Short name T258
Test name
Test status
Simulation time 1268724686 ps
CPU time 4.93 seconds
Started Feb 25 02:47:06 PM PST 24
Finished Feb 25 02:47:11 PM PST 24
Peak memory 210760 kb
Host smart-7e36b27a-397c-4cdf-8438-fa0473d16928
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712425323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_lc_es
calation.1712425323
Directory /workspace/22.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/22.sram_ctrl_max_throughput.2613914468
Short name T309
Test name
Test status
Simulation time 74460022 ps
CPU time 2.88 seconds
Started Feb 25 02:47:15 PM PST 24
Finished Feb 25 02:47:18 PM PST 24
Peak memory 210728 kb
Host smart-cd449328-2a32-4770-a107-40b888ab1c52
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613914468 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 22.sram_ctrl_max_throughput.2613914468
Directory /workspace/22.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_partial_access.1287234568
Short name T14
Test name
Test status
Simulation time 230964966 ps
CPU time 5.04 seconds
Started Feb 25 02:47:11 PM PST 24
Finished Feb 25 02:47:16 PM PST 24
Peak memory 211876 kb
Host smart-62fd80eb-8d75-4aeb-816f-64d82098aac5
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287234568 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_mem_partial_access.1287234568
Directory /workspace/22.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_mem_walk.3013751851
Short name T489
Test name
Test status
Simulation time 267619231 ps
CPU time 7.86 seconds
Started Feb 25 02:47:15 PM PST 24
Finished Feb 25 02:47:23 PM PST 24
Peak memory 202520 kb
Host smart-f026fb26-db4d-4297-a877-ac5e4ba4d65b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013751851 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctr
l_mem_walk.3013751851
Directory /workspace/22.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/22.sram_ctrl_multiple_keys.2484606564
Short name T181
Test name
Test status
Simulation time 16763974516 ps
CPU time 1610.44 seconds
Started Feb 25 02:47:08 PM PST 24
Finished Feb 25 03:13:59 PM PST 24
Peak memory 374928 kb
Host smart-ee9cf58f-3653-414a-87c2-71b94bf0cf3c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484606564 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_multi
ple_keys.2484606564
Directory /workspace/22.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access.1123404950
Short name T288
Test name
Test status
Simulation time 166727641 ps
CPU time 7.12 seconds
Started Feb 25 02:47:17 PM PST 24
Finished Feb 25 02:47:25 PM PST 24
Peak memory 202640 kb
Host smart-f5674bd5-df06-40af-a5be-0f52d5690115
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123404950 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
sram_ctrl_partial_access.1123404950
Directory /workspace/22.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2312626672
Short name T594
Test name
Test status
Simulation time 10953509205 ps
CPU time 400.75 seconds
Started Feb 25 02:47:12 PM PST 24
Finished Feb 25 02:53:53 PM PST 24
Peak memory 202680 kb
Host smart-1d20b457-71d9-495f-b43f-96c57adccdc6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312626672 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_partial_access_b2b.2312626672
Directory /workspace/22.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/22.sram_ctrl_ram_cfg.1022482143
Short name T583
Test name
Test status
Simulation time 113268737 ps
CPU time 0.84 seconds
Started Feb 25 02:47:11 PM PST 24
Finished Feb 25 02:47:11 PM PST 24
Peak memory 202560 kb
Host smart-b24b87fc-db29-4333-8337-2fa55596d1d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022482143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_ram_cfg.1022482143
Directory /workspace/22.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/22.sram_ctrl_regwen.1362775000
Short name T462
Test name
Test status
Simulation time 2028170343 ps
CPU time 351.72 seconds
Started Feb 25 02:47:15 PM PST 24
Finished Feb 25 02:53:07 PM PST 24
Peak memory 353064 kb
Host smart-a358b3b7-db4a-4080-ad41-8187c24c6c7a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362775000 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_regwen.1362775000
Directory /workspace/22.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/22.sram_ctrl_smoke.3031974435
Short name T422
Test name
Test status
Simulation time 43768881 ps
CPU time 5.54 seconds
Started Feb 25 02:47:10 PM PST 24
Finished Feb 25 02:47:16 PM PST 24
Peak memory 223936 kb
Host smart-1bec285a-c4bb-4bfc-9952-50a8c05b1358
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031974435 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sram_ctrl_smoke.3031974435
Directory /workspace/22.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_all.908866537
Short name T756
Test name
Test status
Simulation time 59043110551 ps
CPU time 1029.03 seconds
Started Feb 25 02:47:13 PM PST 24
Finished Feb 25 03:04:22 PM PST 24
Peak memory 372672 kb
Host smart-e11c37ba-4f65-4a7f-8c90-4c513b762136
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908866537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 22.sram_ctrl_stress_all.908866537
Directory /workspace/22.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sram_ctrl_stress_pipeline.3087722491
Short name T217
Test name
Test status
Simulation time 9600444055 ps
CPU time 225.47 seconds
Started Feb 25 02:47:08 PM PST 24
Finished Feb 25 02:50:54 PM PST 24
Peak memory 202596 kb
Host smart-c49831e3-d894-4271-b2f6-6769496cfa52
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087722491 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.sram_ctrl_stress_pipeline.3087722491
Directory /workspace/22.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.1473458504
Short name T498
Test name
Test status
Simulation time 614616029 ps
CPU time 127.24 seconds
Started Feb 25 02:47:16 PM PST 24
Finished Feb 25 02:49:23 PM PST 24
Peak memory 366952 kb
Host smart-0787120e-5a6c-4050-acab-0356de515631
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473458504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sram_ctrl_throughput_w_partial_write.1473458504
Directory /workspace/22.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/23.sram_ctrl_access_during_key_req.4203550685
Short name T657
Test name
Test status
Simulation time 1772374013 ps
CPU time 65.84 seconds
Started Feb 25 02:47:21 PM PST 24
Finished Feb 25 02:48:27 PM PST 24
Peak memory 296320 kb
Host smart-ab3fd538-ae89-4a7a-b2da-75c155087415
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203550685 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 23.sram_ctrl_access_during_key_req.4203550685
Directory /workspace/23.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/23.sram_ctrl_alert_test.1438533894
Short name T790
Test name
Test status
Simulation time 17264378 ps
CPU time 0.66 seconds
Started Feb 25 02:47:14 PM PST 24
Finished Feb 25 02:47:15 PM PST 24
Peak memory 202432 kb
Host smart-79b87ba9-c7a1-458b-9210-57073f5381b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438533894 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.sram_ctrl_alert_test.1438533894
Directory /workspace/23.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sram_ctrl_bijection.27927476
Short name T742
Test name
Test status
Simulation time 4518228653 ps
CPU time 43.53 seconds
Started Feb 25 02:47:14 PM PST 24
Finished Feb 25 02:47:58 PM PST 24
Peak memory 202692 kb
Host smart-b5549b56-5b36-4c04-8e87-e9873aff0c5f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27927476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_bijection.27927476
Directory /workspace/23.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/23.sram_ctrl_executable.2289062701
Short name T590
Test name
Test status
Simulation time 2367271319 ps
CPU time 89.19 seconds
Started Feb 25 02:47:17 PM PST 24
Finished Feb 25 02:48:47 PM PST 24
Peak memory 318808 kb
Host smart-a12e3a09-68d8-4f81-b64d-765f94a98c38
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289062701 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_executab
le.2289062701
Directory /workspace/23.sram_ctrl_executable/latest

Test location /workspace/coverage/default/23.sram_ctrl_lc_escalation.817896989
Short name T120
Test name
Test status
Simulation time 166834386 ps
CPU time 4.78 seconds
Started Feb 25 02:47:15 PM PST 24
Finished Feb 25 02:47:20 PM PST 24
Peak memory 210832 kb
Host smart-504d094f-5b88-45c3-bfab-6d909855914c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817896989 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_lc_esc
alation.817896989
Directory /workspace/23.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/23.sram_ctrl_max_throughput.483525692
Short name T531
Test name
Test status
Simulation time 125718645 ps
CPU time 12.1 seconds
Started Feb 25 02:47:09 PM PST 24
Finished Feb 25 02:47:21 PM PST 24
Peak memory 239676 kb
Host smart-2a95fec3-9062-47a4-a157-f48b5a8afb88
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483525692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.sram_ctrl_max_throughput.483525692
Directory /workspace/23.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_partial_access.802228514
Short name T853
Test name
Test status
Simulation time 126876567 ps
CPU time 4.83 seconds
Started Feb 25 02:47:26 PM PST 24
Finished Feb 25 02:47:31 PM PST 24
Peak memory 210876 kb
Host smart-41c862d2-d18f-495c-b21b-cd005a06d512
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802228514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.sram_ctrl_mem_partial_access.802228514
Directory /workspace/23.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_mem_walk.34850168
Short name T598
Test name
Test status
Simulation time 232469007 ps
CPU time 4.85 seconds
Started Feb 25 02:47:16 PM PST 24
Finished Feb 25 02:47:22 PM PST 24
Peak memory 202560 kb
Host smart-8d2fcee8-2aa1-454f-9e68-b1b28be3b8b2
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34850168 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sr
am_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_
mem_walk.34850168
Directory /workspace/23.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/23.sram_ctrl_multiple_keys.1804341715
Short name T693
Test name
Test status
Simulation time 8527574546 ps
CPU time 531.41 seconds
Started Feb 25 02:47:08 PM PST 24
Finished Feb 25 02:55:59 PM PST 24
Peak memory 369916 kb
Host smart-eabccf3d-ce63-4720-832d-9bcca8a3ac6a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804341715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_multi
ple_keys.1804341715
Directory /workspace/23.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access.4158293454
Short name T714
Test name
Test status
Simulation time 618810969 ps
CPU time 2.56 seconds
Started Feb 25 02:47:11 PM PST 24
Finished Feb 25 02:47:13 PM PST 24
Peak memory 202732 kb
Host smart-68720090-479c-4daf-ba6f-e2fb55beff33
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158293454 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
sram_ctrl_partial_access.4158293454
Directory /workspace/23.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3529113410
Short name T146
Test name
Test status
Simulation time 11135530028 ps
CPU time 299.91 seconds
Started Feb 25 02:47:17 PM PST 24
Finished Feb 25 02:52:17 PM PST 24
Peak memory 202684 kb
Host smart-c14c9160-d5bb-49a1-9d34-d75e1cfb03da
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529113410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 23.sram_ctrl_partial_access_b2b.3529113410
Directory /workspace/23.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/23.sram_ctrl_ram_cfg.1389866102
Short name T878
Test name
Test status
Simulation time 71015244 ps
CPU time 1.01 seconds
Started Feb 25 02:47:12 PM PST 24
Finished Feb 25 02:47:14 PM PST 24
Peak memory 202816 kb
Host smart-08168d96-41e4-4053-9b2f-660b6b643cff
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389866102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_ram_cfg.1389866102
Directory /workspace/23.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/23.sram_ctrl_regwen.2518430581
Short name T345
Test name
Test status
Simulation time 35361218412 ps
CPU time 1297.11 seconds
Started Feb 25 02:47:12 PM PST 24
Finished Feb 25 03:08:49 PM PST 24
Peak memory 367348 kb
Host smart-fc478df1-0fa8-47a2-8010-3c7cf9717372
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518430581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_regwen.2518430581
Directory /workspace/23.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/23.sram_ctrl_smoke.118377304
Short name T187
Test name
Test status
Simulation time 268693953 ps
CPU time 136.53 seconds
Started Feb 25 02:47:26 PM PST 24
Finished Feb 25 02:49:43 PM PST 24
Peak memory 370972 kb
Host smart-8ee1f3fd-0ce1-4ed2-9380-7d1e41cea6b4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118377304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sram_ctrl_smoke.118377304
Directory /workspace/23.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sram_ctrl_stress_pipeline.4161940603
Short name T696
Test name
Test status
Simulation time 42965953171 ps
CPU time 406.68 seconds
Started Feb 25 02:47:17 PM PST 24
Finished Feb 25 02:54:04 PM PST 24
Peak memory 202704 kb
Host smart-4b67e4d0-db19-4436-ac49-57af9dac2ced
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161940603 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
3.sram_ctrl_stress_pipeline.4161940603
Directory /workspace/23.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.279769765
Short name T332
Test name
Test status
Simulation time 855606344 ps
CPU time 70.2 seconds
Started Feb 25 02:47:15 PM PST 24
Finished Feb 25 02:48:26 PM PST 24
Peak memory 345740 kb
Host smart-4165cbcf-af06-4e9b-aa7b-532bcf59afc9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279769765 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 23.sram_ctrl_throughput_w_partial_write.279769765
Directory /workspace/23.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/24.sram_ctrl_access_during_key_req.306055614
Short name T51
Test name
Test status
Simulation time 3377679771 ps
CPU time 478.27 seconds
Started Feb 25 02:47:16 PM PST 24
Finished Feb 25 02:55:15 PM PST 24
Peak memory 335612 kb
Host smart-d15bd489-9a75-461f-8d85-adb430388526
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306055614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 24.sram_ctrl_access_during_key_req.306055614
Directory /workspace/24.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/24.sram_ctrl_alert_test.3990167450
Short name T864
Test name
Test status
Simulation time 86458707 ps
CPU time 0.7 seconds
Started Feb 25 02:47:18 PM PST 24
Finished Feb 25 02:47:19 PM PST 24
Peak memory 201504 kb
Host smart-1da263da-426b-470f-ab6c-7bb901fc35a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990167450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.sram_ctrl_alert_test.3990167450
Directory /workspace/24.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sram_ctrl_bijection.2502393528
Short name T513
Test name
Test status
Simulation time 6640666932 ps
CPU time 50.2 seconds
Started Feb 25 02:47:15 PM PST 24
Finished Feb 25 02:48:06 PM PST 24
Peak memory 202716 kb
Host smart-1f4ad707-3e9a-4fe4-a8f1-609d10f7c157
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502393528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_bijection
.2502393528
Directory /workspace/24.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/24.sram_ctrl_executable.2122421372
Short name T409
Test name
Test status
Simulation time 55619723763 ps
CPU time 1702.38 seconds
Started Feb 25 02:47:16 PM PST 24
Finished Feb 25 03:15:39 PM PST 24
Peak memory 374236 kb
Host smart-e0f5c050-4c78-4000-a0d1-b58ff9506253
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122421372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_executab
le.2122421372
Directory /workspace/24.sram_ctrl_executable/latest

Test location /workspace/coverage/default/24.sram_ctrl_lc_escalation.3656864591
Short name T557
Test name
Test status
Simulation time 765213388 ps
CPU time 10.07 seconds
Started Feb 25 02:47:14 PM PST 24
Finished Feb 25 02:47:25 PM PST 24
Peak memory 210848 kb
Host smart-925c74c7-c399-45d1-bf8b-6b4417e39a52
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656864591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_lc_es
calation.3656864591
Directory /workspace/24.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/24.sram_ctrl_max_throughput.2498281503
Short name T373
Test name
Test status
Simulation time 84413347 ps
CPU time 3.61 seconds
Started Feb 25 02:47:11 PM PST 24
Finished Feb 25 02:47:14 PM PST 24
Peak memory 219000 kb
Host smart-17f6717c-8a43-41f2-8dd3-e373d1227069
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498281503 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 24.sram_ctrl_max_throughput.2498281503
Directory /workspace/24.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_partial_access.2433371127
Short name T167
Test name
Test status
Simulation time 47002507 ps
CPU time 3.03 seconds
Started Feb 25 02:47:19 PM PST 24
Finished Feb 25 02:47:22 PM PST 24
Peak memory 210836 kb
Host smart-c2773632-50d9-4a9c-8d13-55a825b16fcc
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433371127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_mem_partial_access.2433371127
Directory /workspace/24.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_mem_walk.1164474972
Short name T569
Test name
Test status
Simulation time 2621831446 ps
CPU time 9 seconds
Started Feb 25 02:47:20 PM PST 24
Finished Feb 25 02:47:29 PM PST 24
Peak memory 202620 kb
Host smart-5fd66b46-a3db-4c0c-98c9-5a82ca978b92
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164474972 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctr
l_mem_walk.1164474972
Directory /workspace/24.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/24.sram_ctrl_multiple_keys.3937734772
Short name T353
Test name
Test status
Simulation time 34422329670 ps
CPU time 325.66 seconds
Started Feb 25 02:47:12 PM PST 24
Finished Feb 25 02:52:38 PM PST 24
Peak memory 354812 kb
Host smart-0b7a28a4-9726-49f4-9aa6-ff3925380f74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937734772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_multi
ple_keys.3937734772
Directory /workspace/24.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access.2729768484
Short name T818
Test name
Test status
Simulation time 568500771 ps
CPU time 11.08 seconds
Started Feb 25 02:47:15 PM PST 24
Finished Feb 25 02:47:27 PM PST 24
Peak memory 202540 kb
Host smart-13603012-ec4d-4f73-bde1-dae40d31fe9d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729768484 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
sram_ctrl_partial_access.2729768484
Directory /workspace/24.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.2450418263
Short name T741
Test name
Test status
Simulation time 27935095293 ps
CPU time 631.24 seconds
Started Feb 25 02:47:12 PM PST 24
Finished Feb 25 02:57:43 PM PST 24
Peak memory 202656 kb
Host smart-c4088673-b60a-47df-99ba-6b751f8210c6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450418263 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 24.sram_ctrl_partial_access_b2b.2450418263
Directory /workspace/24.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/24.sram_ctrl_ram_cfg.2141071589
Short name T476
Test name
Test status
Simulation time 47659191 ps
CPU time 1.1 seconds
Started Feb 25 02:47:26 PM PST 24
Finished Feb 25 02:47:28 PM PST 24
Peak memory 202876 kb
Host smart-c51ea7a2-3c26-429b-8b9e-1efd46a39dbb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141071589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_ram_cfg.2141071589
Directory /workspace/24.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/24.sram_ctrl_regwen.559074824
Short name T29
Test name
Test status
Simulation time 414192792 ps
CPU time 162.52 seconds
Started Feb 25 02:47:17 PM PST 24
Finished Feb 25 02:50:00 PM PST 24
Peak memory 372208 kb
Host smart-fcbace18-82c2-47ea-84d0-98fa620521a0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559074824 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_regwen.559074824
Directory /workspace/24.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/24.sram_ctrl_smoke.3657232891
Short name T366
Test name
Test status
Simulation time 1387179546 ps
CPU time 16.14 seconds
Started Feb 25 02:47:12 PM PST 24
Finished Feb 25 02:47:29 PM PST 24
Peak memory 202596 kb
Host smart-4a77243b-4e38-4846-9019-0217821e3d88
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657232891 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sram_ctrl_smoke.3657232891
Directory /workspace/24.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_all.3713535745
Short name T6
Test name
Test status
Simulation time 83820035835 ps
CPU time 1755.31 seconds
Started Feb 25 02:47:17 PM PST 24
Finished Feb 25 03:16:32 PM PST 24
Peak memory 370352 kb
Host smart-e2883d49-01dd-4d5e-8bc8-9bd80458bf6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713535745 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 24.sram_ctrl_stress_all.3713535745
Directory /workspace/24.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sram_ctrl_stress_pipeline.3791240146
Short name T482
Test name
Test status
Simulation time 2836177009 ps
CPU time 270.17 seconds
Started Feb 25 02:47:12 PM PST 24
Finished Feb 25 02:51:42 PM PST 24
Peak memory 202688 kb
Host smart-a5be2883-8631-4141-a17f-b2f62b2b26eb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791240146 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.sram_ctrl_stress_pipeline.3791240146
Directory /workspace/24.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1177307941
Short name T198
Test name
Test status
Simulation time 130279393 ps
CPU time 58.86 seconds
Started Feb 25 02:47:14 PM PST 24
Finished Feb 25 02:48:13 PM PST 24
Peak memory 337484 kb
Host smart-714c9282-4ca2-4536-8fec-6cedcb237eca
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177307941 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sram_ctrl_throughput_w_partial_write.1177307941
Directory /workspace/24.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2346092692
Short name T548
Test name
Test status
Simulation time 5424033472 ps
CPU time 617.48 seconds
Started Feb 25 02:47:20 PM PST 24
Finished Feb 25 02:57:38 PM PST 24
Peak memory 352880 kb
Host smart-4eb842c8-dbbd-4023-a1b8-6c2a0b05d1e0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346092692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 25.sram_ctrl_access_during_key_req.2346092692
Directory /workspace/25.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/25.sram_ctrl_alert_test.2947902804
Short name T411
Test name
Test status
Simulation time 23053546 ps
CPU time 0.66 seconds
Started Feb 25 02:47:27 PM PST 24
Finished Feb 25 02:47:27 PM PST 24
Peak memory 201544 kb
Host smart-b1449d81-6596-45af-baa0-84eda5238eab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947902804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.sram_ctrl_alert_test.2947902804
Directory /workspace/25.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sram_ctrl_bijection.1556395811
Short name T593
Test name
Test status
Simulation time 15111301088 ps
CPU time 57.3 seconds
Started Feb 25 02:47:29 PM PST 24
Finished Feb 25 02:48:27 PM PST 24
Peak memory 202608 kb
Host smart-d801a15c-486c-4cbd-bda3-d5fba4516058
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556395811 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_bijection
.1556395811
Directory /workspace/25.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/25.sram_ctrl_executable.164617566
Short name T150
Test name
Test status
Simulation time 3705557652 ps
CPU time 18.81 seconds
Started Feb 25 02:47:18 PM PST 24
Finished Feb 25 02:47:37 PM PST 24
Peak memory 202632 kb
Host smart-e0336104-f0aa-4f20-98d5-d90ea944d771
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164617566 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_executabl
e.164617566
Directory /workspace/25.sram_ctrl_executable/latest

Test location /workspace/coverage/default/25.sram_ctrl_lc_escalation.931194487
Short name T587
Test name
Test status
Simulation time 490465687 ps
CPU time 7.54 seconds
Started Feb 25 02:47:21 PM PST 24
Finished Feb 25 02:47:29 PM PST 24
Peak memory 213148 kb
Host smart-ad31b454-2afd-4047-8130-a6ad5ce9e03c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931194487 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_lc_esc
alation.931194487
Directory /workspace/25.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/25.sram_ctrl_max_throughput.1690039604
Short name T662
Test name
Test status
Simulation time 214499318 ps
CPU time 73.22 seconds
Started Feb 25 02:47:26 PM PST 24
Finished Feb 25 02:48:40 PM PST 24
Peak memory 331604 kb
Host smart-4f59399b-1af6-4de9-9628-8c27e43bfa63
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690039604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_max_throughput.1690039604
Directory /workspace/25.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_partial_access.1609251524
Short name T506
Test name
Test status
Simulation time 889903970 ps
CPU time 2.98 seconds
Started Feb 25 02:47:21 PM PST 24
Finished Feb 25 02:47:25 PM PST 24
Peak memory 210812 kb
Host smart-8b84a97e-fdc5-4ba5-99a9-13cd6b4fe4fa
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609251524 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_mem_partial_access.1609251524
Directory /workspace/25.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_mem_walk.492165696
Short name T248
Test name
Test status
Simulation time 2400860337 ps
CPU time 11.12 seconds
Started Feb 25 02:47:27 PM PST 24
Finished Feb 25 02:47:39 PM PST 24
Peak memory 202648 kb
Host smart-08fa0832-bb9d-438c-a722-b0661c8550b8
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492165696 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl
_mem_walk.492165696
Directory /workspace/25.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/25.sram_ctrl_multiple_keys.483380581
Short name T706
Test name
Test status
Simulation time 2366144119 ps
CPU time 37.39 seconds
Started Feb 25 02:47:19 PM PST 24
Finished Feb 25 02:47:56 PM PST 24
Peak memory 202684 kb
Host smart-b9b20ca6-286c-4564-979d-0b533d0efdc1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483380581 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_multip
le_keys.483380581
Directory /workspace/25.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access.3947528157
Short name T226
Test name
Test status
Simulation time 1756092743 ps
CPU time 16.41 seconds
Started Feb 25 02:47:27 PM PST 24
Finished Feb 25 02:47:44 PM PST 24
Peak memory 202644 kb
Host smart-b08f14f6-5945-4a27-ba9a-b3e2a4692694
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947528157 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
sram_ctrl_partial_access.3947528157
Directory /workspace/25.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/25.sram_ctrl_partial_access_b2b.2957970420
Short name T511
Test name
Test status
Simulation time 17326884439 ps
CPU time 318.74 seconds
Started Feb 25 02:47:21 PM PST 24
Finished Feb 25 02:52:40 PM PST 24
Peak memory 202688 kb
Host smart-4137676e-9c17-4b9b-9903-4a894f432443
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957970420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 25.sram_ctrl_partial_access_b2b.2957970420
Directory /workspace/25.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/25.sram_ctrl_ram_cfg.745306802
Short name T134
Test name
Test status
Simulation time 65585101 ps
CPU time 0.87 seconds
Started Feb 25 02:47:19 PM PST 24
Finished Feb 25 02:47:20 PM PST 24
Peak memory 202576 kb
Host smart-23dea30f-c611-4389-933e-9e4018255816
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745306802 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_ram_cfg.745306802
Directory /workspace/25.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/25.sram_ctrl_regwen.3277167540
Short name T427
Test name
Test status
Simulation time 12268207259 ps
CPU time 591.89 seconds
Started Feb 25 02:47:26 PM PST 24
Finished Feb 25 02:57:18 PM PST 24
Peak memory 365108 kb
Host smart-7c376147-254b-427d-99a2-bc3da1c1c04f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277167540 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_regwen.3277167540
Directory /workspace/25.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/25.sram_ctrl_smoke.2021787632
Short name T135
Test name
Test status
Simulation time 1769973435 ps
CPU time 14.31 seconds
Started Feb 25 02:47:26 PM PST 24
Finished Feb 25 02:47:41 PM PST 24
Peak memory 202620 kb
Host smart-d4f4a43d-6bf6-4365-9431-756aae270285
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021787632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sram_ctrl_smoke.2021787632
Directory /workspace/25.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_all.1002540687
Short name T271
Test name
Test status
Simulation time 12694556957 ps
CPU time 4048.83 seconds
Started Feb 25 02:47:27 PM PST 24
Finished Feb 25 03:54:56 PM PST 24
Peak memory 375484 kb
Host smart-d27e5e88-5b45-4327-9596-a5c7237d4b5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002540687 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 25.sram_ctrl_stress_all.1002540687
Directory /workspace/25.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sram_ctrl_stress_pipeline.3932756328
Short name T508
Test name
Test status
Simulation time 19139708785 ps
CPU time 280.41 seconds
Started Feb 25 02:47:19 PM PST 24
Finished Feb 25 02:52:00 PM PST 24
Peak memory 202696 kb
Host smart-04fc0edb-f460-468e-a239-17a7c99e100b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932756328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.sram_ctrl_stress_pipeline.3932756328
Directory /workspace/25.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.525425975
Short name T129
Test name
Test status
Simulation time 82721447 ps
CPU time 15.73 seconds
Started Feb 25 02:47:19 PM PST 24
Finished Feb 25 02:47:35 PM PST 24
Peak memory 267788 kb
Host smart-14df30d8-f9c0-4f89-9599-550cc9b78b9e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525425975 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 25.sram_ctrl_throughput_w_partial_write.525425975
Directory /workspace/25.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/26.sram_ctrl_access_during_key_req.984662283
Short name T268
Test name
Test status
Simulation time 3214320360 ps
CPU time 317.65 seconds
Started Feb 25 02:47:25 PM PST 24
Finished Feb 25 02:52:43 PM PST 24
Peak memory 375448 kb
Host smart-10e20392-560d-40c7-91c6-b1f626272563
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984662283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 26.sram_ctrl_access_during_key_req.984662283
Directory /workspace/26.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/26.sram_ctrl_alert_test.1154918416
Short name T25
Test name
Test status
Simulation time 35381182 ps
CPU time 0.66 seconds
Started Feb 25 02:47:25 PM PST 24
Finished Feb 25 02:47:26 PM PST 24
Peak memory 202428 kb
Host smart-a1adc645-2d98-4c5e-a163-04691f75a382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154918416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.sram_ctrl_alert_test.1154918416
Directory /workspace/26.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sram_ctrl_bijection.13931716
Short name T871
Test name
Test status
Simulation time 684827024 ps
CPU time 43.8 seconds
Started Feb 25 02:47:27 PM PST 24
Finished Feb 25 02:48:11 PM PST 24
Peak memory 202528 kb
Host smart-3d59a504-e9f3-4be3-9864-70408be7dcee
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13931716 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_biject
ion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_bijection.13931716
Directory /workspace/26.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/26.sram_ctrl_executable.3649787364
Short name T809
Test name
Test status
Simulation time 3283878192 ps
CPU time 1337.75 seconds
Started Feb 25 02:47:26 PM PST 24
Finished Feb 25 03:09:44 PM PST 24
Peak memory 367236 kb
Host smart-c8693b17-4a4c-443b-87ae-dfad98b45a89
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649787364 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_executab
le.3649787364
Directory /workspace/26.sram_ctrl_executable/latest

Test location /workspace/coverage/default/26.sram_ctrl_max_throughput.1983266299
Short name T9
Test name
Test status
Simulation time 193297120 ps
CPU time 5.58 seconds
Started Feb 25 02:47:26 PM PST 24
Finished Feb 25 02:47:32 PM PST 24
Peak memory 227360 kb
Host smart-eedb333c-5094-4d46-bfcb-4cf6776b1839
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983266299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 26.sram_ctrl_max_throughput.1983266299
Directory /workspace/26.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_partial_access.60824645
Short name T264
Test name
Test status
Simulation time 386357508 ps
CPU time 3.08 seconds
Started Feb 25 02:47:31 PM PST 24
Finished Feb 25 02:47:34 PM PST 24
Peak memory 210880 kb
Host smart-8dfadce3-e9a5-4cd3-862a-664ad631b7d1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60824645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
sram_ctrl_mem_partial_access.60824645
Directory /workspace/26.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_mem_walk.618280464
Short name T527
Test name
Test status
Simulation time 900583576 ps
CPU time 9.84 seconds
Started Feb 25 02:47:32 PM PST 24
Finished Feb 25 02:47:41 PM PST 24
Peak memory 202588 kb
Host smart-a35b7c00-98ac-41f9-b4a0-8d3c29d1e9a6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618280464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl
_mem_walk.618280464
Directory /workspace/26.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/26.sram_ctrl_multiple_keys.4078877760
Short name T457
Test name
Test status
Simulation time 10519188942 ps
CPU time 1247.65 seconds
Started Feb 25 02:47:29 PM PST 24
Finished Feb 25 03:08:16 PM PST 24
Peak memory 372380 kb
Host smart-c7b6abbc-ffe5-46d8-8921-b1d115fd1738
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078877760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_multi
ple_keys.4078877760
Directory /workspace/26.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access.656345532
Short name T415
Test name
Test status
Simulation time 375324184 ps
CPU time 7.21 seconds
Started Feb 25 02:47:31 PM PST 24
Finished Feb 25 02:47:38 PM PST 24
Peak memory 202620 kb
Host smart-56d51214-dbad-41b7-adcc-09705216b928
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656345532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.s
ram_ctrl_partial_access.656345532
Directory /workspace/26.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3964351280
Short name T46
Test name
Test status
Simulation time 13960605361 ps
CPU time 366.34 seconds
Started Feb 25 02:47:31 PM PST 24
Finished Feb 25 02:53:37 PM PST 24
Peak memory 202668 kb
Host smart-b7c6cd88-5565-4b1c-9d2c-139815cd5001
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964351280 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 26.sram_ctrl_partial_access_b2b.3964351280
Directory /workspace/26.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/26.sram_ctrl_ram_cfg.910893219
Short name T798
Test name
Test status
Simulation time 73675060 ps
CPU time 1.11 seconds
Started Feb 25 02:47:28 PM PST 24
Finished Feb 25 02:47:29 PM PST 24
Peak memory 202876 kb
Host smart-84b622c4-17b1-4949-8805-7af305680605
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910893219 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_ram_cfg.910893219
Directory /workspace/26.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/26.sram_ctrl_regwen.4237797288
Short name T677
Test name
Test status
Simulation time 8044165578 ps
CPU time 668.89 seconds
Started Feb 25 02:47:32 PM PST 24
Finished Feb 25 02:58:41 PM PST 24
Peak memory 374448 kb
Host smart-46abf11f-b202-44b0-be97-215ff4f8f715
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237797288 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_regwen.4237797288
Directory /workspace/26.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/26.sram_ctrl_smoke.1750905818
Short name T490
Test name
Test status
Simulation time 416650245 ps
CPU time 47.52 seconds
Started Feb 25 02:47:27 PM PST 24
Finished Feb 25 02:48:15 PM PST 24
Peak memory 304908 kb
Host smart-2bac0a36-c2d3-4816-87f4-6ad83c2c2009
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750905818 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sram_ctrl_smoke.1750905818
Directory /workspace/26.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sram_ctrl_stress_pipeline.1116930047
Short name T408
Test name
Test status
Simulation time 3021134060 ps
CPU time 280.17 seconds
Started Feb 25 02:47:29 PM PST 24
Finished Feb 25 02:52:09 PM PST 24
Peak memory 202696 kb
Host smart-7e8325cd-b225-4efe-b2a4-08922be0d18a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116930047 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.sram_ctrl_stress_pipeline.1116930047
Directory /workspace/26.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1701197803
Short name T558
Test name
Test status
Simulation time 203869076 ps
CPU time 2.25 seconds
Started Feb 25 02:47:28 PM PST 24
Finished Feb 25 02:47:30 PM PST 24
Peak memory 210844 kb
Host smart-4296d960-998d-42cc-9cb3-e95ba6fdb2bf
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701197803 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sram_ctrl_throughput_w_partial_write.1701197803
Directory /workspace/26.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/27.sram_ctrl_access_during_key_req.1702782217
Short name T830
Test name
Test status
Simulation time 7767847260 ps
CPU time 1640.93 seconds
Started Feb 25 02:47:33 PM PST 24
Finished Feb 25 03:14:54 PM PST 24
Peak memory 367164 kb
Host smart-a62e36d0-0ec4-412a-a04b-a29d8f4bfea9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702782217 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 27.sram_ctrl_access_during_key_req.1702782217
Directory /workspace/27.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/27.sram_ctrl_alert_test.925862383
Short name T577
Test name
Test status
Simulation time 60769274 ps
CPU time 0.66 seconds
Started Feb 25 02:47:34 PM PST 24
Finished Feb 25 02:47:35 PM PST 24
Peak memory 201480 kb
Host smart-1698042e-363a-4812-9578-e211f094ff1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925862383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.sram_ctrl_alert_test.925862383
Directory /workspace/27.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sram_ctrl_bijection.2062325464
Short name T290
Test name
Test status
Simulation time 7836107560 ps
CPU time 28.4 seconds
Started Feb 25 02:47:27 PM PST 24
Finished Feb 25 02:47:55 PM PST 24
Peak memory 202608 kb
Host smart-290b3dd2-a54e-4a99-b0e5-323989f18e8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062325464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_bijection
.2062325464
Directory /workspace/27.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/27.sram_ctrl_executable.4096909423
Short name T233
Test name
Test status
Simulation time 16931758606 ps
CPU time 1584.09 seconds
Started Feb 25 02:47:33 PM PST 24
Finished Feb 25 03:13:57 PM PST 24
Peak memory 371408 kb
Host smart-2006036d-065d-4f28-aaa4-ecc938573dd2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096909423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_executab
le.4096909423
Directory /workspace/27.sram_ctrl_executable/latest

Test location /workspace/coverage/default/27.sram_ctrl_lc_escalation.1081809278
Short name T5
Test name
Test status
Simulation time 1662053720 ps
CPU time 12.51 seconds
Started Feb 25 02:47:32 PM PST 24
Finished Feb 25 02:47:45 PM PST 24
Peak memory 210832 kb
Host smart-ed119a65-7c56-471a-b73e-2c8a22ec5a23
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081809278 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_lc_es
calation.1081809278
Directory /workspace/27.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/27.sram_ctrl_max_throughput.956302015
Short name T465
Test name
Test status
Simulation time 247295716 ps
CPU time 15.14 seconds
Started Feb 25 02:47:34 PM PST 24
Finished Feb 25 02:47:49 PM PST 24
Peak memory 255340 kb
Host smart-9246a78c-58a1-4f6c-b84c-8c0cca58c4c4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956302015 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.sram_ctrl_max_throughput.956302015
Directory /workspace/27.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3565374271
Short name T371
Test name
Test status
Simulation time 47450026 ps
CPU time 3.12 seconds
Started Feb 25 02:47:33 PM PST 24
Finished Feb 25 02:47:36 PM PST 24
Peak memory 210852 kb
Host smart-accff7bf-692e-40c3-83ff-403b253ed220
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565374271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_mem_partial_access.3565374271
Directory /workspace/27.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_mem_walk.1103512316
Short name T314
Test name
Test status
Simulation time 1616574778 ps
CPU time 5.23 seconds
Started Feb 25 02:47:35 PM PST 24
Finished Feb 25 02:47:40 PM PST 24
Peak memory 202560 kb
Host smart-34faa983-8216-4f51-b667-0f4460129ed7
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103512316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctr
l_mem_walk.1103512316
Directory /workspace/27.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/27.sram_ctrl_multiple_keys.1407175382
Short name T324
Test name
Test status
Simulation time 6170890106 ps
CPU time 656.99 seconds
Started Feb 25 02:47:25 PM PST 24
Finished Feb 25 02:58:22 PM PST 24
Peak memory 370280 kb
Host smart-ecb73765-4f4c-4d0e-960f-ee5f5cc938a1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407175382 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_multi
ple_keys.1407175382
Directory /workspace/27.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access.3169607362
Short name T154
Test name
Test status
Simulation time 618451003 ps
CPU time 78.68 seconds
Started Feb 25 02:47:26 PM PST 24
Finished Feb 25 02:48:45 PM PST 24
Peak memory 328220 kb
Host smart-798763c0-9789-4aa5-990a-b63cec9f6ceb
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169607362 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
sram_ctrl_partial_access.3169607362
Directory /workspace/27.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/27.sram_ctrl_partial_access_b2b.1388383522
Short name T733
Test name
Test status
Simulation time 8524368683 ps
CPU time 347.86 seconds
Started Feb 25 02:47:36 PM PST 24
Finished Feb 25 02:53:24 PM PST 24
Peak memory 202672 kb
Host smart-56298a8d-b927-4f00-a22b-2aed95492527
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388383522 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 27.sram_ctrl_partial_access_b2b.1388383522
Directory /workspace/27.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/27.sram_ctrl_ram_cfg.2489786876
Short name T759
Test name
Test status
Simulation time 148250826 ps
CPU time 0.9 seconds
Started Feb 25 02:47:35 PM PST 24
Finished Feb 25 02:47:36 PM PST 24
Peak memory 202560 kb
Host smart-94f324e4-f0a4-47ca-89a4-0ce8d339f777
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489786876 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_ram_cfg.2489786876
Directory /workspace/27.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/27.sram_ctrl_regwen.3534912042
Short name T801
Test name
Test status
Simulation time 12018752195 ps
CPU time 447.74 seconds
Started Feb 25 02:47:40 PM PST 24
Finished Feb 25 02:55:07 PM PST 24
Peak memory 361580 kb
Host smart-936c1332-5069-4f6d-8ed7-64110b8e5ee5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534912042 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_regwen.3534912042
Directory /workspace/27.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/27.sram_ctrl_smoke.3645131231
Short name T700
Test name
Test status
Simulation time 4525190077 ps
CPU time 18.36 seconds
Started Feb 25 02:47:26 PM PST 24
Finished Feb 25 02:47:44 PM PST 24
Peak memory 202624 kb
Host smart-bb3bf0cb-e4ff-4d5a-aa74-9efda51cb9ed
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645131231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sram_ctrl_smoke.3645131231
Directory /workspace/27.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_all.94541832
Short name T107
Test name
Test status
Simulation time 111285430441 ps
CPU time 4207.88 seconds
Started Feb 25 02:47:34 PM PST 24
Finished Feb 25 03:57:42 PM PST 24
Peak memory 380456 kb
Host smart-f7456738-9693-485b-8ecf-b0d6f681307e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94541832 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 27.sram_ctrl_stress_all.94541832
Directory /workspace/27.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sram_ctrl_stress_pipeline.1924802985
Short name T660
Test name
Test status
Simulation time 9746913553 ps
CPU time 235.76 seconds
Started Feb 25 02:47:26 PM PST 24
Finished Feb 25 02:51:22 PM PST 24
Peak memory 202712 kb
Host smart-9fc43492-ea80-4908-9865-edb8dd05a1f4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924802985 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.sram_ctrl_stress_pipeline.1924802985
Directory /workspace/27.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1722041194
Short name T122
Test name
Test status
Simulation time 58982001 ps
CPU time 6.76 seconds
Started Feb 25 02:47:33 PM PST 24
Finished Feb 25 02:47:39 PM PST 24
Peak memory 234444 kb
Host smart-f9859dcb-f7ae-48b0-9071-24c862257a38
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722041194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sram_ctrl_throughput_w_partial_write.1722041194
Directory /workspace/27.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/28.sram_ctrl_access_during_key_req.3366181267
Short name T510
Test name
Test status
Simulation time 5876474688 ps
CPU time 224.83 seconds
Started Feb 25 02:47:58 PM PST 24
Finished Feb 25 02:51:43 PM PST 24
Peak memory 310416 kb
Host smart-23b91f92-89e8-4692-84a7-5ce5b65886ae
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366181267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 28.sram_ctrl_access_during_key_req.3366181267
Directory /workspace/28.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/28.sram_ctrl_alert_test.2253547445
Short name T708
Test name
Test status
Simulation time 23571038 ps
CPU time 0.65 seconds
Started Feb 25 02:47:59 PM PST 24
Finished Feb 25 02:47:59 PM PST 24
Peak memory 202436 kb
Host smart-1e4bfb6b-782a-441d-95cb-d2c4b785f433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253547445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.sram_ctrl_alert_test.2253547445
Directory /workspace/28.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sram_ctrl_bijection.1824187319
Short name T404
Test name
Test status
Simulation time 4767473351 ps
CPU time 70.42 seconds
Started Feb 25 02:47:40 PM PST 24
Finished Feb 25 02:48:50 PM PST 24
Peak memory 202668 kb
Host smart-b35de3bd-d6c1-486e-bcd7-6e71070c6c85
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824187319 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_bijection
.1824187319
Directory /workspace/28.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/28.sram_ctrl_executable.3815440304
Short name T887
Test name
Test status
Simulation time 12281921763 ps
CPU time 909.68 seconds
Started Feb 25 02:48:04 PM PST 24
Finished Feb 25 03:03:14 PM PST 24
Peak memory 373304 kb
Host smart-af7bc389-428d-4cd7-b4bf-99918910c0af
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815440304 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_executab
le.3815440304
Directory /workspace/28.sram_ctrl_executable/latest

Test location /workspace/coverage/default/28.sram_ctrl_lc_escalation.4127769044
Short name T416
Test name
Test status
Simulation time 975512584 ps
CPU time 12.11 seconds
Started Feb 25 02:48:03 PM PST 24
Finished Feb 25 02:48:15 PM PST 24
Peak memory 202620 kb
Host smart-4127e3c6-93ea-4957-b9e3-4e40375c5474
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127769044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_lc_es
calation.4127769044
Directory /workspace/28.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/28.sram_ctrl_max_throughput.3680700449
Short name T611
Test name
Test status
Simulation time 112443975 ps
CPU time 88.2 seconds
Started Feb 25 02:47:59 PM PST 24
Finished Feb 25 02:49:27 PM PST 24
Peak memory 324160 kb
Host smart-cc7d3669-3216-4888-999a-dd3cbda4abf2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680700449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 28.sram_ctrl_max_throughput.3680700449
Directory /workspace/28.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_partial_access.1331906125
Short name T396
Test name
Test status
Simulation time 65950051 ps
CPU time 5.1 seconds
Started Feb 25 02:47:53 PM PST 24
Finished Feb 25 02:47:58 PM PST 24
Peak memory 212092 kb
Host smart-ad6af3e9-ac46-4946-9364-76f621c85d0a
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331906125 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_mem_partial_access.1331906125
Directory /workspace/28.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_mem_walk.2816130346
Short name T317
Test name
Test status
Simulation time 237437234 ps
CPU time 5.21 seconds
Started Feb 25 02:47:52 PM PST 24
Finished Feb 25 02:47:58 PM PST 24
Peak memory 202580 kb
Host smart-62a5d9d1-7356-40e1-92d8-9cddd36ff371
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816130346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctr
l_mem_walk.2816130346
Directory /workspace/28.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/28.sram_ctrl_multiple_keys.863724863
Short name T627
Test name
Test status
Simulation time 26299798469 ps
CPU time 602.17 seconds
Started Feb 25 02:47:39 PM PST 24
Finished Feb 25 02:57:42 PM PST 24
Peak memory 374152 kb
Host smart-96adb91f-b6fb-4256-b3da-881d257e3428
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863724863 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_multip
le_keys.863724863
Directory /workspace/28.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access.453270822
Short name T263
Test name
Test status
Simulation time 2533559462 ps
CPU time 12.69 seconds
Started Feb 25 02:47:41 PM PST 24
Finished Feb 25 02:47:54 PM PST 24
Peak memory 202720 kb
Host smart-214613e3-7295-41fe-a001-bb2980b5be5c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453270822 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.s
ram_ctrl_partial_access.453270822
Directory /workspace/28.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.765195844
Short name T213
Test name
Test status
Simulation time 42504059805 ps
CPU time 266.4 seconds
Started Feb 25 02:48:05 PM PST 24
Finished Feb 25 02:52:32 PM PST 24
Peak memory 202676 kb
Host smart-3b73e983-659d-4e01-88d6-9602c986dd25
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765195844 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 28.sram_ctrl_partial_access_b2b.765195844
Directory /workspace/28.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/28.sram_ctrl_ram_cfg.2606137742
Short name T589
Test name
Test status
Simulation time 44296437 ps
CPU time 0.97 seconds
Started Feb 25 02:47:53 PM PST 24
Finished Feb 25 02:47:54 PM PST 24
Peak memory 202572 kb
Host smart-7422c96a-8d91-445f-9746-d3a1f1b418a6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606137742 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_ram_cfg.2606137742
Directory /workspace/28.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/28.sram_ctrl_smoke.4109448259
Short name T629
Test name
Test status
Simulation time 442513282 ps
CPU time 11.14 seconds
Started Feb 25 02:47:34 PM PST 24
Finished Feb 25 02:47:45 PM PST 24
Peak memory 248888 kb
Host smart-6a06b172-f1bf-4bb0-acec-ae599294c40e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109448259 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sram_ctrl_smoke.4109448259
Directory /workspace/28.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sram_ctrl_stress_pipeline.1831556787
Short name T142
Test name
Test status
Simulation time 4021542460 ps
CPU time 154.79 seconds
Started Feb 25 02:47:40 PM PST 24
Finished Feb 25 02:50:15 PM PST 24
Peak memory 202724 kb
Host smart-17573c67-dbf5-485c-b6ff-c3953615f9de
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831556787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.sram_ctrl_stress_pipeline.1831556787
Directory /workspace/28.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1790988490
Short name T763
Test name
Test status
Simulation time 343842404 ps
CPU time 22.04 seconds
Started Feb 25 02:47:57 PM PST 24
Finished Feb 25 02:48:19 PM PST 24
Peak memory 273136 kb
Host smart-bb9b4383-aba0-430b-a964-a6d626e28eea
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790988490 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sram_ctrl_throughput_w_partial_write.1790988490
Directory /workspace/28.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/29.sram_ctrl_access_during_key_req.1008687751
Short name T879
Test name
Test status
Simulation time 11119811097 ps
CPU time 612.2 seconds
Started Feb 25 02:48:05 PM PST 24
Finished Feb 25 02:58:17 PM PST 24
Peak memory 348104 kb
Host smart-23d06752-2e85-4a2a-beb1-6be72fe90afe
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008687751 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 29.sram_ctrl_access_during_key_req.1008687751
Directory /workspace/29.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/29.sram_ctrl_alert_test.1766287423
Short name T648
Test name
Test status
Simulation time 14323385 ps
CPU time 0.73 seconds
Started Feb 25 02:47:59 PM PST 24
Finished Feb 25 02:48:00 PM PST 24
Peak memory 201684 kb
Host smart-5cb5b031-d272-4432-8d31-c6e02a06fab0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766287423 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.sram_ctrl_alert_test.1766287423
Directory /workspace/29.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sram_ctrl_bijection.2628547694
Short name T533
Test name
Test status
Simulation time 2103781074 ps
CPU time 37.06 seconds
Started Feb 25 02:48:04 PM PST 24
Finished Feb 25 02:48:41 PM PST 24
Peak memory 202624 kb
Host smart-b8e848cd-fbfd-4996-896f-61431c3d13b1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628547694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_bijection
.2628547694
Directory /workspace/29.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/29.sram_ctrl_executable.1527307577
Short name T448
Test name
Test status
Simulation time 2127887157 ps
CPU time 684.9 seconds
Started Feb 25 02:48:02 PM PST 24
Finished Feb 25 02:59:27 PM PST 24
Peak memory 365984 kb
Host smart-91cb4fc3-bf05-493b-b87e-c820cbade9d6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527307577 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_executab
le.1527307577
Directory /workspace/29.sram_ctrl_executable/latest

Test location /workspace/coverage/default/29.sram_ctrl_lc_escalation.1875241053
Short name T182
Test name
Test status
Simulation time 2259150016 ps
CPU time 7.59 seconds
Started Feb 25 02:47:59 PM PST 24
Finished Feb 25 02:48:06 PM PST 24
Peak memory 210836 kb
Host smart-db95dd1c-6f6b-44d5-b196-5ecc628c0ccd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875241053 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_lc_es
calation.1875241053
Directory /workspace/29.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/29.sram_ctrl_max_throughput.1188601736
Short name T144
Test name
Test status
Simulation time 508576957 ps
CPU time 115.06 seconds
Started Feb 25 02:48:06 PM PST 24
Finished Feb 25 02:50:01 PM PST 24
Peak memory 358008 kb
Host smart-1ea6bb28-4422-41a2-ad68-90e35280241b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188601736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 29.sram_ctrl_max_throughput.1188601736
Directory /workspace/29.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_partial_access.2345573505
Short name T584
Test name
Test status
Simulation time 68880783 ps
CPU time 2.92 seconds
Started Feb 25 02:48:00 PM PST 24
Finished Feb 25 02:48:04 PM PST 24
Peak memory 210956 kb
Host smart-95356227-842f-4e5c-b6fb-3173bcd00e9d
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345573505 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.sram_ctrl_mem_partial_access.2345573505
Directory /workspace/29.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_mem_walk.4293811618
Short name T92
Test name
Test status
Simulation time 870430462 ps
CPU time 4.63 seconds
Started Feb 25 02:48:12 PM PST 24
Finished Feb 25 02:48:17 PM PST 24
Peak memory 202580 kb
Host smart-1ea85440-c205-427d-b842-4ad748e34a7b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293811618 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctr
l_mem_walk.4293811618
Directory /workspace/29.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/29.sram_ctrl_multiple_keys.4015737973
Short name T481
Test name
Test status
Simulation time 6837143496 ps
CPU time 988.49 seconds
Started Feb 25 02:47:55 PM PST 24
Finished Feb 25 03:04:24 PM PST 24
Peak memory 372420 kb
Host smart-a319bc4b-a336-416a-82d0-439474234cb6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015737973 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_multi
ple_keys.4015737973
Directory /workspace/29.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access.1468452072
Short name T654
Test name
Test status
Simulation time 876587903 ps
CPU time 14.96 seconds
Started Feb 25 02:47:54 PM PST 24
Finished Feb 25 02:48:09 PM PST 24
Peak memory 202640 kb
Host smart-bc08698d-4450-4cd0-ae1e-dcf267f85322
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468452072 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
sram_ctrl_partial_access.1468452072
Directory /workspace/29.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.489354166
Short name T200
Test name
Test status
Simulation time 3054797595 ps
CPU time 215.72 seconds
Started Feb 25 02:48:05 PM PST 24
Finished Feb 25 02:51:41 PM PST 24
Peak memory 202660 kb
Host smart-ee5c7178-c675-48c9-a16b-0f0fac4b9736
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489354166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 29.sram_ctrl_partial_access_b2b.489354166
Directory /workspace/29.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/29.sram_ctrl_ram_cfg.3384264163
Short name T665
Test name
Test status
Simulation time 48805614 ps
CPU time 1.2 seconds
Started Feb 25 02:48:04 PM PST 24
Finished Feb 25 02:48:05 PM PST 24
Peak memory 202864 kb
Host smart-ab836c39-3262-4e54-8998-db52ed0f5505
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384264163 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_ram_cfg.3384264163
Directory /workspace/29.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/29.sram_ctrl_regwen.2393334512
Short name T349
Test name
Test status
Simulation time 1831593282 ps
CPU time 285.32 seconds
Started Feb 25 02:48:00 PM PST 24
Finished Feb 25 02:52:46 PM PST 24
Peak memory 356708 kb
Host smart-7255efe3-139f-4aca-bdea-f7c30d9ddb9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393334512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_regwen.2393334512
Directory /workspace/29.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/29.sram_ctrl_smoke.1084629340
Short name T362
Test name
Test status
Simulation time 191999702 ps
CPU time 3 seconds
Started Feb 25 02:47:53 PM PST 24
Finished Feb 25 02:47:56 PM PST 24
Peak memory 202640 kb
Host smart-6571e028-9ef7-44bd-ae27-648897582340
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084629340 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sram_ctrl_smoke.1084629340
Directory /workspace/29.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sram_ctrl_stress_pipeline.494053888
Short name T644
Test name
Test status
Simulation time 7239581334 ps
CPU time 272.26 seconds
Started Feb 25 02:47:54 PM PST 24
Finished Feb 25 02:52:26 PM PST 24
Peak memory 202660 kb
Host smart-700869fe-d446-4301-ab8e-605990abc571
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494053888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.sram_ctrl_stress_pipeline.494053888
Directory /workspace/29.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3003191211
Short name T521
Test name
Test status
Simulation time 252189022 ps
CPU time 148.04 seconds
Started Feb 25 02:48:03 PM PST 24
Finished Feb 25 02:50:32 PM PST 24
Peak memory 365108 kb
Host smart-8f668fa1-ee7a-453f-b4e3-d45b33623989
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003191211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sram_ctrl_throughput_w_partial_write.3003191211
Directory /workspace/29.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/3.sram_ctrl_access_during_key_req.296726360
Short name T789
Test name
Test status
Simulation time 1942362927 ps
CPU time 893.21 seconds
Started Feb 25 02:45:51 PM PST 24
Finished Feb 25 03:00:46 PM PST 24
Peak memory 373396 kb
Host smart-30b12b5d-51c5-441f-9979-c3535354d955
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296726360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.sram_ctrl_access_during_key_req.296726360
Directory /workspace/3.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/3.sram_ctrl_alert_test.3515084459
Short name T690
Test name
Test status
Simulation time 22715304 ps
CPU time 0.64 seconds
Started Feb 25 02:45:51 PM PST 24
Finished Feb 25 02:45:52 PM PST 24
Peak memory 201304 kb
Host smart-8128809d-12dd-492e-9103-fe3e0639db7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515084459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_alert_test.3515084459
Directory /workspace/3.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sram_ctrl_bijection.2888293082
Short name T374
Test name
Test status
Simulation time 492680997 ps
CPU time 31.41 seconds
Started Feb 25 02:45:51 PM PST 24
Finished Feb 25 02:46:24 PM PST 24
Peak memory 202572 kb
Host smart-4ad9e660-1efc-470d-9471-77a2231973e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888293082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_bijection.
2888293082
Directory /workspace/3.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/3.sram_ctrl_executable.3254115218
Short name T391
Test name
Test status
Simulation time 13512807033 ps
CPU time 845.73 seconds
Started Feb 25 02:45:48 PM PST 24
Finished Feb 25 02:59:56 PM PST 24
Peak memory 367356 kb
Host smart-51d532fc-5cc2-4a69-8693-ef4264d94128
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254115218 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_executabl
e.3254115218
Directory /workspace/3.sram_ctrl_executable/latest

Test location /workspace/coverage/default/3.sram_ctrl_lc_escalation.182085965
Short name T485
Test name
Test status
Simulation time 599403272 ps
CPU time 8.8 seconds
Started Feb 25 02:45:42 PM PST 24
Finished Feb 25 02:45:51 PM PST 24
Peak memory 210844 kb
Host smart-eeeffdf8-1814-46c6-84bb-d20e6eeee16e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182085965 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_lc_esca
lation.182085965
Directory /workspace/3.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/3.sram_ctrl_max_throughput.261941808
Short name T417
Test name
Test status
Simulation time 178001496 ps
CPU time 40.97 seconds
Started Feb 25 02:45:52 PM PST 24
Finished Feb 25 02:46:34 PM PST 24
Peak memory 284336 kb
Host smart-724b9778-1e7d-4c20-b6f6-83f43e499ee9
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261941808 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.sram_ctrl_max_throughput.261941808
Directory /workspace/3.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1437535455
Short name T624
Test name
Test status
Simulation time 47024696 ps
CPU time 2.92 seconds
Started Feb 25 02:45:52 PM PST 24
Finished Feb 25 02:45:56 PM PST 24
Peak memory 211648 kb
Host smart-26f39420-eab8-49f4-b5d8-97999e832909
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437535455 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_mem_partial_access.1437535455
Directory /workspace/3.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_mem_walk.1688446489
Short name T212
Test name
Test status
Simulation time 410335201 ps
CPU time 5.86 seconds
Started Feb 25 02:45:52 PM PST 24
Finished Feb 25 02:45:59 PM PST 24
Peak memory 202564 kb
Host smart-a9e5f9f5-54be-43fc-80a4-11a602ef5a82
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688446489 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl
_mem_walk.1688446489
Directory /workspace/3.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/3.sram_ctrl_multiple_keys.2839475098
Short name T787
Test name
Test status
Simulation time 11409724217 ps
CPU time 539.48 seconds
Started Feb 25 02:45:49 PM PST 24
Finished Feb 25 02:54:50 PM PST 24
Peak memory 374428 kb
Host smart-b545560c-765b-428d-8822-c90d72c327ad
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839475098 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_multip
le_keys.2839475098
Directory /workspace/3.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access.834552093
Short name T669
Test name
Test status
Simulation time 1214119022 ps
CPU time 32.29 seconds
Started Feb 25 02:45:52 PM PST 24
Finished Feb 25 02:46:25 PM PST 24
Peak memory 276512 kb
Host smart-918a2a4a-111e-42bd-8f6b-7f4a433f4f0e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834552093 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sr
am_ctrl_partial_access.834552093
Directory /workspace/3.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3170432066
Short name T838
Test name
Test status
Simulation time 91262411791 ps
CPU time 523.63 seconds
Started Feb 25 02:45:52 PM PST 24
Finished Feb 25 02:54:37 PM PST 24
Peak memory 202652 kb
Host smart-6c03ebc6-304e-480a-9bd3-ff9f31896d49
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170432066 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 3.sram_ctrl_partial_access_b2b.3170432066
Directory /workspace/3.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/3.sram_ctrl_ram_cfg.2368721598
Short name T306
Test name
Test status
Simulation time 27632644 ps
CPU time 1.12 seconds
Started Feb 25 02:45:48 PM PST 24
Finished Feb 25 02:45:52 PM PST 24
Peak memory 202828 kb
Host smart-38fdb3b5-c0c2-468d-901a-4ea0a86ad59f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368721598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_ram_cfg.2368721598
Directory /workspace/3.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/3.sram_ctrl_regwen.1564358782
Short name T761
Test name
Test status
Simulation time 10795008199 ps
CPU time 1037.3 seconds
Started Feb 25 02:45:49 PM PST 24
Finished Feb 25 03:03:08 PM PST 24
Peak memory 368300 kb
Host smart-f62316dc-07a4-409a-a324-7c498b95cc03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564358782 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_regwen.1564358782
Directory /workspace/3.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/3.sram_ctrl_sec_cm.2202992759
Short name T22
Test name
Test status
Simulation time 197516050 ps
CPU time 1.77 seconds
Started Feb 25 02:45:54 PM PST 24
Finished Feb 25 02:45:56 PM PST 24
Peak memory 220796 kb
Host smart-64b80890-a492-44d5-b29c-4d47a9b4840a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202992759 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.sram_ctrl_sec_cm.2202992759
Directory /workspace/3.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.sram_ctrl_smoke.3238610417
Short name T764
Test name
Test status
Simulation time 463319377 ps
CPU time 58.09 seconds
Started Feb 25 02:45:49 PM PST 24
Finished Feb 25 02:46:49 PM PST 24
Peak memory 295728 kb
Host smart-7512fa85-e085-4edd-a13d-03ecdda56de1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238610417 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sram_ctrl_smoke.3238610417
Directory /workspace/3.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_all.3568074804
Short name T273
Test name
Test status
Simulation time 185283577974 ps
CPU time 3338.62 seconds
Started Feb 25 02:45:51 PM PST 24
Finished Feb 25 03:41:31 PM PST 24
Peak memory 374540 kb
Host smart-a89c4a95-9cda-45d0-8afb-4244244d86ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568074804 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 3.sram_ctrl_stress_all.3568074804
Directory /workspace/3.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sram_ctrl_stress_pipeline.2548032921
Short name T894
Test name
Test status
Simulation time 7363527481 ps
CPU time 174.56 seconds
Started Feb 25 02:45:48 PM PST 24
Finished Feb 25 02:48:44 PM PST 24
Peak memory 202704 kb
Host smart-7cadc70d-4922-4185-89d6-8b571c31bfdb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548032921 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.sram_ctrl_stress_pipeline.2548032921
Directory /workspace/3.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3214298279
Short name T616
Test name
Test status
Simulation time 126210329 ps
CPU time 1.69 seconds
Started Feb 25 02:45:52 PM PST 24
Finished Feb 25 02:45:55 PM PST 24
Peak memory 202584 kb
Host smart-25c4f1a8-0192-4aa6-a1b5-2a72ed387e5f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214298279 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sram_ctrl_throughput_w_partial_write.3214298279
Directory /workspace/3.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/30.sram_ctrl_access_during_key_req.3163721916
Short name T19
Test name
Test status
Simulation time 1102619158 ps
CPU time 586.43 seconds
Started Feb 25 02:48:01 PM PST 24
Finished Feb 25 02:57:47 PM PST 24
Peak memory 374380 kb
Host smart-5662d8b2-a8e8-4be9-ad01-f9ad7771dc86
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163721916 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 30.sram_ctrl_access_during_key_req.3163721916
Directory /workspace/30.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/30.sram_ctrl_alert_test.4035060035
Short name T468
Test name
Test status
Simulation time 25372480 ps
CPU time 0.65 seconds
Started Feb 25 02:48:04 PM PST 24
Finished Feb 25 02:48:05 PM PST 24
Peak memory 201688 kb
Host smart-0fe59935-0ac2-434f-b05b-737ff8bb5aad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035060035 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.sram_ctrl_alert_test.4035060035
Directory /workspace/30.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sram_ctrl_bijection.3322028227
Short name T393
Test name
Test status
Simulation time 26287231888 ps
CPU time 68.48 seconds
Started Feb 25 02:48:10 PM PST 24
Finished Feb 25 02:49:19 PM PST 24
Peak memory 202620 kb
Host smart-c693a034-9bbf-4cf3-98aa-f77b118a0e8d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322028227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_bijection
.3322028227
Directory /workspace/30.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/30.sram_ctrl_executable.1769534860
Short name T823
Test name
Test status
Simulation time 48646488745 ps
CPU time 893.67 seconds
Started Feb 25 02:48:04 PM PST 24
Finished Feb 25 03:02:58 PM PST 24
Peak memory 367280 kb
Host smart-4f6de3d8-34d2-4be6-b44f-b20e4f94ba5e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769534860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_executab
le.1769534860
Directory /workspace/30.sram_ctrl_executable/latest

Test location /workspace/coverage/default/30.sram_ctrl_lc_escalation.765698162
Short name T852
Test name
Test status
Simulation time 1279000742 ps
CPU time 8.95 seconds
Started Feb 25 02:47:59 PM PST 24
Finished Feb 25 02:48:08 PM PST 24
Peak memory 202648 kb
Host smart-9cbd83ff-d1f0-4dac-bd32-6f16b2315813
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765698162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_lc_esc
alation.765698162
Directory /workspace/30.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/30.sram_ctrl_max_throughput.2898067886
Short name T703
Test name
Test status
Simulation time 109180056 ps
CPU time 52.92 seconds
Started Feb 25 02:48:00 PM PST 24
Finished Feb 25 02:48:54 PM PST 24
Peak memory 319556 kb
Host smart-6f2ad745-48e7-4cd8-8493-ca6e664e50a6
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898067886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sram_ctrl_max_throughput.2898067886
Directory /workspace/30.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2942875530
Short name T454
Test name
Test status
Simulation time 90621361 ps
CPU time 3.12 seconds
Started Feb 25 02:48:06 PM PST 24
Finished Feb 25 02:48:09 PM PST 24
Peak memory 210844 kb
Host smart-e3423b20-73b3-4936-85b3-eb53e2f70aba
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942875530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_mem_partial_access.2942875530
Directory /workspace/30.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_mem_walk.3703242251
Short name T716
Test name
Test status
Simulation time 140905897 ps
CPU time 4.47 seconds
Started Feb 25 02:48:09 PM PST 24
Finished Feb 25 02:48:14 PM PST 24
Peak memory 202560 kb
Host smart-000d10c6-603f-40cc-9c03-aa0222d7abd5
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703242251 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctr
l_mem_walk.3703242251
Directory /workspace/30.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/30.sram_ctrl_multiple_keys.4257388951
Short name T201
Test name
Test status
Simulation time 25815633678 ps
CPU time 977.8 seconds
Started Feb 25 02:48:06 PM PST 24
Finished Feb 25 03:04:24 PM PST 24
Peak memory 373400 kb
Host smart-0d7ad4c8-8afa-4aaf-9675-e09fb10e98f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257388951 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_multi
ple_keys.4257388951
Directory /workspace/30.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access.1415361299
Short name T560
Test name
Test status
Simulation time 1882346091 ps
CPU time 8.84 seconds
Started Feb 25 02:47:59 PM PST 24
Finished Feb 25 02:48:09 PM PST 24
Peak memory 202528 kb
Host smart-9934f6c6-c017-454c-9c5e-5409b4b0134d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415361299 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
sram_ctrl_partial_access.1415361299
Directory /workspace/30.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.684785763
Short name T721
Test name
Test status
Simulation time 57303444194 ps
CPU time 399.56 seconds
Started Feb 25 02:48:04 PM PST 24
Finished Feb 25 02:54:44 PM PST 24
Peak memory 202648 kb
Host smart-cb09e687-afc5-4ffb-9206-d5659f317772
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684785763 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 30.sram_ctrl_partial_access_b2b.684785763
Directory /workspace/30.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/30.sram_ctrl_ram_cfg.676329267
Short name T369
Test name
Test status
Simulation time 40928932 ps
CPU time 1.09 seconds
Started Feb 25 02:47:58 PM PST 24
Finished Feb 25 02:47:59 PM PST 24
Peak memory 202844 kb
Host smart-4262dfad-c889-4b5f-9adc-a8127450abfa
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676329267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_ram_cfg.676329267
Directory /workspace/30.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/30.sram_ctrl_regwen.3735737046
Short name T333
Test name
Test status
Simulation time 4473967283 ps
CPU time 2111.42 seconds
Started Feb 25 02:48:00 PM PST 24
Finished Feb 25 03:23:11 PM PST 24
Peak memory 370356 kb
Host smart-a3ae1388-2386-4940-9b1f-990fb06211f3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735737046 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_regwen.3735737046
Directory /workspace/30.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/30.sram_ctrl_smoke.1536459394
Short name T472
Test name
Test status
Simulation time 107755768 ps
CPU time 1.73 seconds
Started Feb 25 02:48:05 PM PST 24
Finished Feb 25 02:48:07 PM PST 24
Peak memory 202624 kb
Host smart-dd491046-5017-4f1e-b579-63a27360fee6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536459394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sram_ctrl_smoke.1536459394
Directory /workspace/30.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_all.3824737129
Short name T166
Test name
Test status
Simulation time 144682243332 ps
CPU time 1939.46 seconds
Started Feb 25 02:48:00 PM PST 24
Finished Feb 25 03:20:19 PM PST 24
Peak memory 374564 kb
Host smart-910dd7a1-3eb8-49bc-b721-01bd15d36285
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824737129 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 30.sram_ctrl_stress_all.3824737129
Directory /workspace/30.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sram_ctrl_stress_pipeline.3591398441
Short name T623
Test name
Test status
Simulation time 2197322954 ps
CPU time 162.18 seconds
Started Feb 25 02:48:09 PM PST 24
Finished Feb 25 02:50:51 PM PST 24
Peak memory 202696 kb
Host smart-aa036dad-befb-43c8-85e9-6d3010614f22
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591398441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.sram_ctrl_stress_pipeline.3591398441
Directory /workspace/30.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.3730030664
Short name T210
Test name
Test status
Simulation time 607859355 ps
CPU time 145.84 seconds
Started Feb 25 02:48:00 PM PST 24
Finished Feb 25 02:50:27 PM PST 24
Peak memory 364860 kb
Host smart-05b58566-8c78-42b5-948e-73d5e3ef0f49
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730030664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sram_ctrl_throughput_w_partial_write.3730030664
Directory /workspace/30.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/31.sram_ctrl_access_during_key_req.1685293767
Short name T719
Test name
Test status
Simulation time 5255115112 ps
CPU time 1087.44 seconds
Started Feb 25 02:48:13 PM PST 24
Finished Feb 25 03:06:21 PM PST 24
Peak memory 372404 kb
Host smart-5c4402e1-92e0-4151-8dc2-9750a5116b23
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685293767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 31.sram_ctrl_access_during_key_req.1685293767
Directory /workspace/31.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/31.sram_ctrl_alert_test.528715162
Short name T856
Test name
Test status
Simulation time 20120356 ps
CPU time 0.69 seconds
Started Feb 25 02:48:12 PM PST 24
Finished Feb 25 02:48:13 PM PST 24
Peak memory 201552 kb
Host smart-e5c84156-2d96-4334-83e5-d19fcc474f7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528715162 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.sram_ctrl_alert_test.528715162
Directory /workspace/31.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sram_ctrl_bijection.738116591
Short name T160
Test name
Test status
Simulation time 5454651900 ps
CPU time 30.19 seconds
Started Feb 25 02:48:03 PM PST 24
Finished Feb 25 02:48:34 PM PST 24
Peak memory 202604 kb
Host smart-29c40267-d168-457b-a0c5-a052b1ffc7b6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738116591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_bijection.
738116591
Directory /workspace/31.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/31.sram_ctrl_executable.1542021292
Short name T38
Test name
Test status
Simulation time 11531784771 ps
CPU time 937.08 seconds
Started Feb 25 02:48:11 PM PST 24
Finished Feb 25 03:03:48 PM PST 24
Peak memory 371356 kb
Host smart-5c9aa10a-5406-4cd2-b26f-ebe33cb395e2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542021292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_executab
le.1542021292
Directory /workspace/31.sram_ctrl_executable/latest

Test location /workspace/coverage/default/31.sram_ctrl_lc_escalation.2070104706
Short name T363
Test name
Test status
Simulation time 1224685048 ps
CPU time 5.88 seconds
Started Feb 25 02:48:10 PM PST 24
Finished Feb 25 02:48:16 PM PST 24
Peak memory 202640 kb
Host smart-6eee65d6-de7b-429e-945e-c4f5ce80add2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070104706 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_lc_es
calation.2070104706
Directory /workspace/31.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/31.sram_ctrl_max_throughput.1916783776
Short name T770
Test name
Test status
Simulation time 265286133 ps
CPU time 18.52 seconds
Started Feb 25 02:48:11 PM PST 24
Finished Feb 25 02:48:30 PM PST 24
Peak memory 257888 kb
Host smart-4eab9d4a-d2c9-44d0-a8de-4623340e9a47
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916783776 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sram_ctrl_max_throughput.1916783776
Directory /workspace/31.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2347400809
Short name T722
Test name
Test status
Simulation time 47577713 ps
CPU time 3.21 seconds
Started Feb 25 02:48:11 PM PST 24
Finished Feb 25 02:48:15 PM PST 24
Peak memory 212060 kb
Host smart-48bde4cd-f340-40de-8634-5cf17fc68f57
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347400809 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_mem_partial_access.2347400809
Directory /workspace/31.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_mem_walk.3225590274
Short name T342
Test name
Test status
Simulation time 305040168 ps
CPU time 5.57 seconds
Started Feb 25 02:48:11 PM PST 24
Finished Feb 25 02:48:17 PM PST 24
Peak memory 202552 kb
Host smart-d0175cd8-3612-4e7b-9b69-ea166f9ffd0c
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225590274 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctr
l_mem_walk.3225590274
Directory /workspace/31.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/31.sram_ctrl_multiple_keys.3284222748
Short name T471
Test name
Test status
Simulation time 17757966472 ps
CPU time 1644.53 seconds
Started Feb 25 02:48:00 PM PST 24
Finished Feb 25 03:15:25 PM PST 24
Peak memory 373460 kb
Host smart-9f9a5563-6ab9-4ac9-8f72-94a19a2e85a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284222748 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_multi
ple_keys.3284222748
Directory /workspace/31.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access.2601873379
Short name T857
Test name
Test status
Simulation time 4075932223 ps
CPU time 19.26 seconds
Started Feb 25 02:48:12 PM PST 24
Finished Feb 25 02:48:32 PM PST 24
Peak memory 202684 kb
Host smart-1abdb5b7-3bc2-4018-a8f1-b88c1d2aca6c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601873379 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
sram_ctrl_partial_access.2601873379
Directory /workspace/31.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2835495630
Short name T552
Test name
Test status
Simulation time 31308684390 ps
CPU time 353.22 seconds
Started Feb 25 02:48:18 PM PST 24
Finished Feb 25 02:54:13 PM PST 24
Peak memory 202628 kb
Host smart-9e0e4dba-8eb7-46d9-b545-f17afd509d9a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835495630 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 31.sram_ctrl_partial_access_b2b.2835495630
Directory /workspace/31.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/31.sram_ctrl_ram_cfg.1980976294
Short name T241
Test name
Test status
Simulation time 45191442 ps
CPU time 1.52 seconds
Started Feb 25 02:48:18 PM PST 24
Finished Feb 25 02:48:21 PM PST 24
Peak memory 202764 kb
Host smart-6ee871f5-4f50-4b6b-b79f-48f9cc835b43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980976294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_ram_cfg.1980976294
Directory /workspace/31.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/31.sram_ctrl_regwen.2137078055
Short name T186
Test name
Test status
Simulation time 16522303135 ps
CPU time 1384.08 seconds
Started Feb 25 02:48:14 PM PST 24
Finished Feb 25 03:11:18 PM PST 24
Peak memory 373408 kb
Host smart-0c9f85c4-b230-4762-8c2c-721cd932d8fc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137078055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_regwen.2137078055
Directory /workspace/31.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/31.sram_ctrl_smoke.3548633923
Short name T832
Test name
Test status
Simulation time 2304285484 ps
CPU time 16.87 seconds
Started Feb 25 02:48:09 PM PST 24
Finished Feb 25 02:48:26 PM PST 24
Peak memory 251132 kb
Host smart-d929fb64-798e-4521-9fcc-02f396824461
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548633923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sram_ctrl_smoke.3548633923
Directory /workspace/31.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_all.4129890845
Short name T640
Test name
Test status
Simulation time 8760103173 ps
CPU time 3112.58 seconds
Started Feb 25 02:48:18 PM PST 24
Finished Feb 25 03:40:11 PM PST 24
Peak memory 382048 kb
Host smart-6cff6b9b-ce2f-45e1-95fb-6d4e6e5468bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129890845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 31.sram_ctrl_stress_all.4129890845
Directory /workspace/31.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2093969700
Short name T803
Test name
Test status
Simulation time 10283043379 ps
CPU time 326.06 seconds
Started Feb 25 02:48:11 PM PST 24
Finished Feb 25 02:53:38 PM PST 24
Peak memory 202692 kb
Host smart-9a291135-69a3-47bd-a666-26116ad17440
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093969700 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.sram_ctrl_stress_pipeline.2093969700
Directory /workspace/31.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.2061476882
Short name T526
Test name
Test status
Simulation time 175502467 ps
CPU time 4.01 seconds
Started Feb 25 02:48:11 PM PST 24
Finished Feb 25 02:48:15 PM PST 24
Peak memory 219992 kb
Host smart-84983812-10ee-48f5-91c3-537983f072fb
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061476882 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sram_ctrl_throughput_w_partial_write.2061476882
Directory /workspace/31.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/32.sram_ctrl_access_during_key_req.2272202034
Short name T464
Test name
Test status
Simulation time 9283463568 ps
CPU time 529.35 seconds
Started Feb 25 02:48:12 PM PST 24
Finished Feb 25 02:57:02 PM PST 24
Peak memory 363392 kb
Host smart-e5613407-1178-42a2-86ef-310097496dc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272202034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 32.sram_ctrl_access_during_key_req.2272202034
Directory /workspace/32.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/32.sram_ctrl_alert_test.2390679922
Short name T638
Test name
Test status
Simulation time 127760225 ps
CPU time 0.64 seconds
Started Feb 25 02:48:13 PM PST 24
Finished Feb 25 02:48:14 PM PST 24
Peak memory 202448 kb
Host smart-104a372e-84a5-4789-b671-4409b5a9796f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390679922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.sram_ctrl_alert_test.2390679922
Directory /workspace/32.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sram_ctrl_bijection.160597323
Short name T254
Test name
Test status
Simulation time 4825647322 ps
CPU time 60.35 seconds
Started Feb 25 02:48:10 PM PST 24
Finished Feb 25 02:49:11 PM PST 24
Peak memory 202616 kb
Host smart-470b12bc-03cb-4a25-80b3-91698be1d682
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160597323 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_bijection.
160597323
Directory /workspace/32.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/32.sram_ctrl_executable.3927734719
Short name T559
Test name
Test status
Simulation time 2824138337 ps
CPU time 843.39 seconds
Started Feb 25 02:48:13 PM PST 24
Finished Feb 25 03:02:17 PM PST 24
Peak memory 374124 kb
Host smart-09912942-b433-47f7-8f1f-d045b9a57d9d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927734719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_executab
le.3927734719
Directory /workspace/32.sram_ctrl_executable/latest

Test location /workspace/coverage/default/32.sram_ctrl_lc_escalation.2441244393
Short name T455
Test name
Test status
Simulation time 512802898 ps
CPU time 7.75 seconds
Started Feb 25 02:48:18 PM PST 24
Finished Feb 25 02:48:27 PM PST 24
Peak memory 210300 kb
Host smart-ec52739f-d986-42f6-84d2-22351eecdea1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441244393 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_lc_es
calation.2441244393
Directory /workspace/32.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/32.sram_ctrl_max_throughput.971876684
Short name T556
Test name
Test status
Simulation time 810985543 ps
CPU time 29.75 seconds
Started Feb 25 02:48:13 PM PST 24
Finished Feb 25 02:48:43 PM PST 24
Peak memory 284004 kb
Host smart-3db69099-1385-4a8d-baf8-f21e3b0fda52
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971876684 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.sram_ctrl_max_throughput.971876684
Directory /workspace/32.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_partial_access.1253252565
Short name T760
Test name
Test status
Simulation time 535691390 ps
CPU time 3.3 seconds
Started Feb 25 02:48:12 PM PST 24
Finished Feb 25 02:48:16 PM PST 24
Peak memory 210864 kb
Host smart-97cba73f-e684-4910-930e-d8e9cb1de656
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253252565 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_mem_partial_access.1253252565
Directory /workspace/32.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_mem_walk.441317283
Short name T609
Test name
Test status
Simulation time 292059550 ps
CPU time 5.47 seconds
Started Feb 25 02:48:12 PM PST 24
Finished Feb 25 02:48:18 PM PST 24
Peak memory 202528 kb
Host smart-0ecab220-b9b4-47cd-9a31-64e6e5818209
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441317283 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl
_mem_walk.441317283
Directory /workspace/32.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/32.sram_ctrl_multiple_keys.1783251400
Short name T133
Test name
Test status
Simulation time 4460050405 ps
CPU time 996.3 seconds
Started Feb 25 02:48:09 PM PST 24
Finished Feb 25 03:04:46 PM PST 24
Peak memory 373456 kb
Host smart-069620cd-cd75-454f-b898-20c78fbc8c44
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783251400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_multi
ple_keys.1783251400
Directory /workspace/32.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access.1752775531
Short name T202
Test name
Test status
Simulation time 725950681 ps
CPU time 31.07 seconds
Started Feb 25 02:48:18 PM PST 24
Finished Feb 25 02:48:50 PM PST 24
Peak memory 287980 kb
Host smart-a291d78f-9c7d-4c27-8717-c05583efcb8f
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752775531 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
sram_ctrl_partial_access.1752775531
Directory /workspace/32.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.3494898442
Short name T238
Test name
Test status
Simulation time 89262039987 ps
CPU time 509.95 seconds
Started Feb 25 02:48:13 PM PST 24
Finished Feb 25 02:56:43 PM PST 24
Peak memory 202688 kb
Host smart-284c3745-c1ad-4ac6-a1ea-7d7f21c977ec
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494898442 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_partial_access_b2b.3494898442
Directory /workspace/32.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/32.sram_ctrl_ram_cfg.672940138
Short name T494
Test name
Test status
Simulation time 80134224 ps
CPU time 0.84 seconds
Started Feb 25 02:48:12 PM PST 24
Finished Feb 25 02:48:14 PM PST 24
Peak memory 202540 kb
Host smart-07edcd84-8315-4881-88cb-ac00797a9372
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672940138 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_ram_cfg.672940138
Directory /workspace/32.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/32.sram_ctrl_regwen.1531135112
Short name T183
Test name
Test status
Simulation time 1783213983 ps
CPU time 506.17 seconds
Started Feb 25 02:48:09 PM PST 24
Finished Feb 25 02:56:36 PM PST 24
Peak memory 367200 kb
Host smart-b7c7a161-82d3-409f-8bff-305ef12ca27f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531135112 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_regwen.1531135112
Directory /workspace/32.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/32.sram_ctrl_smoke.1904173633
Short name T424
Test name
Test status
Simulation time 163491348 ps
CPU time 10.11 seconds
Started Feb 25 02:48:13 PM PST 24
Finished Feb 25 02:48:24 PM PST 24
Peak memory 202640 kb
Host smart-080a45ce-b78f-4421-b529-6377e87a3f0e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904173633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sram_ctrl_smoke.1904173633
Directory /workspace/32.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_all.158498923
Short name T890
Test name
Test status
Simulation time 112905755273 ps
CPU time 1497.62 seconds
Started Feb 25 02:48:12 PM PST 24
Finished Feb 25 03:13:10 PM PST 24
Peak memory 367212 kb
Host smart-39e35fc3-79bc-4068-8ed1-33155ebdae57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158498923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 32.sram_ctrl_stress_all.158498923
Directory /workspace/32.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1623030289
Short name T442
Test name
Test status
Simulation time 3386857355 ps
CPU time 314.57 seconds
Started Feb 25 02:48:18 PM PST 24
Finished Feb 25 02:53:34 PM PST 24
Peak memory 202712 kb
Host smart-a1c1d335-3bce-4056-8cb8-4f455eb12ed6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623030289 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.sram_ctrl_stress_pipeline.1623030289
Directory /workspace/32.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.2013108887
Short name T450
Test name
Test status
Simulation time 158792278 ps
CPU time 108.68 seconds
Started Feb 25 02:48:11 PM PST 24
Finished Feb 25 02:50:00 PM PST 24
Peak memory 366724 kb
Host smart-ec5ec807-870b-4114-b3f7-a51853ae00ce
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013108887 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sram_ctrl_throughput_w_partial_write.2013108887
Directory /workspace/32.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/33.sram_ctrl_access_during_key_req.2925637159
Short name T727
Test name
Test status
Simulation time 1548653459 ps
CPU time 624.28 seconds
Started Feb 25 02:48:23 PM PST 24
Finished Feb 25 02:58:48 PM PST 24
Peak memory 371324 kb
Host smart-906a4fff-edc3-4b27-8705-4595551c6446
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925637159 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 33.sram_ctrl_access_during_key_req.2925637159
Directory /workspace/33.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/33.sram_ctrl_alert_test.2031038459
Short name T296
Test name
Test status
Simulation time 57999106 ps
CPU time 0.68 seconds
Started Feb 25 02:48:24 PM PST 24
Finished Feb 25 02:48:25 PM PST 24
Peak memory 201496 kb
Host smart-52b65e03-aa4f-4747-a6a4-e8ede3efcc51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031038459 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.sram_ctrl_alert_test.2031038459
Directory /workspace/33.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sram_ctrl_bijection.3295393461
Short name T390
Test name
Test status
Simulation time 2780100118 ps
CPU time 56.65 seconds
Started Feb 25 02:48:19 PM PST 24
Finished Feb 25 02:49:16 PM PST 24
Peak memory 202660 kb
Host smart-6cdb9a0d-7b09-40b8-95e3-6179dc138022
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295393461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_bijection
.3295393461
Directory /workspace/33.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/33.sram_ctrl_executable.313367194
Short name T116
Test name
Test status
Simulation time 8605950094 ps
CPU time 972.48 seconds
Started Feb 25 02:48:19 PM PST 24
Finished Feb 25 03:04:32 PM PST 24
Peak memory 374428 kb
Host smart-59b101b5-d47f-4355-aae4-e7d9df7e2409
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313367194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_executabl
e.313367194
Directory /workspace/33.sram_ctrl_executable/latest

Test location /workspace/coverage/default/33.sram_ctrl_lc_escalation.429853045
Short name T628
Test name
Test status
Simulation time 795722297 ps
CPU time 11.25 seconds
Started Feb 25 02:48:18 PM PST 24
Finished Feb 25 02:48:31 PM PST 24
Peak memory 210832 kb
Host smart-28ab56d7-fc19-4604-87e1-2c2d018e331b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429853045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_lc_esc
alation.429853045
Directory /workspace/33.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/33.sram_ctrl_max_throughput.4115648510
Short name T843
Test name
Test status
Simulation time 105188156 ps
CPU time 8.22 seconds
Started Feb 25 02:48:23 PM PST 24
Finished Feb 25 02:48:31 PM PST 24
Peak memory 234816 kb
Host smart-ef7432a9-5ac6-4589-baa9-2853800aa917
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115648510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 33.sram_ctrl_max_throughput.4115648510
Directory /workspace/33.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_partial_access.2565577715
Short name T888
Test name
Test status
Simulation time 86224522 ps
CPU time 2.98 seconds
Started Feb 25 02:48:19 PM PST 24
Finished Feb 25 02:48:23 PM PST 24
Peak memory 210788 kb
Host smart-22099cb6-e3eb-4cc8-a5d7-4a3d253b6c70
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565577715 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_mem_partial_access.2565577715
Directory /workspace/33.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_mem_walk.493631599
Short name T300
Test name
Test status
Simulation time 1237606511 ps
CPU time 10.57 seconds
Started Feb 25 02:48:21 PM PST 24
Finished Feb 25 02:48:33 PM PST 24
Peak memory 202584 kb
Host smart-8b0ab451-e411-4d72-900e-56fbeb4329a0
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493631599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl
_mem_walk.493631599
Directory /workspace/33.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/33.sram_ctrl_multiple_keys.767197750
Short name T626
Test name
Test status
Simulation time 21886767821 ps
CPU time 910.1 seconds
Started Feb 25 02:48:12 PM PST 24
Finished Feb 25 03:03:23 PM PST 24
Peak memory 375468 kb
Host smart-08ab464b-5009-43bb-a0e4-3c23beb898cf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767197750 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_multip
le_keys.767197750
Directory /workspace/33.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access.1830817400
Short name T352
Test name
Test status
Simulation time 118912438 ps
CPU time 3.88 seconds
Started Feb 25 02:48:24 PM PST 24
Finished Feb 25 02:48:28 PM PST 24
Peak memory 211512 kb
Host smart-756dd693-7bf6-442a-95c7-f026a6eb3b05
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830817400 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
sram_ctrl_partial_access.1830817400
Directory /workspace/33.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2359837789
Short name T849
Test name
Test status
Simulation time 24558654017 ps
CPU time 273.9 seconds
Started Feb 25 02:48:19 PM PST 24
Finished Feb 25 02:52:54 PM PST 24
Peak memory 202688 kb
Host smart-4500b1ce-483f-43ce-842f-a778dc7b8775
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359837789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 33.sram_ctrl_partial_access_b2b.2359837789
Directory /workspace/33.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/33.sram_ctrl_ram_cfg.2549761509
Short name T779
Test name
Test status
Simulation time 31891655 ps
CPU time 0.87 seconds
Started Feb 25 02:48:17 PM PST 24
Finished Feb 25 02:48:18 PM PST 24
Peak memory 202568 kb
Host smart-7aed7c69-63da-46b7-84c0-74a1e590f342
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549761509 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_ram_cfg.2549761509
Directory /workspace/33.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/33.sram_ctrl_regwen.807156747
Short name T767
Test name
Test status
Simulation time 5992637036 ps
CPU time 180.65 seconds
Started Feb 25 02:48:21 PM PST 24
Finished Feb 25 02:51:22 PM PST 24
Peak memory 370220 kb
Host smart-a0a8f9d1-d60a-4dcc-a740-a9006d0df693
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807156747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_regwen.807156747
Directory /workspace/33.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/33.sram_ctrl_smoke.1762570512
Short name T608
Test name
Test status
Simulation time 2368538961 ps
CPU time 70.28 seconds
Started Feb 25 02:48:11 PM PST 24
Finished Feb 25 02:49:22 PM PST 24
Peak memory 320396 kb
Host smart-2cbb833e-ec33-4856-a57a-22629036cb0a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762570512 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sram_ctrl_smoke.1762570512
Directory /workspace/33.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_all.1489596496
Short name T647
Test name
Test status
Simulation time 7959647135 ps
CPU time 86.83 seconds
Started Feb 25 02:48:16 PM PST 24
Finished Feb 25 02:49:43 PM PST 24
Peak memory 289964 kb
Host smart-3f89d879-3560-4f5c-8959-dc3e1048ecb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489596496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 33.sram_ctrl_stress_all.1489596496
Directory /workspace/33.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1076011028
Short name T711
Test name
Test status
Simulation time 2608292074 ps
CPU time 235.87 seconds
Started Feb 25 02:48:23 PM PST 24
Finished Feb 25 02:52:20 PM PST 24
Peak memory 202696 kb
Host smart-5b9c914e-a53b-43d6-88e6-4a4531b1d9ce
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076011028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.sram_ctrl_stress_pipeline.1076011028
Directory /workspace/33.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2531156394
Short name T189
Test name
Test status
Simulation time 576122958 ps
CPU time 63.17 seconds
Started Feb 25 02:48:18 PM PST 24
Finished Feb 25 02:49:22 PM PST 24
Peak memory 311516 kb
Host smart-0d583411-433e-4ccc-9d94-c8667133e72c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531156394 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sram_ctrl_throughput_w_partial_write.2531156394
Directory /workspace/33.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/34.sram_ctrl_access_during_key_req.2300587859
Short name T633
Test name
Test status
Simulation time 3788713556 ps
CPU time 1244.15 seconds
Started Feb 25 02:48:19 PM PST 24
Finished Feb 25 03:09:04 PM PST 24
Peak memory 373440 kb
Host smart-7b519c4e-1c5e-41dd-9c51-13e4d5d3126e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300587859 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 34.sram_ctrl_access_during_key_req.2300587859
Directory /workspace/34.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/34.sram_ctrl_alert_test.131210787
Short name T250
Test name
Test status
Simulation time 30930219 ps
CPU time 0.63 seconds
Started Feb 25 02:48:29 PM PST 24
Finished Feb 25 02:48:30 PM PST 24
Peak memory 201668 kb
Host smart-d655a1e2-f57a-4e46-bc9b-7fac28afb6cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131210787 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.sram_ctrl_alert_test.131210787
Directory /workspace/34.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sram_ctrl_bijection.1224701328
Short name T203
Test name
Test status
Simulation time 11258793426 ps
CPU time 46.7 seconds
Started Feb 25 02:48:19 PM PST 24
Finished Feb 25 02:49:07 PM PST 24
Peak memory 202620 kb
Host smart-975e609b-4b8b-43ee-9c3c-7e1237d04876
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224701328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_bijection
.1224701328
Directory /workspace/34.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/34.sram_ctrl_executable.1482554211
Short name T505
Test name
Test status
Simulation time 18561758934 ps
CPU time 984.08 seconds
Started Feb 25 02:48:24 PM PST 24
Finished Feb 25 03:04:49 PM PST 24
Peak memory 373012 kb
Host smart-3ec62186-aa54-4485-acef-86a0cec1038f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482554211 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_executab
le.1482554211
Directory /workspace/34.sram_ctrl_executable/latest

Test location /workspace/coverage/default/34.sram_ctrl_lc_escalation.3845825048
Short name T245
Test name
Test status
Simulation time 611922073 ps
CPU time 7.9 seconds
Started Feb 25 02:48:19 PM PST 24
Finished Feb 25 02:48:28 PM PST 24
Peak memory 210776 kb
Host smart-7295f0a0-49c1-43dd-b9b2-f702276a61c6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845825048 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_lc_es
calation.3845825048
Directory /workspace/34.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/34.sram_ctrl_max_throughput.4043975619
Short name T625
Test name
Test status
Simulation time 797491496 ps
CPU time 35.14 seconds
Started Feb 25 02:48:15 PM PST 24
Finished Feb 25 02:48:51 PM PST 24
Peak memory 292592 kb
Host smart-225677e8-5afe-4529-822d-d5c0fa18e6d1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043975619 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 34.sram_ctrl_max_throughput.4043975619
Directory /workspace/34.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_partial_access.459395722
Short name T678
Test name
Test status
Simulation time 126346168 ps
CPU time 4.67 seconds
Started Feb 25 02:48:28 PM PST 24
Finished Feb 25 02:48:33 PM PST 24
Peak memory 210820 kb
Host smart-c388611e-6bf3-4512-8991-68acc7ec8ac0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459395722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.sram_ctrl_mem_partial_access.459395722
Directory /workspace/34.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_mem_walk.3166660106
Short name T137
Test name
Test status
Simulation time 525526379 ps
CPU time 8.05 seconds
Started Feb 25 02:48:26 PM PST 24
Finished Feb 25 02:48:34 PM PST 24
Peak memory 202560 kb
Host smart-22f5f8bd-2278-4346-9225-9fed8c043149
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166660106 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctr
l_mem_walk.3166660106
Directory /workspace/34.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/34.sram_ctrl_multiple_keys.2539543767
Short name T704
Test name
Test status
Simulation time 90566306497 ps
CPU time 1361.5 seconds
Started Feb 25 02:48:21 PM PST 24
Finished Feb 25 03:11:03 PM PST 24
Peak memory 370768 kb
Host smart-af447709-55cc-4734-bf12-fc6bcd984e79
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539543767 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_multi
ple_keys.2539543767
Directory /workspace/34.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access.3539451705
Short name T216
Test name
Test status
Simulation time 1162089744 ps
CPU time 17.01 seconds
Started Feb 25 02:48:22 PM PST 24
Finished Feb 25 02:48:40 PM PST 24
Peak memory 202628 kb
Host smart-93f6a4a5-b442-4bb4-8c8e-1da58d3ae65b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539451705 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
sram_ctrl_partial_access.3539451705
Directory /workspace/34.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.590380037
Short name T541
Test name
Test status
Simulation time 21962514416 ps
CPU time 250.92 seconds
Started Feb 25 02:48:24 PM PST 24
Finished Feb 25 02:52:35 PM PST 24
Peak memory 202620 kb
Host smart-7ecaead4-3bef-47ac-bee6-6d09682883b4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590380037 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 34.sram_ctrl_partial_access_b2b.590380037
Directory /workspace/34.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/34.sram_ctrl_ram_cfg.905480347
Short name T41
Test name
Test status
Simulation time 25618822 ps
CPU time 1.07 seconds
Started Feb 25 02:48:21 PM PST 24
Finished Feb 25 02:48:23 PM PST 24
Peak memory 202904 kb
Host smart-dd51e5aa-4c95-441e-9c37-b8b35f748324
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905480347 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_ram_cfg.905480347
Directory /workspace/34.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/34.sram_ctrl_regwen.1110992123
Short name T460
Test name
Test status
Simulation time 11444632960 ps
CPU time 431.05 seconds
Started Feb 25 02:48:23 PM PST 24
Finished Feb 25 02:55:34 PM PST 24
Peak memory 316152 kb
Host smart-03329c8b-d263-4efb-99f7-e665b27732b9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110992123 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_regwen.1110992123
Directory /workspace/34.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/34.sram_ctrl_smoke.1627242740
Short name T336
Test name
Test status
Simulation time 588078334 ps
CPU time 13.4 seconds
Started Feb 25 02:48:20 PM PST 24
Finished Feb 25 02:48:33 PM PST 24
Peak memory 202592 kb
Host smart-f5aceb31-0a70-4ca7-91c1-9121648be08c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627242740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sram_ctrl_smoke.1627242740
Directory /workspace/34.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sram_ctrl_stress_pipeline.842861680
Short name T540
Test name
Test status
Simulation time 9217248327 ps
CPU time 215.58 seconds
Started Feb 25 02:48:15 PM PST 24
Finished Feb 25 02:51:51 PM PST 24
Peak memory 202692 kb
Host smart-461eaa71-9280-41af-8b1d-5215c379d3b4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842861680 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.sram_ctrl_stress_pipeline.842861680
Directory /workspace/34.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.1448226833
Short name T327
Test name
Test status
Simulation time 203793860 ps
CPU time 9.04 seconds
Started Feb 25 02:48:19 PM PST 24
Finished Feb 25 02:48:29 PM PST 24
Peak memory 235336 kb
Host smart-d3448325-8c56-483e-846b-6bdea2bf6378
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448226833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sram_ctrl_throughput_w_partial_write.1448226833
Directory /workspace/34.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2149504821
Short name T582
Test name
Test status
Simulation time 7703025185 ps
CPU time 853.24 seconds
Started Feb 25 02:48:29 PM PST 24
Finished Feb 25 03:02:42 PM PST 24
Peak memory 373472 kb
Host smart-f4b2ca03-c55f-461f-bf75-201f0820e213
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149504821 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 35.sram_ctrl_access_during_key_req.2149504821
Directory /workspace/35.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/35.sram_ctrl_alert_test.2198626354
Short name T171
Test name
Test status
Simulation time 16536314 ps
CPU time 0.66 seconds
Started Feb 25 02:48:34 PM PST 24
Finished Feb 25 02:48:35 PM PST 24
Peak memory 201500 kb
Host smart-7b737b6e-74cc-458b-9f09-451837e068d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198626354 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.sram_ctrl_alert_test.2198626354
Directory /workspace/35.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sram_ctrl_bijection.2483150089
Short name T215
Test name
Test status
Simulation time 567527050 ps
CPU time 38.52 seconds
Started Feb 25 02:48:33 PM PST 24
Finished Feb 25 02:49:12 PM PST 24
Peak memory 202632 kb
Host smart-e14fc695-6804-4add-8591-58976de18a48
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483150089 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_bijection
.2483150089
Directory /workspace/35.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/35.sram_ctrl_executable.1689636121
Short name T443
Test name
Test status
Simulation time 90398183536 ps
CPU time 744.22 seconds
Started Feb 25 02:48:28 PM PST 24
Finished Feb 25 03:00:52 PM PST 24
Peak memory 366484 kb
Host smart-39c92755-844e-4191-b081-ff6d8bede9e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689636121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_executab
le.1689636121
Directory /workspace/35.sram_ctrl_executable/latest

Test location /workspace/coverage/default/35.sram_ctrl_lc_escalation.3340287693
Short name T33
Test name
Test status
Simulation time 846281588 ps
CPU time 11.3 seconds
Started Feb 25 02:48:28 PM PST 24
Finished Feb 25 02:48:39 PM PST 24
Peak memory 213476 kb
Host smart-fa1ff973-0c00-4d7c-8e64-5a428276e74f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340287693 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_lc_es
calation.3340287693
Directory /workspace/35.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/35.sram_ctrl_max_throughput.3705919746
Short name T266
Test name
Test status
Simulation time 70265709 ps
CPU time 7.79 seconds
Started Feb 25 02:48:28 PM PST 24
Finished Feb 25 02:48:36 PM PST 24
Peak memory 236584 kb
Host smart-6eacbe61-7e54-4e91-ac10-a253e9eb429b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705919746 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 35.sram_ctrl_max_throughput.3705919746
Directory /workspace/35.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_partial_access.173388642
Short name T83
Test name
Test status
Simulation time 89359668 ps
CPU time 3.18 seconds
Started Feb 25 02:48:38 PM PST 24
Finished Feb 25 02:48:41 PM PST 24
Peak memory 211836 kb
Host smart-4118a361-8d23-412d-b5c2-e01b20baef85
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173388642 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.sram_ctrl_mem_partial_access.173388642
Directory /workspace/35.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_mem_walk.3258201906
Short name T407
Test name
Test status
Simulation time 684122523 ps
CPU time 5.23 seconds
Started Feb 25 02:48:34 PM PST 24
Finished Feb 25 02:48:40 PM PST 24
Peak memory 202540 kb
Host smart-d8905cdb-9e71-4138-8781-d2f0cca21479
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258201906 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctr
l_mem_walk.3258201906
Directory /workspace/35.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/35.sram_ctrl_multiple_keys.2318871476
Short name T618
Test name
Test status
Simulation time 3216042633 ps
CPU time 272.84 seconds
Started Feb 25 02:48:33 PM PST 24
Finished Feb 25 02:53:06 PM PST 24
Peak memory 370644 kb
Host smart-2af62934-b775-4afa-99d6-c3ccc88a61d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318871476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_multi
ple_keys.2318871476
Directory /workspace/35.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access.566778097
Short name T566
Test name
Test status
Simulation time 235182329 ps
CPU time 2.16 seconds
Started Feb 25 02:48:27 PM PST 24
Finished Feb 25 02:48:29 PM PST 24
Peak memory 203576 kb
Host smart-59bacc5e-b6a9-4097-9bd3-e15a0e96167c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566778097 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.s
ram_ctrl_partial_access.566778097
Directory /workspace/35.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1559268857
Short name T361
Test name
Test status
Simulation time 31023476500 ps
CPU time 389.28 seconds
Started Feb 25 02:48:28 PM PST 24
Finished Feb 25 02:54:58 PM PST 24
Peak memory 202676 kb
Host smart-3e021fcf-77b1-4afb-a19c-d1b9163e4207
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559268857 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 35.sram_ctrl_partial_access_b2b.1559268857
Directory /workspace/35.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/35.sram_ctrl_ram_cfg.2782686346
Short name T846
Test name
Test status
Simulation time 31505814 ps
CPU time 0.86 seconds
Started Feb 25 02:48:41 PM PST 24
Finished Feb 25 02:48:42 PM PST 24
Peak memory 202588 kb
Host smart-522121b5-2d2e-43cd-a865-acdc4fcafe92
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782686346 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_ram_cfg.2782686346
Directory /workspace/35.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/35.sram_ctrl_regwen.472813977
Short name T889
Test name
Test status
Simulation time 2183660773 ps
CPU time 290.44 seconds
Started Feb 25 02:48:40 PM PST 24
Finished Feb 25 02:53:31 PM PST 24
Peak memory 363916 kb
Host smart-979e42f9-eaa1-4ee6-8256-f27346a18eb2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472813977 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_regwen.472813977
Directory /workspace/35.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/35.sram_ctrl_smoke.1388965953
Short name T397
Test name
Test status
Simulation time 80000062 ps
CPU time 18.71 seconds
Started Feb 25 02:48:28 PM PST 24
Finished Feb 25 02:48:47 PM PST 24
Peak memory 257616 kb
Host smart-d2c891e7-e9f2-4cc5-a322-570c0841cc46
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388965953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sram_ctrl_smoke.1388965953
Directory /workspace/35.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_all.1687278314
Short name T501
Test name
Test status
Simulation time 175911084226 ps
CPU time 4456.11 seconds
Started Feb 25 02:48:33 PM PST 24
Finished Feb 25 04:02:50 PM PST 24
Peak memory 374424 kb
Host smart-66e6d797-71f7-423c-aa41-6d94bf90bb44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687278314 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 35.sram_ctrl_stress_all.1687278314
Directory /workspace/35.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sram_ctrl_stress_pipeline.828966127
Short name T375
Test name
Test status
Simulation time 3319906402 ps
CPU time 318.95 seconds
Started Feb 25 02:48:28 PM PST 24
Finished Feb 25 02:53:47 PM PST 24
Peak memory 202700 kb
Host smart-935825a6-d552-4445-8145-e60d6445d7ab
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828966127 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.sram_ctrl_stress_pipeline.828966127
Directory /workspace/35.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.4007322841
Short name T800
Test name
Test status
Simulation time 159305700 ps
CPU time 3.38 seconds
Started Feb 25 02:48:27 PM PST 24
Finished Feb 25 02:48:30 PM PST 24
Peak memory 217320 kb
Host smart-5a57a9dc-3c55-40e3-a5ca-eb8fee5ad5b1
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007322841 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sram_ctrl_throughput_w_partial_write.4007322841
Directory /workspace/35.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/36.sram_ctrl_access_during_key_req.709144915
Short name T470
Test name
Test status
Simulation time 13550494874 ps
CPU time 833.45 seconds
Started Feb 25 02:48:34 PM PST 24
Finished Feb 25 03:02:28 PM PST 24
Peak memory 362100 kb
Host smart-1d730f54-55d8-464d-a988-4994e0e38ed2
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709144915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 36.sram_ctrl_access_during_key_req.709144915
Directory /workspace/36.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/36.sram_ctrl_alert_test.1704241247
Short name T220
Test name
Test status
Simulation time 17679975 ps
CPU time 0.66 seconds
Started Feb 25 02:48:55 PM PST 24
Finished Feb 25 02:48:55 PM PST 24
Peak memory 201484 kb
Host smart-c11de218-f60b-4cca-9965-793893c593fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704241247 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.sram_ctrl_alert_test.1704241247
Directory /workspace/36.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sram_ctrl_bijection.1444379008
Short name T190
Test name
Test status
Simulation time 5870419851 ps
CPU time 64.74 seconds
Started Feb 25 02:48:36 PM PST 24
Finished Feb 25 02:49:41 PM PST 24
Peak memory 202700 kb
Host smart-3e173cb5-8daa-4fb9-af6f-dc8391e15f39
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444379008 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_bijection
.1444379008
Directory /workspace/36.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/36.sram_ctrl_executable.3532100189
Short name T401
Test name
Test status
Simulation time 26307103208 ps
CPU time 427.49 seconds
Started Feb 25 02:48:45 PM PST 24
Finished Feb 25 02:55:53 PM PST 24
Peak memory 324116 kb
Host smart-c9e6c9ec-a1fa-43ed-9f1a-76b39173c939
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532100189 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_executab
le.3532100189
Directory /workspace/36.sram_ctrl_executable/latest

Test location /workspace/coverage/default/36.sram_ctrl_lc_escalation.3912436090
Short name T518
Test name
Test status
Simulation time 1833804048 ps
CPU time 13.53 seconds
Started Feb 25 02:48:35 PM PST 24
Finished Feb 25 02:48:49 PM PST 24
Peak memory 202664 kb
Host smart-403e1d1b-9c17-461f-a9de-6da6da60f067
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912436090 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_lc_es
calation.3912436090
Directory /workspace/36.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/36.sram_ctrl_max_throughput.1258421294
Short name T380
Test name
Test status
Simulation time 182649151 ps
CPU time 5.2 seconds
Started Feb 25 02:48:42 PM PST 24
Finished Feb 25 02:48:47 PM PST 24
Peak memory 225336 kb
Host smart-b02ab4ef-50f1-4e77-ae64-812f4539a58c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258421294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sram_ctrl_max_throughput.1258421294
Directory /workspace/36.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_partial_access.143524209
Short name T529
Test name
Test status
Simulation time 153052173 ps
CPU time 4.9 seconds
Started Feb 25 02:48:46 PM PST 24
Finished Feb 25 02:48:51 PM PST 24
Peak memory 210824 kb
Host smart-904dd198-710d-43b5-a405-160aa8da3dc1
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143524209 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.sram_ctrl_mem_partial_access.143524209
Directory /workspace/36.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_mem_walk.185688258
Short name T145
Test name
Test status
Simulation time 1095009792 ps
CPU time 9.05 seconds
Started Feb 25 02:48:54 PM PST 24
Finished Feb 25 02:49:04 PM PST 24
Peak memory 202552 kb
Host smart-5590face-4a29-4869-872a-76115a8ed2cc
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185688258 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl
_mem_walk.185688258
Directory /workspace/36.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/36.sram_ctrl_multiple_keys.3517890261
Short name T315
Test name
Test status
Simulation time 5617837001 ps
CPU time 253.66 seconds
Started Feb 25 02:48:35 PM PST 24
Finished Feb 25 02:52:49 PM PST 24
Peak memory 351740 kb
Host smart-cfe0e02a-db74-44f7-bb05-4bae3ccfc499
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517890261 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_multi
ple_keys.3517890261
Directory /workspace/36.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access.582643637
Short name T836
Test name
Test status
Simulation time 91959997 ps
CPU time 4.37 seconds
Started Feb 25 02:48:35 PM PST 24
Finished Feb 25 02:48:39 PM PST 24
Peak memory 202632 kb
Host smart-4ed9a3a3-eba8-415f-8564-bca713cb6826
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582643637 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.s
ram_ctrl_partial_access.582643637
Directory /workspace/36.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2012325614
Short name T666
Test name
Test status
Simulation time 12663884659 ps
CPU time 457.92 seconds
Started Feb 25 02:48:34 PM PST 24
Finished Feb 25 02:56:12 PM PST 24
Peak memory 202696 kb
Host smart-8cb1b108-9b34-4298-8c4c-8c8bf6131c4e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012325614 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_partial_access_b2b.2012325614
Directory /workspace/36.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/36.sram_ctrl_ram_cfg.3969821678
Short name T162
Test name
Test status
Simulation time 26946551 ps
CPU time 1.11 seconds
Started Feb 25 02:48:45 PM PST 24
Finished Feb 25 02:48:46 PM PST 24
Peak memory 202900 kb
Host smart-93bd108c-2dba-4819-9270-740f657c9629
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969821678 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_ram_cfg.3969821678
Directory /workspace/36.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/36.sram_ctrl_regwen.122473797
Short name T772
Test name
Test status
Simulation time 7142336678 ps
CPU time 375.14 seconds
Started Feb 25 02:48:45 PM PST 24
Finished Feb 25 02:55:00 PM PST 24
Peak memory 357916 kb
Host smart-a4c0e73d-c7b4-4aea-9b10-1653484776bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122473797 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_regwen.122473797
Directory /workspace/36.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/36.sram_ctrl_smoke.2017160976
Short name T272
Test name
Test status
Simulation time 54718617 ps
CPU time 1.54 seconds
Started Feb 25 02:48:41 PM PST 24
Finished Feb 25 02:48:42 PM PST 24
Peak memory 202540 kb
Host smart-bc972725-3936-4117-82a2-9906acf77ede
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017160976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sram_ctrl_smoke.2017160976
Directory /workspace/36.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_all.952384469
Short name T786
Test name
Test status
Simulation time 26558641065 ps
CPU time 759.91 seconds
Started Feb 25 02:48:44 PM PST 24
Finished Feb 25 03:01:25 PM PST 24
Peak memory 374476 kb
Host smart-d44bc098-8bcc-4fb3-962e-648105e1fc1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952384469 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 36.sram_ctrl_stress_all.952384469
Directory /workspace/36.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sram_ctrl_stress_pipeline.248614736
Short name T723
Test name
Test status
Simulation time 2724489737 ps
CPU time 263.89 seconds
Started Feb 25 02:48:42 PM PST 24
Finished Feb 25 02:53:06 PM PST 24
Peak memory 202664 kb
Host smart-2df0929d-858d-4287-84dc-78ed5fefc909
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248614736 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.sram_ctrl_stress_pipeline.248614736
Directory /workspace/36.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1332124886
Short name T400
Test name
Test status
Simulation time 150033356 ps
CPU time 112.21 seconds
Started Feb 25 02:48:36 PM PST 24
Finished Feb 25 02:50:29 PM PST 24
Peak memory 355864 kb
Host smart-e3a0b8f4-adc3-4417-be40-8bfbfc43d23c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332124886 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 36.sram_ctrl_throughput_w_partial_write.1332124886
Directory /workspace/36.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/37.sram_ctrl_access_during_key_req.4120839719
Short name T639
Test name
Test status
Simulation time 1963415120 ps
CPU time 432.03 seconds
Started Feb 25 02:48:44 PM PST 24
Finished Feb 25 02:55:56 PM PST 24
Peak memory 372464 kb
Host smart-48c8efda-45b9-446c-b80c-cf690010c27e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120839719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 37.sram_ctrl_access_during_key_req.4120839719
Directory /workspace/37.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/37.sram_ctrl_alert_test.1151871510
Short name T737
Test name
Test status
Simulation time 31292910 ps
CPU time 0.63 seconds
Started Feb 25 02:48:45 PM PST 24
Finished Feb 25 02:48:46 PM PST 24
Peak memory 201680 kb
Host smart-12f0c346-88f6-4221-9298-b8050ce3d362
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151871510 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.sram_ctrl_alert_test.1151871510
Directory /workspace/37.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sram_ctrl_bijection.4142788739
Short name T204
Test name
Test status
Simulation time 4743614759 ps
CPU time 72.49 seconds
Started Feb 25 02:48:55 PM PST 24
Finished Feb 25 02:50:07 PM PST 24
Peak memory 202636 kb
Host smart-1aa01964-c999-4802-886d-d83be6a85278
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142788739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_bijection
.4142788739
Directory /workspace/37.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/37.sram_ctrl_executable.3735326556
Short name T780
Test name
Test status
Simulation time 42859433201 ps
CPU time 736.46 seconds
Started Feb 25 02:48:46 PM PST 24
Finished Feb 25 03:01:03 PM PST 24
Peak memory 373436 kb
Host smart-dd4a6f93-41ad-4581-b0c9-93d2533d48e8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735326556 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_executab
le.3735326556
Directory /workspace/37.sram_ctrl_executable/latest

Test location /workspace/coverage/default/37.sram_ctrl_lc_escalation.687186937
Short name T545
Test name
Test status
Simulation time 503013105 ps
CPU time 15.01 seconds
Started Feb 25 02:48:47 PM PST 24
Finished Feb 25 02:49:02 PM PST 24
Peak memory 210856 kb
Host smart-d3ab3b0d-5552-4e35-a101-74da291cd01f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687186937 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_lc_esc
alation.687186937
Directory /workspace/37.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/37.sram_ctrl_max_throughput.586986910
Short name T785
Test name
Test status
Simulation time 266499094 ps
CPU time 161.93 seconds
Started Feb 25 02:48:45 PM PST 24
Finished Feb 25 02:51:27 PM PST 24
Peak memory 373244 kb
Host smart-816bbe97-0166-419d-8d3c-7ba4c6ffe13f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586986910 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.sram_ctrl_max_throughput.586986910
Directory /workspace/37.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_partial_access.96614011
Short name T755
Test name
Test status
Simulation time 157787793 ps
CPU time 5.14 seconds
Started Feb 25 02:48:47 PM PST 24
Finished Feb 25 02:48:52 PM PST 24
Peak memory 210760 kb
Host smart-388676f7-d042-49b0-825b-c56e1bd472e4
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96614011 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
sram_ctrl_mem_partial_access.96614011
Directory /workspace/37.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_mem_walk.3903728088
Short name T488
Test name
Test status
Simulation time 290633739 ps
CPU time 5.65 seconds
Started Feb 25 02:48:50 PM PST 24
Finished Feb 25 02:48:55 PM PST 24
Peak memory 202436 kb
Host smart-b2001675-7a38-4bd1-a94c-ec35d41a46dd
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903728088 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctr
l_mem_walk.3903728088
Directory /workspace/37.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/37.sram_ctrl_multiple_keys.2831356583
Short name T792
Test name
Test status
Simulation time 12850845126 ps
CPU time 955.67 seconds
Started Feb 25 02:48:54 PM PST 24
Finished Feb 25 03:04:50 PM PST 24
Peak memory 375464 kb
Host smart-0e52f7e2-ec87-4651-9f09-33f971360e7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831356583 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_multi
ple_keys.2831356583
Directory /workspace/37.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access.170690690
Short name T503
Test name
Test status
Simulation time 2863889519 ps
CPU time 99.03 seconds
Started Feb 25 02:48:45 PM PST 24
Finished Feb 25 02:50:24 PM PST 24
Peak memory 332632 kb
Host smart-2f7d31db-15c9-44b3-8ad9-61c7c85fbffe
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170690690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.s
ram_ctrl_partial_access.170690690
Directory /workspace/37.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3270750253
Short name T430
Test name
Test status
Simulation time 3510565557 ps
CPU time 260.36 seconds
Started Feb 25 02:48:48 PM PST 24
Finished Feb 25 02:53:08 PM PST 24
Peak memory 202680 kb
Host smart-41b0a352-a569-449b-9df6-bb02cbe8f040
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270750253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 37.sram_ctrl_partial_access_b2b.3270750253
Directory /workspace/37.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/37.sram_ctrl_ram_cfg.3301853136
Short name T193
Test name
Test status
Simulation time 94829069 ps
CPU time 0.81 seconds
Started Feb 25 02:48:45 PM PST 24
Finished Feb 25 02:48:46 PM PST 24
Peak memory 202620 kb
Host smart-6f9fa131-ea09-4a35-a336-a1fa7a0d6dbe
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301853136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_ram_cfg.3301853136
Directory /workspace/37.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/37.sram_ctrl_regwen.110697694
Short name T439
Test name
Test status
Simulation time 9327764985 ps
CPU time 2146.93 seconds
Started Feb 25 02:48:46 PM PST 24
Finished Feb 25 03:24:33 PM PST 24
Peak memory 375464 kb
Host smart-d6913111-febf-433b-b1b4-68b20fd51397
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110697694 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_regwen.110697694
Directory /workspace/37.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/37.sram_ctrl_smoke.1959393434
Short name T139
Test name
Test status
Simulation time 353862342 ps
CPU time 7.59 seconds
Started Feb 25 02:48:45 PM PST 24
Finished Feb 25 02:48:53 PM PST 24
Peak memory 202472 kb
Host smart-cc420c56-2368-43c4-bf36-9930f10d8308
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959393434 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sram_ctrl_smoke.1959393434
Directory /workspace/37.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_all.3095287860
Short name T185
Test name
Test status
Simulation time 15199888388 ps
CPU time 909.25 seconds
Started Feb 25 02:48:46 PM PST 24
Finished Feb 25 03:03:55 PM PST 24
Peak memory 374436 kb
Host smart-7e9865c9-8de3-4aed-a4a7-8595c21f6209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095287860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 37.sram_ctrl_stress_all.3095287860
Directory /workspace/37.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.sram_ctrl_stress_pipeline.946518952
Short name T172
Test name
Test status
Simulation time 2437059296 ps
CPU time 230.14 seconds
Started Feb 25 02:48:47 PM PST 24
Finished Feb 25 02:52:37 PM PST 24
Peak memory 202692 kb
Host smart-fc436cdb-742b-4e3d-8347-7b4cc7585748
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946518952 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.sram_ctrl_stress_pipeline.946518952
Directory /workspace/37.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.410996134
Short name T372
Test name
Test status
Simulation time 105401636 ps
CPU time 32.6 seconds
Started Feb 25 02:48:44 PM PST 24
Finished Feb 25 02:49:17 PM PST 24
Peak memory 287420 kb
Host smart-762ecc9b-a67b-4548-9185-aa4058cc90fc
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410996134 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 37.sram_ctrl_throughput_w_partial_write.410996134
Directory /workspace/37.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/38.sram_ctrl_access_during_key_req.3146119017
Short name T658
Test name
Test status
Simulation time 1636244943 ps
CPU time 372.82 seconds
Started Feb 25 02:48:54 PM PST 24
Finished Feb 25 02:55:07 PM PST 24
Peak memory 364596 kb
Host smart-14f59c76-e627-4fac-a391-524a66d3b0fa
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146119017 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 38.sram_ctrl_access_during_key_req.3146119017
Directory /workspace/38.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/38.sram_ctrl_alert_test.3287561539
Short name T880
Test name
Test status
Simulation time 57296618 ps
CPU time 0.67 seconds
Started Feb 25 02:48:55 PM PST 24
Finished Feb 25 02:48:56 PM PST 24
Peak memory 201492 kb
Host smart-dd849549-ccfe-4b94-a275-511f0d237b9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287561539 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.sram_ctrl_alert_test.3287561539
Directory /workspace/38.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sram_ctrl_bijection.4206836021
Short name T765
Test name
Test status
Simulation time 1346499514 ps
CPU time 54.16 seconds
Started Feb 25 02:48:54 PM PST 24
Finished Feb 25 02:49:48 PM PST 24
Peak memory 202648 kb
Host smart-56bfcb81-a55f-40db-9214-7763114f7fc3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206836021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_bijection
.4206836021
Directory /workspace/38.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/38.sram_ctrl_executable.2627996148
Short name T738
Test name
Test status
Simulation time 31744644461 ps
CPU time 641.8 seconds
Started Feb 25 02:48:56 PM PST 24
Finished Feb 25 02:59:38 PM PST 24
Peak memory 372124 kb
Host smart-107513bd-4549-405c-9373-47c30f10bfc6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627996148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_executab
le.2627996148
Directory /workspace/38.sram_ctrl_executable/latest

Test location /workspace/coverage/default/38.sram_ctrl_lc_escalation.2627141117
Short name T32
Test name
Test status
Simulation time 692259948 ps
CPU time 8.33 seconds
Started Feb 25 02:48:55 PM PST 24
Finished Feb 25 02:49:03 PM PST 24
Peak memory 213236 kb
Host smart-337b770b-1916-429c-8761-24214a6a52be
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627141117 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_lc_es
calation.2627141117
Directory /workspace/38.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/38.sram_ctrl_max_throughput.2126464255
Short name T757
Test name
Test status
Simulation time 178899077 ps
CPU time 5.88 seconds
Started Feb 25 02:49:11 PM PST 24
Finished Feb 25 02:49:18 PM PST 24
Peak memory 226164 kb
Host smart-f7475054-5855-40d2-a9f5-aa9e3ce01a6c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126464255 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 38.sram_ctrl_max_throughput.2126464255
Directory /workspace/38.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_partial_access.758615294
Short name T431
Test name
Test status
Simulation time 381263308 ps
CPU time 2.79 seconds
Started Feb 25 02:48:54 PM PST 24
Finished Feb 25 02:48:57 PM PST 24
Peak memory 210804 kb
Host smart-382c9713-1ffd-40cc-bfe9-5c616978a02b
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758615294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.sram_ctrl_mem_partial_access.758615294
Directory /workspace/38.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_mem_walk.1031954228
Short name T410
Test name
Test status
Simulation time 81144380 ps
CPU time 4.6 seconds
Started Feb 25 02:48:55 PM PST 24
Finished Feb 25 02:48:59 PM PST 24
Peak memory 202580 kb
Host smart-813a02c6-8745-4a15-8567-a707145d2767
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031954228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctr
l_mem_walk.1031954228
Directory /workspace/38.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/38.sram_ctrl_multiple_keys.2654157520
Short name T403
Test name
Test status
Simulation time 1836847100 ps
CPU time 826.31 seconds
Started Feb 25 02:49:11 PM PST 24
Finished Feb 25 03:02:58 PM PST 24
Peak memory 375340 kb
Host smart-1f4d2970-a012-4541-9549-b4d282d6ecc2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654157520 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_multi
ple_keys.2654157520
Directory /workspace/38.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access.881813087
Short name T298
Test name
Test status
Simulation time 107705863 ps
CPU time 24.14 seconds
Started Feb 25 02:48:56 PM PST 24
Finished Feb 25 02:49:20 PM PST 24
Peak memory 259472 kb
Host smart-488f155d-5bf7-4bc3-bc31-bdd3cdc039c5
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881813087 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.s
ram_ctrl_partial_access.881813087
Directory /workspace/38.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.1585092620
Short name T348
Test name
Test status
Simulation time 275906408349 ps
CPU time 381 seconds
Started Feb 25 02:48:54 PM PST 24
Finished Feb 25 02:55:15 PM PST 24
Peak memory 202600 kb
Host smart-d0a360d5-301a-41a1-94f4-a042ce8f45ca
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585092620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 38.sram_ctrl_partial_access_b2b.1585092620
Directory /workspace/38.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/38.sram_ctrl_ram_cfg.3461925044
Short name T173
Test name
Test status
Simulation time 29407431 ps
CPU time 0.81 seconds
Started Feb 25 02:48:54 PM PST 24
Finished Feb 25 02:48:55 PM PST 24
Peak memory 202564 kb
Host smart-de6dc533-51b6-425d-bee8-2d2ac58c7d05
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461925044 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_ram_cfg.3461925044
Directory /workspace/38.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/38.sram_ctrl_regwen.155425860
Short name T28
Test name
Test status
Simulation time 21381706743 ps
CPU time 705.02 seconds
Started Feb 25 02:48:53 PM PST 24
Finished Feb 25 03:00:38 PM PST 24
Peak memory 369308 kb
Host smart-46fbbf5c-8f98-497e-8de2-05190dd4ae54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155425860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_regwen.155425860
Directory /workspace/38.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/38.sram_ctrl_smoke.3222752532
Short name T153
Test name
Test status
Simulation time 834898859 ps
CPU time 13.91 seconds
Started Feb 25 02:48:55 PM PST 24
Finished Feb 25 02:49:09 PM PST 24
Peak memory 202632 kb
Host smart-d4201683-c5a7-48f9-bbfb-58fa433b135a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222752532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sram_ctrl_smoke.3222752532
Directory /workspace/38.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_all.4224348028
Short name T817
Test name
Test status
Simulation time 17665905082 ps
CPU time 839.72 seconds
Started Feb 25 02:49:11 PM PST 24
Finished Feb 25 03:03:12 PM PST 24
Peak memory 360532 kb
Host smart-0cf32ec6-4367-4f7e-82a6-8fd54fa60790
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224348028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 38.sram_ctrl_stress_all.4224348028
Directory /workspace/38.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sram_ctrl_stress_pipeline.2580251357
Short name T253
Test name
Test status
Simulation time 7574632456 ps
CPU time 186.18 seconds
Started Feb 25 02:48:55 PM PST 24
Finished Feb 25 02:52:01 PM PST 24
Peak memory 202676 kb
Host smart-87aadb89-6a3a-489f-b7d9-fe1a6b939e44
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580251357 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.sram_ctrl_stress_pipeline.2580251357
Directory /workspace/38.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.2198091451
Short name T591
Test name
Test status
Simulation time 245745869 ps
CPU time 8.77 seconds
Started Feb 25 02:48:55 PM PST 24
Finished Feb 25 02:49:04 PM PST 24
Peak memory 236360 kb
Host smart-06a3d63e-da6e-4c75-bf46-c4e59278486d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198091451 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sram_ctrl_throughput_w_partial_write.2198091451
Directory /workspace/38.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/39.sram_ctrl_access_during_key_req.964770598
Short name T681
Test name
Test status
Simulation time 6364170848 ps
CPU time 392.45 seconds
Started Feb 25 02:49:06 PM PST 24
Finished Feb 25 02:55:39 PM PST 24
Peak memory 368344 kb
Host smart-810b242d-3dc7-4ffb-ac02-f93a4d414bbb
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964770598 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 39.sram_ctrl_access_during_key_req.964770598
Directory /workspace/39.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/39.sram_ctrl_alert_test.2554761683
Short name T795
Test name
Test status
Simulation time 16151535 ps
CPU time 0.66 seconds
Started Feb 25 02:49:05 PM PST 24
Finished Feb 25 02:49:07 PM PST 24
Peak memory 201696 kb
Host smart-219c5a20-0929-44e6-977a-d41a5b9bbc99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554761683 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.sram_ctrl_alert_test.2554761683
Directory /workspace/39.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sram_ctrl_bijection.3120777727
Short name T794
Test name
Test status
Simulation time 28950174815 ps
CPU time 71.08 seconds
Started Feb 25 02:48:55 PM PST 24
Finished Feb 25 02:50:06 PM PST 24
Peak memory 202672 kb
Host smart-984da9d8-dcf3-4c4e-bd8a-29fd820e1fd9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120777727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_bijection
.3120777727
Directory /workspace/39.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/39.sram_ctrl_executable.1885459837
Short name T837
Test name
Test status
Simulation time 18241164188 ps
CPU time 673.48 seconds
Started Feb 25 02:49:07 PM PST 24
Finished Feb 25 03:00:21 PM PST 24
Peak memory 374264 kb
Host smart-f428537a-5219-439e-9d10-982251fe0c0b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885459837 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_executab
le.1885459837
Directory /workspace/39.sram_ctrl_executable/latest

Test location /workspace/coverage/default/39.sram_ctrl_lc_escalation.2839654833
Short name T199
Test name
Test status
Simulation time 1447276338 ps
CPU time 6.24 seconds
Started Feb 25 02:49:11 PM PST 24
Finished Feb 25 02:49:18 PM PST 24
Peak memory 212984 kb
Host smart-c70ce14e-1cb1-4542-9016-5a591434653c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839654833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_lc_es
calation.2839654833
Directory /workspace/39.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/39.sram_ctrl_max_throughput.3533637099
Short name T383
Test name
Test status
Simulation time 503274890 ps
CPU time 139.66 seconds
Started Feb 25 02:48:53 PM PST 24
Finished Feb 25 02:51:13 PM PST 24
Peak memory 358076 kb
Host smart-fee8d333-4e37-4859-8c7b-008cafb389c2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533637099 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 39.sram_ctrl_max_throughput.3533637099
Directory /workspace/39.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_partial_access.3344012124
Short name T370
Test name
Test status
Simulation time 372526466 ps
CPU time 3.02 seconds
Started Feb 25 02:49:04 PM PST 24
Finished Feb 25 02:49:07 PM PST 24
Peak memory 210832 kb
Host smart-61dfc927-d40c-425b-96cf-b4dd78d32213
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344012124 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_mem_partial_access.3344012124
Directory /workspace/39.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_mem_walk.1233213458
Short name T555
Test name
Test status
Simulation time 3266672893 ps
CPU time 11.44 seconds
Started Feb 25 02:49:04 PM PST 24
Finished Feb 25 02:49:15 PM PST 24
Peak memory 202632 kb
Host smart-5738d151-e76a-4327-8d77-8fac5b0a1dc9
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233213458 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctr
l_mem_walk.1233213458
Directory /workspace/39.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/39.sram_ctrl_multiple_keys.3602130391
Short name T797
Test name
Test status
Simulation time 60366236741 ps
CPU time 953.35 seconds
Started Feb 25 02:49:11 PM PST 24
Finished Feb 25 03:05:05 PM PST 24
Peak memory 367184 kb
Host smart-d1b76269-dd9f-46ef-b8ec-fff8b2e145d3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602130391 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_multi
ple_keys.3602130391
Directory /workspace/39.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access.912562504
Short name T141
Test name
Test status
Simulation time 2475099301 ps
CPU time 4.67 seconds
Started Feb 25 02:48:53 PM PST 24
Finished Feb 25 02:48:58 PM PST 24
Peak memory 217456 kb
Host smart-7070e8f4-0515-4fac-bb41-2577d2b2161e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912562504 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.s
ram_ctrl_partial_access.912562504
Directory /workspace/39.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.937344747
Short name T729
Test name
Test status
Simulation time 14624006448 ps
CPU time 246.79 seconds
Started Feb 25 02:48:55 PM PST 24
Finished Feb 25 02:53:02 PM PST 24
Peak memory 202688 kb
Host smart-98ca254b-eba4-4c8a-b3bc-ac07125f7b7b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937344747 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 39.sram_ctrl_partial_access_b2b.937344747
Directory /workspace/39.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/39.sram_ctrl_ram_cfg.4197275136
Short name T456
Test name
Test status
Simulation time 75224273 ps
CPU time 0.85 seconds
Started Feb 25 02:49:06 PM PST 24
Finished Feb 25 02:49:07 PM PST 24
Peak memory 202576 kb
Host smart-e4fd6b94-4bcb-4f24-85af-03c2457d93c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197275136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_ram_cfg.4197275136
Directory /workspace/39.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/39.sram_ctrl_regwen.1769176055
Short name T825
Test name
Test status
Simulation time 24559481911 ps
CPU time 606.4 seconds
Started Feb 25 02:49:06 PM PST 24
Finished Feb 25 02:59:12 PM PST 24
Peak memory 357592 kb
Host smart-774b0001-691d-454a-8a7b-94b45e6dba54
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769176055 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_regwen.1769176055
Directory /workspace/39.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/39.sram_ctrl_smoke.569411550
Short name T466
Test name
Test status
Simulation time 130288704 ps
CPU time 94.17 seconds
Started Feb 25 02:49:11 PM PST 24
Finished Feb 25 02:50:46 PM PST 24
Peak memory 358672 kb
Host smart-931b2b90-1735-4499-acec-ddb1b37c952d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569411550 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sram_ctrl_smoke.569411550
Directory /workspace/39.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_all.1565752253
Short name T191
Test name
Test status
Simulation time 127009652637 ps
CPU time 3066.65 seconds
Started Feb 25 02:49:05 PM PST 24
Finished Feb 25 03:40:12 PM PST 24
Peak memory 374512 kb
Host smart-e31e901c-2117-4e80-90d4-7bab4668874a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565752253 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 39.sram_ctrl_stress_all.1565752253
Directory /workspace/39.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sram_ctrl_stress_pipeline.4076518621
Short name T695
Test name
Test status
Simulation time 6412509140 ps
CPU time 172.13 seconds
Started Feb 25 02:48:55 PM PST 24
Finished Feb 25 02:51:48 PM PST 24
Peak memory 202680 kb
Host smart-85477430-5621-4a48-a616-b1c77abdda43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076518621 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.sram_ctrl_stress_pipeline.4076518621
Directory /workspace/39.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2676200392
Short name T414
Test name
Test status
Simulation time 910659740 ps
CPU time 137.57 seconds
Started Feb 25 02:49:03 PM PST 24
Finished Feb 25 02:51:21 PM PST 24
Peak memory 364580 kb
Host smart-ecc78df9-a29d-495b-9a19-41af043f5d46
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676200392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sram_ctrl_throughput_w_partial_write.2676200392
Directory /workspace/39.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/4.sram_ctrl_access_during_key_req.1266732136
Short name T564
Test name
Test status
Simulation time 2235619414 ps
CPU time 105.96 seconds
Started Feb 25 02:45:51 PM PST 24
Finished Feb 25 02:47:38 PM PST 24
Peak memory 334360 kb
Host smart-c40d86b4-34ef-46b4-b3d9-94586be8d62b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266732136 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 4.sram_ctrl_access_during_key_req.1266732136
Directory /workspace/4.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/4.sram_ctrl_alert_test.1511869036
Short name T694
Test name
Test status
Simulation time 13158092 ps
CPU time 0.69 seconds
Started Feb 25 02:46:05 PM PST 24
Finished Feb 25 02:46:06 PM PST 24
Peak memory 201560 kb
Host smart-fbb43dba-9716-42e5-b096-d2d72441fbc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511869036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_alert_test.1511869036
Directory /workspace/4.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sram_ctrl_bijection.2185895656
Short name T883
Test name
Test status
Simulation time 18996345357 ps
CPU time 80.92 seconds
Started Feb 25 02:45:53 PM PST 24
Finished Feb 25 02:47:14 PM PST 24
Peak memory 202776 kb
Host smart-ff2351c5-4eb5-48c5-809b-a46ba4364af7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185895656 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_bijection.
2185895656
Directory /workspace/4.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/4.sram_ctrl_executable.4153354817
Short name T653
Test name
Test status
Simulation time 9323510928 ps
CPU time 952.47 seconds
Started Feb 25 02:45:56 PM PST 24
Finished Feb 25 03:01:49 PM PST 24
Peak memory 374316 kb
Host smart-7f6b0186-431d-445c-a839-47a65daec942
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153354817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_executabl
e.4153354817
Directory /workspace/4.sram_ctrl_executable/latest

Test location /workspace/coverage/default/4.sram_ctrl_lc_escalation.267882139
Short name T311
Test name
Test status
Simulation time 656129113 ps
CPU time 3.32 seconds
Started Feb 25 02:45:49 PM PST 24
Finished Feb 25 02:45:54 PM PST 24
Peak memory 210812 kb
Host smart-4d61442c-bb27-46f0-9ddb-00f6230dd5b7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267882139 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_lc_esca
lation.267882139
Directory /workspace/4.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/4.sram_ctrl_max_throughput.3543203783
Short name T323
Test name
Test status
Simulation time 442049946 ps
CPU time 49.39 seconds
Started Feb 25 02:45:51 PM PST 24
Finished Feb 25 02:46:42 PM PST 24
Peak memory 318884 kb
Host smart-85ee157d-a949-4b78-9970-b4ad673686aa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543203783 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_max_throughput.3543203783
Directory /workspace/4.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_partial_access.433197514
Short name T550
Test name
Test status
Simulation time 184081071 ps
CPU time 2.98 seconds
Started Feb 25 02:46:08 PM PST 24
Finished Feb 25 02:46:11 PM PST 24
Peak memory 210780 kb
Host smart-6f7c919f-0d34-457e-9761-aa4013d37b16
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433197514 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
sram_ctrl_mem_partial_access.433197514
Directory /workspace/4.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_mem_walk.258655878
Short name T663
Test name
Test status
Simulation time 567759855 ps
CPU time 8.37 seconds
Started Feb 25 02:46:06 PM PST 24
Finished Feb 25 02:46:14 PM PST 24
Peak memory 202540 kb
Host smart-e4d55c26-68a6-45e1-b20b-055158c49849
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258655878 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_
mem_walk.258655878
Directory /workspace/4.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/4.sram_ctrl_multiple_keys.808170643
Short name T834
Test name
Test status
Simulation time 5401558699 ps
CPU time 676.06 seconds
Started Feb 25 02:45:49 PM PST 24
Finished Feb 25 02:57:07 PM PST 24
Peak memory 375208 kb
Host smart-30d5112b-1466-4eb9-b93e-74ab35f08b76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808170643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_multipl
e_keys.808170643
Directory /workspace/4.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access.103274321
Short name T196
Test name
Test status
Simulation time 4815066340 ps
CPU time 20.19 seconds
Started Feb 25 02:45:48 PM PST 24
Finished Feb 25 02:46:10 PM PST 24
Peak memory 202620 kb
Host smart-845fefea-ea46-4599-a370-589a875d06fa
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103274321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sr
am_ctrl_partial_access.103274321
Directory /workspace/4.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.3523114431
Short name T816
Test name
Test status
Simulation time 21387649430 ps
CPU time 371.1 seconds
Started Feb 25 02:45:50 PM PST 24
Finished Feb 25 02:52:02 PM PST 24
Peak memory 202728 kb
Host smart-3b84602c-35bb-430a-8bf2-74d24baab53b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523114431 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 4.sram_ctrl_partial_access_b2b.3523114431
Directory /workspace/4.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/4.sram_ctrl_ram_cfg.1071067993
Short name T728
Test name
Test status
Simulation time 90987149 ps
CPU time 1.12 seconds
Started Feb 25 02:46:03 PM PST 24
Finished Feb 25 02:46:04 PM PST 24
Peak memory 202832 kb
Host smart-bbc501b6-beb8-4f66-ab42-99653cc76abb
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071067993 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_ram_cfg.1071067993
Directory /workspace/4.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/4.sram_ctrl_regwen.3997277312
Short name T631
Test name
Test status
Simulation time 29790798029 ps
CPU time 1362.46 seconds
Started Feb 25 02:46:03 PM PST 24
Finished Feb 25 03:08:46 PM PST 24
Peak memory 372764 kb
Host smart-e79c0491-aebc-4e67-8cd3-8ef89ca537c3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997277312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_regwen.3997277312
Directory /workspace/4.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/4.sram_ctrl_sec_cm.2941717789
Short name T43
Test name
Test status
Simulation time 227910505 ps
CPU time 3.06 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 02:46:04 PM PST 24
Peak memory 220912 kb
Host smart-af1a0ca2-bcbc-4c3d-9836-a3978a3617a9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941717789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.sram_ctrl_sec_cm.2941717789
Directory /workspace/4.sram_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sram_ctrl_smoke.855723990
Short name T758
Test name
Test status
Simulation time 1473793900 ps
CPU time 17.43 seconds
Started Feb 25 02:45:47 PM PST 24
Finished Feb 25 02:46:06 PM PST 24
Peak memory 202576 kb
Host smart-bc3b29b7-0bd7-4495-b672-6a0e7a194475
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855723990 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sram_ctrl_smoke.855723990
Directory /workspace/4.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_all.3766247142
Short name T684
Test name
Test status
Simulation time 82852724609 ps
CPU time 1223.88 seconds
Started Feb 25 02:46:07 PM PST 24
Finished Feb 25 03:06:31 PM PST 24
Peak memory 369404 kb
Host smart-c8533436-1ac5-4f6c-9ced-edec4d0f7ecd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766247142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 4.sram_ctrl_stress_all.3766247142
Directory /workspace/4.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sram_ctrl_stress_pipeline.2339639896
Short name T782
Test name
Test status
Simulation time 4208630025 ps
CPU time 208.34 seconds
Started Feb 25 02:45:51 PM PST 24
Finished Feb 25 02:49:20 PM PST 24
Peak memory 202636 kb
Host smart-219be70b-d534-4db8-a5a0-8e381b485650
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339639896 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.sram_ctrl_stress_pipeline.2339639896
Directory /workspace/4.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.409843607
Short name T565
Test name
Test status
Simulation time 209696403 ps
CPU time 5.25 seconds
Started Feb 25 02:45:49 PM PST 24
Finished Feb 25 02:45:56 PM PST 24
Peak memory 224660 kb
Host smart-d0c6f042-5848-4981-a540-e9243ebfe05e
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409843607 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 4.sram_ctrl_throughput_w_partial_write.409843607
Directory /workspace/4.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/40.sram_ctrl_access_during_key_req.4033163380
Short name T875
Test name
Test status
Simulation time 6447856652 ps
CPU time 319.44 seconds
Started Feb 25 02:49:06 PM PST 24
Finished Feb 25 02:54:25 PM PST 24
Peak memory 313060 kb
Host smart-705248b4-c4ed-4016-933c-8ee827ecbac6
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033163380 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 40.sram_ctrl_access_during_key_req.4033163380
Directory /workspace/40.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/40.sram_ctrl_alert_test.3315433418
Short name T436
Test name
Test status
Simulation time 11155730 ps
CPU time 0.65 seconds
Started Feb 25 02:49:23 PM PST 24
Finished Feb 25 02:49:24 PM PST 24
Peak memory 201500 kb
Host smart-998636be-74b8-422f-a7a7-ffc6fd855b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315433418 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.sram_ctrl_alert_test.3315433418
Directory /workspace/40.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sram_ctrl_bijection.274860727
Short name T11
Test name
Test status
Simulation time 2763008165 ps
CPU time 21.46 seconds
Started Feb 25 02:49:06 PM PST 24
Finished Feb 25 02:49:28 PM PST 24
Peak memory 202700 kb
Host smart-7cd52789-b462-4d2b-8ab1-1f20848cc320
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274860727 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_bijection.
274860727
Directory /workspace/40.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/40.sram_ctrl_executable.2284378726
Short name T766
Test name
Test status
Simulation time 54272600845 ps
CPU time 1270.55 seconds
Started Feb 25 02:49:05 PM PST 24
Finished Feb 25 03:10:15 PM PST 24
Peak memory 369320 kb
Host smart-e98e32ed-306c-4ae6-83c4-6793ff6835a2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284378726 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_executab
le.2284378726
Directory /workspace/40.sram_ctrl_executable/latest

Test location /workspace/coverage/default/40.sram_ctrl_lc_escalation.3884020536
Short name T621
Test name
Test status
Simulation time 4009007713 ps
CPU time 13.58 seconds
Started Feb 25 02:49:04 PM PST 24
Finished Feb 25 02:49:18 PM PST 24
Peak memory 210860 kb
Host smart-3261c0c8-7417-4da5-ae75-878fbed4643a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884020536 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_lc_es
calation.3884020536
Directory /workspace/40.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/40.sram_ctrl_max_throughput.2484970271
Short name T720
Test name
Test status
Simulation time 104504279 ps
CPU time 57.58 seconds
Started Feb 25 02:49:03 PM PST 24
Finished Feb 25 02:50:01 PM PST 24
Peak memory 309548 kb
Host smart-6ea84cc7-160b-4251-b4a2-278cf4a2e2a4
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484970271 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sram_ctrl_max_throughput.2484970271
Directory /workspace/40.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_partial_access.1751696445
Short name T783
Test name
Test status
Simulation time 333783991 ps
CPU time 4.94 seconds
Started Feb 25 02:49:19 PM PST 24
Finished Feb 25 02:49:24 PM PST 24
Peak memory 211768 kb
Host smart-8aeafbda-388d-4e19-a386-5a5620d58912
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751696445 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_mem_partial_access.1751696445
Directory /workspace/40.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_mem_walk.2447266718
Short name T381
Test name
Test status
Simulation time 335748233 ps
CPU time 5.16 seconds
Started Feb 25 02:49:18 PM PST 24
Finished Feb 25 02:49:23 PM PST 24
Peak memory 202560 kb
Host smart-5f41d49c-ff32-4dd2-b2c3-904b354db915
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447266718 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctr
l_mem_walk.2447266718
Directory /workspace/40.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/40.sram_ctrl_multiple_keys.3735399363
Short name T826
Test name
Test status
Simulation time 919680905 ps
CPU time 23.44 seconds
Started Feb 25 02:49:05 PM PST 24
Finished Feb 25 02:49:29 PM PST 24
Peak memory 242808 kb
Host smart-d1c157cf-caf3-4f4b-811d-ae9d2ac488e0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735399363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_multi
ple_keys.3735399363
Directory /workspace/40.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access.439099915
Short name T123
Test name
Test status
Simulation time 807359561 ps
CPU time 150.27 seconds
Started Feb 25 02:49:07 PM PST 24
Finished Feb 25 02:51:37 PM PST 24
Peak memory 373204 kb
Host smart-d4e644e0-2faa-4c77-ae03-88cd478d097b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439099915 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.s
ram_ctrl_partial_access.439099915
Directory /workspace/40.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1964142476
Short name T523
Test name
Test status
Simulation time 25891158463 ps
CPU time 328.66 seconds
Started Feb 25 02:49:04 PM PST 24
Finished Feb 25 02:54:33 PM PST 24
Peak memory 202656 kb
Host smart-52edf5e5-14fa-4309-82f0-e48519528b23
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964142476 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_partial_access_b2b.1964142476
Directory /workspace/40.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/40.sram_ctrl_ram_cfg.1077078205
Short name T158
Test name
Test status
Simulation time 82134282 ps
CPU time 1.11 seconds
Started Feb 25 02:49:05 PM PST 24
Finished Feb 25 02:49:07 PM PST 24
Peak memory 202860 kb
Host smart-d3cd9d6f-a60f-492e-ad04-76dfd9862ca6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077078205 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_ram_cfg.1077078205
Directory /workspace/40.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/40.sram_ctrl_regwen.3219989107
Short name T754
Test name
Test status
Simulation time 6331059885 ps
CPU time 166.26 seconds
Started Feb 25 02:49:05 PM PST 24
Finished Feb 25 02:51:52 PM PST 24
Peak memory 328688 kb
Host smart-d0bec22c-0733-4b32-a0c2-73aa85c8fa4a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219989107 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_regwen.3219989107
Directory /workspace/40.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/40.sram_ctrl_smoke.2302671186
Short name T392
Test name
Test status
Simulation time 548142281 ps
CPU time 41.83 seconds
Started Feb 25 02:49:04 PM PST 24
Finished Feb 25 02:49:46 PM PST 24
Peak memory 298096 kb
Host smart-f5f2c6a6-bf00-46fd-9306-a5f4d6b3e3c0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302671186 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sram_ctrl_smoke.2302671186
Directory /workspace/40.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_all.244747571
Short name T734
Test name
Test status
Simulation time 59529091307 ps
CPU time 5561.21 seconds
Started Feb 25 02:49:21 PM PST 24
Finished Feb 25 04:22:03 PM PST 24
Peak memory 375492 kb
Host smart-362c40a8-db33-40a2-868e-0972107537ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244747571 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 40.sram_ctrl_stress_all.244747571
Directory /workspace/40.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sram_ctrl_stress_pipeline.2487555267
Short name T240
Test name
Test status
Simulation time 3060205739 ps
CPU time 281.2 seconds
Started Feb 25 02:49:04 PM PST 24
Finished Feb 25 02:53:45 PM PST 24
Peak memory 202688 kb
Host smart-54be53df-4138-42d9-8a96-e84d0e634b6e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487555267 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.sram_ctrl_stress_pipeline.2487555267
Directory /workspace/40.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1021770424
Short name T351
Test name
Test status
Simulation time 507920095 ps
CPU time 73.7 seconds
Started Feb 25 02:49:14 PM PST 24
Finished Feb 25 02:50:28 PM PST 24
Peak memory 326292 kb
Host smart-f3e95c2c-a3d0-4976-b8c2-163b3480eaf5
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021770424 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 40.sram_ctrl_throughput_w_partial_write.1021770424
Directory /workspace/40.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/41.sram_ctrl_access_during_key_req.2920193922
Short name T387
Test name
Test status
Simulation time 2647349698 ps
CPU time 738.43 seconds
Started Feb 25 02:49:14 PM PST 24
Finished Feb 25 03:01:32 PM PST 24
Peak memory 366316 kb
Host smart-747af50e-cf7f-488a-a524-40d246dd54d0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920193922 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 41.sram_ctrl_access_during_key_req.2920193922
Directory /workspace/41.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/41.sram_ctrl_alert_test.3525127372
Short name T596
Test name
Test status
Simulation time 20981387 ps
CPU time 0.65 seconds
Started Feb 25 02:49:21 PM PST 24
Finished Feb 25 02:49:22 PM PST 24
Peak memory 202432 kb
Host smart-cc504260-343c-42c4-9454-01821d96abfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525127372 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.sram_ctrl_alert_test.3525127372
Directory /workspace/41.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sram_ctrl_bijection.2631184953
Short name T812
Test name
Test status
Simulation time 745327225 ps
CPU time 46.55 seconds
Started Feb 25 02:49:13 PM PST 24
Finished Feb 25 02:50:00 PM PST 24
Peak memory 202628 kb
Host smart-bce71c76-0e62-449c-a982-3b6bc8f14266
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631184953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_bijection
.2631184953
Directory /workspace/41.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/41.sram_ctrl_executable.2849240142
Short name T148
Test name
Test status
Simulation time 723252144 ps
CPU time 234.59 seconds
Started Feb 25 02:49:21 PM PST 24
Finished Feb 25 02:53:16 PM PST 24
Peak memory 372172 kb
Host smart-2031a44b-f366-4c90-be2e-3e35822f65ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849240142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_executab
le.2849240142
Directory /workspace/41.sram_ctrl_executable/latest

Test location /workspace/coverage/default/41.sram_ctrl_lc_escalation.2119399676
Short name T297
Test name
Test status
Simulation time 920222166 ps
CPU time 7.12 seconds
Started Feb 25 02:49:12 PM PST 24
Finished Feb 25 02:49:19 PM PST 24
Peak memory 210820 kb
Host smart-07d78df6-49b1-4600-8a4e-795e2c413ee5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119399676 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_lc_es
calation.2119399676
Directory /workspace/41.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/41.sram_ctrl_max_throughput.3151720625
Short name T265
Test name
Test status
Simulation time 404386165 ps
CPU time 55.6 seconds
Started Feb 25 02:49:22 PM PST 24
Finished Feb 25 02:50:17 PM PST 24
Peak memory 312088 kb
Host smart-b928fbdb-0aef-432d-8fb9-750c0dcf83ee
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151720625 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sram_ctrl_max_throughput.3151720625
Directory /workspace/41.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1983230599
Short name T459
Test name
Test status
Simulation time 587067942 ps
CPU time 5.5 seconds
Started Feb 25 02:49:23 PM PST 24
Finished Feb 25 02:49:29 PM PST 24
Peak memory 210776 kb
Host smart-2989baa7-3285-46f0-a513-e3e48446cb77
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983230599 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_mem_partial_access.1983230599
Directory /workspace/41.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_mem_walk.3354546839
Short name T746
Test name
Test status
Simulation time 75548044 ps
CPU time 4.52 seconds
Started Feb 25 02:49:20 PM PST 24
Finished Feb 25 02:49:25 PM PST 24
Peak memory 202564 kb
Host smart-decd2fe2-636f-4756-95d8-37cfe7ff3b4e
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354546839 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctr
l_mem_walk.3354546839
Directory /workspace/41.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/41.sram_ctrl_multiple_keys.412060392
Short name T284
Test name
Test status
Simulation time 14607882279 ps
CPU time 1327.77 seconds
Started Feb 25 02:49:23 PM PST 24
Finished Feb 25 03:11:31 PM PST 24
Peak memory 372380 kb
Host smart-8f580c17-1329-4161-98d8-28f3c5f3bba6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412060392 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_multip
le_keys.412060392
Directory /workspace/41.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access.3048271339
Short name T637
Test name
Test status
Simulation time 2617466510 ps
CPU time 125.26 seconds
Started Feb 25 02:49:23 PM PST 24
Finished Feb 25 02:51:29 PM PST 24
Peak memory 361224 kb
Host smart-04516d93-8fe8-4d10-a34d-d5f84ddbdbd3
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048271339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
sram_ctrl_partial_access.3048271339
Directory /workspace/41.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.719401102
Short name T810
Test name
Test status
Simulation time 5375622553 ps
CPU time 367.54 seconds
Started Feb 25 02:49:19 PM PST 24
Finished Feb 25 02:55:27 PM PST 24
Peak memory 202728 kb
Host smart-643329af-18a2-42ef-b65e-04983fcd5793
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719401102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 41.sram_ctrl_partial_access_b2b.719401102
Directory /workspace/41.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/41.sram_ctrl_ram_cfg.1199182692
Short name T449
Test name
Test status
Simulation time 46647237 ps
CPU time 1.07 seconds
Started Feb 25 02:49:13 PM PST 24
Finished Feb 25 02:49:14 PM PST 24
Peak memory 202836 kb
Host smart-1b099188-77bb-4fc0-a7d4-4e07574a6aa6
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199182692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_ram_cfg.1199182692
Directory /workspace/41.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/41.sram_ctrl_regwen.948974103
Short name T585
Test name
Test status
Simulation time 13570783205 ps
CPU time 518.49 seconds
Started Feb 25 02:49:25 PM PST 24
Finished Feb 25 02:58:03 PM PST 24
Peak memory 369852 kb
Host smart-9b1988e1-8d8d-4809-98e9-206df1dd2c76
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948974103 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_regwen.948974103
Directory /workspace/41.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/41.sram_ctrl_smoke.2968443166
Short name T863
Test name
Test status
Simulation time 1374387649 ps
CPU time 138.83 seconds
Started Feb 25 02:49:21 PM PST 24
Finished Feb 25 02:51:40 PM PST 24
Peak memory 363588 kb
Host smart-b55fed36-8cdf-48d1-8cb4-4528305848ea
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968443166 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sram_ctrl_smoke.2968443166
Directory /workspace/41.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_all.2286466777
Short name T656
Test name
Test status
Simulation time 38677432463 ps
CPU time 3783.23 seconds
Started Feb 25 02:49:21 PM PST 24
Finished Feb 25 03:52:25 PM PST 24
Peak memory 374432 kb
Host smart-4551a5f9-0ef8-422f-b267-545c613a0eb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286466777 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 41.sram_ctrl_stress_all.2286466777
Directory /workspace/41.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3028090449
Short name T517
Test name
Test status
Simulation time 3793412518 ps
CPU time 190.08 seconds
Started Feb 25 02:49:22 PM PST 24
Finished Feb 25 02:52:32 PM PST 24
Peak memory 202696 kb
Host smart-cfba8a02-c99d-41b1-9886-da6c65c3844b
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028090449 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.sram_ctrl_stress_pipeline.3028090449
Directory /workspace/41.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2076246962
Short name T884
Test name
Test status
Simulation time 242514718 ps
CPU time 7.53 seconds
Started Feb 25 02:49:22 PM PST 24
Finished Feb 25 02:49:30 PM PST 24
Peak memory 235364 kb
Host smart-2257d801-0f80-47e5-b0e1-e4a58bfe5355
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076246962 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sram_ctrl_throughput_w_partial_write.2076246962
Directory /workspace/41.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/42.sram_ctrl_access_during_key_req.3908809461
Short name T891
Test name
Test status
Simulation time 1952584995 ps
CPU time 403.76 seconds
Started Feb 25 02:49:30 PM PST 24
Finished Feb 25 02:56:14 PM PST 24
Peak memory 372248 kb
Host smart-c942c731-bf1f-4ca4-8b60-61e5b392fcaf
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908809461 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 42.sram_ctrl_access_during_key_req.3908809461
Directory /workspace/42.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/42.sram_ctrl_alert_test.3735571589
Short name T546
Test name
Test status
Simulation time 21790696 ps
CPU time 0.65 seconds
Started Feb 25 02:49:28 PM PST 24
Finished Feb 25 02:49:29 PM PST 24
Peak memory 202452 kb
Host smart-2d24a98f-cb0c-4575-9df7-d6a3cee60e1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735571589 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.sram_ctrl_alert_test.3735571589
Directory /workspace/42.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sram_ctrl_bijection.4191871632
Short name T365
Test name
Test status
Simulation time 1223365196 ps
CPU time 48.31 seconds
Started Feb 25 02:49:22 PM PST 24
Finished Feb 25 02:50:11 PM PST 24
Peak memory 202616 kb
Host smart-672e0398-b82d-4349-a783-f2829ea88d2e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191871632 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_bijection
.4191871632
Directory /workspace/42.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/42.sram_ctrl_executable.2935223784
Short name T808
Test name
Test status
Simulation time 16776274132 ps
CPU time 1292.05 seconds
Started Feb 25 02:49:25 PM PST 24
Finished Feb 25 03:10:58 PM PST 24
Peak memory 371352 kb
Host smart-3a26e305-8307-4dc4-8d13-9976c3bf04b0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935223784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_executab
le.2935223784
Directory /workspace/42.sram_ctrl_executable/latest

Test location /workspace/coverage/default/42.sram_ctrl_lc_escalation.1587647815
Short name T882
Test name
Test status
Simulation time 298942928 ps
CPU time 2.47 seconds
Started Feb 25 02:49:30 PM PST 24
Finished Feb 25 02:49:32 PM PST 24
Peak memory 202716 kb
Host smart-986f5ea4-a3f9-4364-a66a-33bfd4ee8922
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587647815 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_lc_es
calation.1587647815
Directory /workspace/42.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/42.sram_ctrl_max_throughput.3181396848
Short name T121
Test name
Test status
Simulation time 180129220 ps
CPU time 24.91 seconds
Started Feb 25 02:49:28 PM PST 24
Finished Feb 25 02:49:53 PM PST 24
Peak memory 268080 kb
Host smart-866d8b4a-1291-4fe2-955b-c33cf641cefe
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181396848 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_max_throughput.3181396848
Directory /workspace/42.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_partial_access.3440132001
Short name T532
Test name
Test status
Simulation time 90239755 ps
CPU time 2.82 seconds
Started Feb 25 02:49:29 PM PST 24
Finished Feb 25 02:49:32 PM PST 24
Peak memory 210764 kb
Host smart-65fe4d16-c614-4f24-aa02-64bd1c820655
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440132001 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_mem_partial_access.3440132001
Directory /workspace/42.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_mem_walk.318599664
Short name T870
Test name
Test status
Simulation time 87780412 ps
CPU time 4.33 seconds
Started Feb 25 02:49:29 PM PST 24
Finished Feb 25 02:49:34 PM PST 24
Peak memory 202568 kb
Host smart-947b9359-b33a-4c3c-bbd1-aca9db323af6
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318599664 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl
_mem_walk.318599664
Directory /workspace/42.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/42.sram_ctrl_multiple_keys.3051989405
Short name T747
Test name
Test status
Simulation time 25071373747 ps
CPU time 842.52 seconds
Started Feb 25 02:49:24 PM PST 24
Finished Feb 25 03:03:27 PM PST 24
Peak memory 370304 kb
Host smart-2728a26d-744f-468a-9140-8e0acba06221
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051989405 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_multi
ple_keys.3051989405
Directory /workspace/42.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access.915015177
Short name T179
Test name
Test status
Simulation time 275783966 ps
CPU time 4.04 seconds
Started Feb 25 02:49:24 PM PST 24
Finished Feb 25 02:49:28 PM PST 24
Peak memory 214328 kb
Host smart-368d9fe5-1301-4796-b1d0-930f6fee8058
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915015177 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.s
ram_ctrl_partial_access.915015177
Directory /workspace/42.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1397513622
Short name T100
Test name
Test status
Simulation time 11166324086 ps
CPU time 213.93 seconds
Started Feb 25 02:49:34 PM PST 24
Finished Feb 25 02:53:09 PM PST 24
Peak memory 202664 kb
Host smart-ab94d03c-8a9e-4dea-ae2c-8fe2de8f735e
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397513622 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_partial_access_b2b.1397513622
Directory /workspace/42.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/42.sram_ctrl_ram_cfg.3187443526
Short name T554
Test name
Test status
Simulation time 159412270 ps
CPU time 1.09 seconds
Started Feb 25 02:49:30 PM PST 24
Finished Feb 25 02:49:32 PM PST 24
Peak memory 202732 kb
Host smart-ac08f461-3642-49de-b201-01d3f16e9a78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187443526 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_ram_cfg.3187443526
Directory /workspace/42.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/42.sram_ctrl_regwen.2794970953
Short name T551
Test name
Test status
Simulation time 19510778110 ps
CPU time 735.68 seconds
Started Feb 25 02:49:31 PM PST 24
Finished Feb 25 03:01:48 PM PST 24
Peak memory 368976 kb
Host smart-dd8412b6-7941-42be-9164-d255de684a1c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794970953 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_regwen.2794970953
Directory /workspace/42.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/42.sram_ctrl_smoke.297424703
Short name T15
Test name
Test status
Simulation time 706571372 ps
CPU time 11.74 seconds
Started Feb 25 02:49:23 PM PST 24
Finished Feb 25 02:49:35 PM PST 24
Peak memory 202628 kb
Host smart-30a1f06a-16ca-4c46-a51e-9fcfda2d722f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297424703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sram_ctrl_smoke.297424703
Directory /workspace/42.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_all.216870901
Short name T354
Test name
Test status
Simulation time 44053182703 ps
CPU time 2545.7 seconds
Started Feb 25 02:49:34 PM PST 24
Finished Feb 25 03:32:00 PM PST 24
Peak memory 383320 kb
Host smart-5b124687-3e77-42e3-9d4d-58d51908fbfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216870901 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 42.sram_ctrl_stress_all.216870901
Directory /workspace/42.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sram_ctrl_stress_pipeline.4283206559
Short name T762
Test name
Test status
Simulation time 6535030070 ps
CPU time 152.92 seconds
Started Feb 25 02:49:24 PM PST 24
Finished Feb 25 02:51:57 PM PST 24
Peak memory 202644 kb
Host smart-736ca0e8-d30d-4d33-b090-82a33401191d
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283206559 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.sram_ctrl_stress_pipeline.4283206559
Directory /workspace/42.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.829511633
Short name T650
Test name
Test status
Simulation time 87140038 ps
CPU time 20.24 seconds
Started Feb 25 02:49:32 PM PST 24
Finished Feb 25 02:49:53 PM PST 24
Peak memory 273440 kb
Host smart-8157d334-fd4c-49e4-b96c-673d1d793f3f
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829511633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 42.sram_ctrl_throughput_w_partial_write.829511633
Directory /workspace/42.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/43.sram_ctrl_access_during_key_req.3552132506
Short name T806
Test name
Test status
Simulation time 3243251005 ps
CPU time 785.13 seconds
Started Feb 25 02:49:34 PM PST 24
Finished Feb 25 03:02:39 PM PST 24
Peak memory 372332 kb
Host smart-4f68703d-9e45-401a-83f1-fb1cf3539a5f
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552132506 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 43.sram_ctrl_access_during_key_req.3552132506
Directory /workspace/43.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/43.sram_ctrl_alert_test.2667574005
Short name T138
Test name
Test status
Simulation time 69552194 ps
CPU time 0.66 seconds
Started Feb 25 02:49:42 PM PST 24
Finished Feb 25 02:49:43 PM PST 24
Peak memory 201684 kb
Host smart-bf948d17-cbba-45d0-9b10-b88d0c7197b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667574005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.sram_ctrl_alert_test.2667574005
Directory /workspace/43.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sram_ctrl_bijection.1900256529
Short name T600
Test name
Test status
Simulation time 3693073554 ps
CPU time 63.24 seconds
Started Feb 25 02:49:30 PM PST 24
Finished Feb 25 02:50:33 PM PST 24
Peak memory 202620 kb
Host smart-c633c977-32f5-4f10-92fe-9dec6f9d59ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900256529 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_bijection
.1900256529
Directory /workspace/43.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/43.sram_ctrl_executable.348036530
Short name T492
Test name
Test status
Simulation time 27985684862 ps
CPU time 733.11 seconds
Started Feb 25 02:49:41 PM PST 24
Finished Feb 25 03:01:55 PM PST 24
Peak memory 374496 kb
Host smart-42a90520-eb55-4740-acdf-d0dba4974b78
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348036530 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_executabl
e.348036530
Directory /workspace/43.sram_ctrl_executable/latest

Test location /workspace/coverage/default/43.sram_ctrl_lc_escalation.3310914681
Short name T221
Test name
Test status
Simulation time 185280064 ps
CPU time 3.12 seconds
Started Feb 25 02:49:32 PM PST 24
Finished Feb 25 02:49:36 PM PST 24
Peak memory 210780 kb
Host smart-e5ac64c2-edff-476d-b4e2-42e77ddf6ac7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310914681 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_lc_es
calation.3310914681
Directory /workspace/43.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/43.sram_ctrl_max_throughput.3409090961
Short name T412
Test name
Test status
Simulation time 69565415 ps
CPU time 16.02 seconds
Started Feb 25 02:49:30 PM PST 24
Finished Feb 25 02:49:46 PM PST 24
Peak memory 260464 kb
Host smart-787493e1-acbd-407c-8cec-2b70f26b57ab
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409090961 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 43.sram_ctrl_max_throughput.3409090961
Directory /workspace/43.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_partial_access.3460451784
Short name T744
Test name
Test status
Simulation time 162452751 ps
CPU time 3.03 seconds
Started Feb 25 02:49:37 PM PST 24
Finished Feb 25 02:49:41 PM PST 24
Peak memory 215372 kb
Host smart-39c3ca22-7fde-4bbb-aa30-a0a728ce3001
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460451784 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_mem_partial_access.3460451784
Directory /workspace/43.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_mem_walk.413778545
Short name T45
Test name
Test status
Simulation time 77320232 ps
CPU time 4.47 seconds
Started Feb 25 02:49:38 PM PST 24
Finished Feb 25 02:49:44 PM PST 24
Peak memory 202528 kb
Host smart-04d3be9b-dc3d-4657-acd5-9214a059f68b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413778545 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl
_mem_walk.413778545
Directory /workspace/43.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/43.sram_ctrl_multiple_keys.57686955
Short name T676
Test name
Test status
Simulation time 2438037126 ps
CPU time 47.5 seconds
Started Feb 25 02:49:20 PM PST 24
Finished Feb 25 02:50:07 PM PST 24
Peak memory 263228 kb
Host smart-57c83d49-4527-410e-8d31-42c27f64278e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57686955 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multip
le_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_multipl
e_keys.57686955
Directory /workspace/43.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access.2829584888
Short name T477
Test name
Test status
Simulation time 104203587 ps
CPU time 6.11 seconds
Started Feb 25 02:49:29 PM PST 24
Finished Feb 25 02:49:35 PM PST 24
Peak memory 224932 kb
Host smart-6c5af072-6c54-42a4-abd7-93420e64bf91
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829584888 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
sram_ctrl_partial_access.2829584888
Directory /workspace/43.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1241847944
Short name T328
Test name
Test status
Simulation time 9781292912 ps
CPU time 218.25 seconds
Started Feb 25 02:49:33 PM PST 24
Finished Feb 25 02:53:12 PM PST 24
Peak memory 202672 kb
Host smart-307aaab6-29ad-4527-bcae-408fb864ca87
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241847944 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 43.sram_ctrl_partial_access_b2b.1241847944
Directory /workspace/43.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/43.sram_ctrl_ram_cfg.4068887660
Short name T562
Test name
Test status
Simulation time 75391605 ps
CPU time 1.13 seconds
Started Feb 25 02:49:36 PM PST 24
Finished Feb 25 02:49:38 PM PST 24
Peak memory 202828 kb
Host smart-2aa0f46a-ffcb-433e-8985-767f86235563
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068887660 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_ram_cfg.4068887660
Directory /workspace/43.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/43.sram_ctrl_regwen.3342401591
Short name T329
Test name
Test status
Simulation time 96001770633 ps
CPU time 3190.12 seconds
Started Feb 25 02:49:36 PM PST 24
Finished Feb 25 03:42:47 PM PST 24
Peak memory 374320 kb
Host smart-6eaf3674-1d11-456c-959f-d7f3f38ec40e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342401591 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_regwen.3342401591
Directory /workspace/43.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/43.sram_ctrl_smoke.2433129936
Short name T350
Test name
Test status
Simulation time 536238399 ps
CPU time 154.22 seconds
Started Feb 25 02:49:34 PM PST 24
Finished Feb 25 02:52:08 PM PST 24
Peak memory 365604 kb
Host smart-e3a3e407-c1e6-4624-84fd-941fbd2b74e7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433129936 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sram_ctrl_smoke.2433129936
Directory /workspace/43.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_all.3328446833
Short name T159
Test name
Test status
Simulation time 29674771411 ps
CPU time 768.29 seconds
Started Feb 25 02:49:42 PM PST 24
Finished Feb 25 03:02:31 PM PST 24
Peak memory 375480 kb
Host smart-6e4de918-3e48-4ca9-ae0f-14b4b69b365b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328446833 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 43.sram_ctrl_stress_all.3328446833
Directory /workspace/43.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1614693148
Short name T16
Test name
Test status
Simulation time 5101381220 ps
CPU time 242.89 seconds
Started Feb 25 02:49:33 PM PST 24
Finished Feb 25 02:53:36 PM PST 24
Peak memory 202672 kb
Host smart-c0cab7c8-3bcb-4285-853f-e0f04855ff97
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614693148 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.sram_ctrl_stress_pipeline.1614693148
Directory /workspace/43.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2444435563
Short name T509
Test name
Test status
Simulation time 160392570 ps
CPU time 21.09 seconds
Started Feb 25 02:49:30 PM PST 24
Finished Feb 25 02:49:52 PM PST 24
Peak memory 267988 kb
Host smart-3e8f1626-efbc-4bef-83e0-98975723f939
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444435563 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sram_ctrl_throughput_w_partial_write.2444435563
Directory /workspace/43.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/44.sram_ctrl_access_during_key_req.917281193
Short name T355
Test name
Test status
Simulation time 1963202206 ps
CPU time 448.59 seconds
Started Feb 25 02:49:41 PM PST 24
Finished Feb 25 02:57:11 PM PST 24
Peak memory 373344 kb
Host smart-aa0ba2fc-27b2-49de-a7d7-491a5ff7034e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917281193 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 44.sram_ctrl_access_during_key_req.917281193
Directory /workspace/44.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/44.sram_ctrl_alert_test.2862115341
Short name T322
Test name
Test status
Simulation time 19947433 ps
CPU time 0.64 seconds
Started Feb 25 02:49:42 PM PST 24
Finished Feb 25 02:49:44 PM PST 24
Peak memory 202436 kb
Host smart-1ae3ff9d-a28c-4183-8c97-157f0a4e58ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862115341 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.sram_ctrl_alert_test.2862115341
Directory /workspace/44.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sram_ctrl_bijection.1696561036
Short name T244
Test name
Test status
Simulation time 1824881894 ps
CPU time 19.21 seconds
Started Feb 25 02:49:38 PM PST 24
Finished Feb 25 02:49:58 PM PST 24
Peak memory 202564 kb
Host smart-6cdc0302-0dd0-4175-bb5f-f30b821e78e5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696561036 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_bijection
.1696561036
Directory /workspace/44.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/44.sram_ctrl_executable.2324701102
Short name T581
Test name
Test status
Simulation time 13099016668 ps
CPU time 1023.87 seconds
Started Feb 25 02:49:41 PM PST 24
Finished Feb 25 03:06:47 PM PST 24
Peak memory 370344 kb
Host smart-c4d284e6-6ee0-4d31-8a31-ace1a87f828b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324701102 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_executab
le.2324701102
Directory /workspace/44.sram_ctrl_executable/latest

Test location /workspace/coverage/default/44.sram_ctrl_lc_escalation.1912248272
Short name T586
Test name
Test status
Simulation time 3280098587 ps
CPU time 10.88 seconds
Started Feb 25 02:49:38 PM PST 24
Finished Feb 25 02:49:50 PM PST 24
Peak memory 202632 kb
Host smart-bd133ec8-d006-4d32-96a4-4982be821462
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912248272 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_lc_es
calation.1912248272
Directory /workspace/44.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/44.sram_ctrl_max_throughput.4217179532
Short name T893
Test name
Test status
Simulation time 71773859 ps
CPU time 2.41 seconds
Started Feb 25 02:49:43 PM PST 24
Finished Feb 25 02:49:46 PM PST 24
Peak memory 210848 kb
Host smart-b517d974-8b6e-4ccd-b1d8-c3b0694f7028
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217179532 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sram_ctrl_max_throughput.4217179532
Directory /workspace/44.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_partial_access.1730949649
Short name T73
Test name
Test status
Simulation time 43724095 ps
CPU time 3.05 seconds
Started Feb 25 02:49:43 PM PST 24
Finished Feb 25 02:49:46 PM PST 24
Peak memory 210832 kb
Host smart-a78575fb-5970-4dc8-8fbd-e7bb22d961b3
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730949649 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_mem_partial_access.1730949649
Directory /workspace/44.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_mem_walk.2414401308
Short name T467
Test name
Test status
Simulation time 1576065598 ps
CPU time 5.77 seconds
Started Feb 25 02:49:40 PM PST 24
Finished Feb 25 02:49:48 PM PST 24
Peak memory 202572 kb
Host smart-5567dfc0-3d28-443c-9eb3-9ea0a5e37295
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414401308 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctr
l_mem_walk.2414401308
Directory /workspace/44.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/44.sram_ctrl_multiple_keys.2003006502
Short name T377
Test name
Test status
Simulation time 62766171489 ps
CPU time 446.9 seconds
Started Feb 25 02:49:35 PM PST 24
Finished Feb 25 02:57:03 PM PST 24
Peak memory 370380 kb
Host smart-b1e8a680-9950-4a72-b46d-f8848db81baf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003006502 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_multi
ple_keys.2003006502
Directory /workspace/44.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access.1133436028
Short name T330
Test name
Test status
Simulation time 845206261 ps
CPU time 11.17 seconds
Started Feb 25 02:49:41 PM PST 24
Finished Feb 25 02:49:53 PM PST 24
Peak memory 202628 kb
Host smart-20539362-b0cf-4265-8f79-2b07faca0f2a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133436028 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
sram_ctrl_partial_access.1133436028
Directory /workspace/44.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3361671828
Short name T895
Test name
Test status
Simulation time 11127833580 ps
CPU time 271.77 seconds
Started Feb 25 02:49:42 PM PST 24
Finished Feb 25 02:54:15 PM PST 24
Peak memory 202648 kb
Host smart-a1f9aa47-5fe4-49e0-b801-34eab491d619
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361671828 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 44.sram_ctrl_partial_access_b2b.3361671828
Directory /workspace/44.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/44.sram_ctrl_ram_cfg.802081861
Short name T606
Test name
Test status
Simulation time 34656905 ps
CPU time 1.11 seconds
Started Feb 25 02:49:41 PM PST 24
Finished Feb 25 02:49:43 PM PST 24
Peak memory 202820 kb
Host smart-771825bf-cd8f-405c-9732-44565043df04
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802081861 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_c
fg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_ram_cfg.802081861
Directory /workspace/44.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/44.sram_ctrl_regwen.3616169643
Short name T854
Test name
Test status
Simulation time 787296847 ps
CPU time 229.33 seconds
Started Feb 25 02:49:38 PM PST 24
Finished Feb 25 02:53:29 PM PST 24
Peak memory 367828 kb
Host smart-3d5cccdb-6209-4b31-9adf-6a1df4947408
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616169643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_regwen.3616169643
Directory /workspace/44.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/44.sram_ctrl_smoke.4211689002
Short name T636
Test name
Test status
Simulation time 83034721 ps
CPU time 5.48 seconds
Started Feb 25 02:49:38 PM PST 24
Finished Feb 25 02:49:45 PM PST 24
Peak memory 226176 kb
Host smart-b6287dab-7ae0-473b-a5af-0a128540d02c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211689002 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sram_ctrl_smoke.4211689002
Directory /workspace/44.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_all.1897756946
Short name T491
Test name
Test status
Simulation time 233395737985 ps
CPU time 4009.35 seconds
Started Feb 25 02:49:38 PM PST 24
Finished Feb 25 03:56:29 PM PST 24
Peak memory 383060 kb
Host smart-539623a1-4a3d-424c-872d-5c5ca0a4a0df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897756946 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 44.sram_ctrl_stress_all.1897756946
Directory /workspace/44.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1716131626
Short name T425
Test name
Test status
Simulation time 29429538319 ps
CPU time 169.85 seconds
Started Feb 25 02:49:38 PM PST 24
Finished Feb 25 02:52:29 PM PST 24
Peak memory 202692 kb
Host smart-50347899-c26d-46c5-9fd6-7a095a3a3a43
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716131626 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.sram_ctrl_stress_pipeline.1716131626
Directory /workspace/44.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2396597788
Short name T855
Test name
Test status
Simulation time 732881375 ps
CPU time 15.93 seconds
Started Feb 25 02:49:36 PM PST 24
Finished Feb 25 02:49:53 PM PST 24
Peak memory 251652 kb
Host smart-e0d62edf-3fbe-43b6-84fa-a537b43cbd7a
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396597788 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 44.sram_ctrl_throughput_w_partial_write.2396597788
Directory /workspace/44.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/45.sram_ctrl_access_during_key_req.226396246
Short name T873
Test name
Test status
Simulation time 3990866866 ps
CPU time 1029.67 seconds
Started Feb 25 02:49:50 PM PST 24
Finished Feb 25 03:07:00 PM PST 24
Peak memory 372420 kb
Host smart-3f9c7c8c-da68-4eb2-875c-f5b7ef1820dc
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226396246 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n
ame 45.sram_ctrl_access_during_key_req.226396246
Directory /workspace/45.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/45.sram_ctrl_alert_test.2431927923
Short name T538
Test name
Test status
Simulation time 14872635 ps
CPU time 0.73 seconds
Started Feb 25 02:50:03 PM PST 24
Finished Feb 25 02:50:04 PM PST 24
Peak memory 202452 kb
Host smart-b1faba78-c4a5-4c3f-a16d-95561e86753b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431927923 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.sram_ctrl_alert_test.2431927923
Directory /workspace/45.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sram_ctrl_bijection.172254537
Short name T293
Test name
Test status
Simulation time 4390974667 ps
CPU time 17.67 seconds
Started Feb 25 02:49:39 PM PST 24
Finished Feb 25 02:49:57 PM PST 24
Peak memory 202608 kb
Host smart-3934a1ee-8308-488b-a07c-77eefd848e03
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172254537 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_bijection.
172254537
Directory /workspace/45.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/45.sram_ctrl_executable.2431929464
Short name T643
Test name
Test status
Simulation time 8542638416 ps
CPU time 631.97 seconds
Started Feb 25 02:49:57 PM PST 24
Finished Feb 25 03:00:30 PM PST 24
Peak memory 374116 kb
Host smart-105544f7-bacb-4781-9f8b-0025cbcfc5d7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431929464 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_executab
le.2431929464
Directory /workspace/45.sram_ctrl_executable/latest

Test location /workspace/coverage/default/45.sram_ctrl_lc_escalation.92287453
Short name T418
Test name
Test status
Simulation time 2602226757 ps
CPU time 21.13 seconds
Started Feb 25 02:49:50 PM PST 24
Finished Feb 25 02:50:11 PM PST 24
Peak memory 210880 kb
Host smart-cd82f907-90b6-4b3f-850c-cf45953b44f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92287453 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_esc
alation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_lc_esca
lation.92287453
Directory /workspace/45.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/45.sram_ctrl_max_throughput.1697664992
Short name T655
Test name
Test status
Simulation time 411660477 ps
CPU time 70.84 seconds
Started Feb 25 02:49:50 PM PST 24
Finished Feb 25 02:51:01 PM PST 24
Peak memory 316008 kb
Host smart-27430f11-81df-481c-be27-e30424f62da0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697664992 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 45.sram_ctrl_max_throughput.1697664992
Directory /workspace/45.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_partial_access.3929224652
Short name T487
Test name
Test status
Simulation time 67263930 ps
CPU time 4.82 seconds
Started Feb 25 02:50:00 PM PST 24
Finished Feb 25 02:50:06 PM PST 24
Peak memory 215736 kb
Host smart-5f1e8363-689a-4447-88d0-21592b88ea01
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929224652 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_mem_partial_access.3929224652
Directory /workspace/45.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_mem_walk.128108739
Short name T124
Test name
Test status
Simulation time 849954676 ps
CPU time 9.5 seconds
Started Feb 25 02:49:50 PM PST 24
Finished Feb 25 02:50:00 PM PST 24
Peak memory 202568 kb
Host smart-e01ce73d-e561-4bdd-b654-51ec9d3e1fe3
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128108739 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=s
ram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl
_mem_walk.128108739
Directory /workspace/45.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/45.sram_ctrl_multiple_keys.3326690201
Short name T339
Test name
Test status
Simulation time 2334882247 ps
CPU time 842.45 seconds
Started Feb 25 02:49:41 PM PST 24
Finished Feb 25 03:03:45 PM PST 24
Peak memory 374468 kb
Host smart-8853065d-e9f9-48c3-ae60-37e7deca0fd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326690201 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_multi
ple_keys.3326690201
Directory /workspace/45.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access.1097960245
Short name T542
Test name
Test status
Simulation time 106988828 ps
CPU time 1.42 seconds
Started Feb 25 02:49:42 PM PST 24
Finished Feb 25 02:49:44 PM PST 24
Peak memory 202612 kb
Host smart-44b7a71c-fd2a-4c54-8747-6360eb5edf6b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097960245 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
sram_ctrl_partial_access.1097960245
Directory /workspace/45.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2910922063
Short name T441
Test name
Test status
Simulation time 15255870989 ps
CPU time 279 seconds
Started Feb 25 02:49:54 PM PST 24
Finished Feb 25 02:54:33 PM PST 24
Peak memory 202688 kb
Host smart-f0a0c78e-83b4-4bb0-b4b9-5cebc07ca20c
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910922063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 45.sram_ctrl_partial_access_b2b.2910922063
Directory /workspace/45.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/45.sram_ctrl_ram_cfg.3205923190
Short name T405
Test name
Test status
Simulation time 60920165 ps
CPU time 1.33 seconds
Started Feb 25 02:49:51 PM PST 24
Finished Feb 25 02:49:52 PM PST 24
Peak memory 202772 kb
Host smart-0ab97152-164f-4de6-b0ea-b178f8bf32b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205923190 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_ram_cfg.3205923190
Directory /workspace/45.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/45.sram_ctrl_regwen.27864188
Short name T642
Test name
Test status
Simulation time 39710363350 ps
CPU time 891.66 seconds
Started Feb 25 02:49:50 PM PST 24
Finished Feb 25 03:04:42 PM PST 24
Peak memory 364228 kb
Host smart-26d47aa6-d35a-4f6e-9e81-a2a72fa45bca
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27864188 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_regwen.27864188
Directory /workspace/45.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/45.sram_ctrl_smoke.1367244317
Short name T130
Test name
Test status
Simulation time 2944607819 ps
CPU time 12.26 seconds
Started Feb 25 02:49:40 PM PST 24
Finished Feb 25 02:49:53 PM PST 24
Peak memory 202508 kb
Host smart-d93c840b-42b8-463b-bb86-14cc813cf051
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367244317 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sram_ctrl_smoke.1367244317
Directory /workspace/45.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_all.4133097175
Short name T615
Test name
Test status
Simulation time 133240592674 ps
CPU time 1599.68 seconds
Started Feb 25 02:50:02 PM PST 24
Finished Feb 25 03:16:43 PM PST 24
Peak memory 374752 kb
Host smart-aec6f4c5-3854-497d-b4bc-e2c3441f1076
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133097175 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 45.sram_ctrl_stress_all.4133097175
Directory /workspace/45.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1214935703
Short name T239
Test name
Test status
Simulation time 2773643053 ps
CPU time 232.39 seconds
Started Feb 25 02:49:42 PM PST 24
Finished Feb 25 02:53:35 PM PST 24
Peak memory 202696 kb
Host smart-ef637270-31bb-4f09-9130-7dc1e55f2f67
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214935703 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.sram_ctrl_stress_pipeline.1214935703
Directory /workspace/45.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3861172345
Short name T847
Test name
Test status
Simulation time 616267514 ps
CPU time 128.61 seconds
Started Feb 25 02:49:51 PM PST 24
Finished Feb 25 02:52:00 PM PST 24
Peak memory 365344 kb
Host smart-36b31119-1136-42ac-989a-6e5bd793914c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861172345 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sram_ctrl_throughput_w_partial_write.3861172345
Directory /workspace/45.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3262174853
Short name T469
Test name
Test status
Simulation time 67034138609 ps
CPU time 2209.55 seconds
Started Feb 25 02:50:01 PM PST 24
Finished Feb 25 03:26:51 PM PST 24
Peak memory 374460 kb
Host smart-4a4a61f0-416d-4bcf-b779-bd3b761f22a4
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262174853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 46.sram_ctrl_access_during_key_req.3262174853
Directory /workspace/46.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/46.sram_ctrl_alert_test.221196068
Short name T231
Test name
Test status
Simulation time 12156519 ps
CPU time 0.64 seconds
Started Feb 25 02:50:12 PM PST 24
Finished Feb 25 02:50:13 PM PST 24
Peak memory 201500 kb
Host smart-924b0726-b4f6-4f0a-8971-53563a68c10f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221196068 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UV
M_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.sram_ctrl_alert_test.221196068
Directory /workspace/46.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sram_ctrl_bijection.2453787594
Short name T234
Test name
Test status
Simulation time 670191276 ps
CPU time 44.08 seconds
Started Feb 25 02:50:03 PM PST 24
Finished Feb 25 02:50:47 PM PST 24
Peak memory 202616 kb
Host smart-f5da5abe-cfef-46e1-a578-65537296e79d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453787594 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_bijection
.2453787594
Directory /workspace/46.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/46.sram_ctrl_executable.24609328
Short name T434
Test name
Test status
Simulation time 16135220873 ps
CPU time 557.76 seconds
Started Feb 25 02:50:02 PM PST 24
Finished Feb 25 02:59:20 PM PST 24
Peak memory 369316 kb
Host smart-95b41896-4865-42e3-844e-6b3ff69d2ba2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24609328 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execut
able_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_executable
.24609328
Directory /workspace/46.sram_ctrl_executable/latest

Test location /workspace/coverage/default/46.sram_ctrl_lc_escalation.4012656292
Short name T499
Test name
Test status
Simulation time 561162864 ps
CPU time 12.26 seconds
Started Feb 25 02:50:00 PM PST 24
Finished Feb 25 02:50:13 PM PST 24
Peak memory 210848 kb
Host smart-9bc82652-3f65-40b5-bac1-2ad44e27dcd7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012656292 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_lc_es
calation.4012656292
Directory /workspace/46.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/46.sram_ctrl_max_throughput.994255082
Short name T537
Test name
Test status
Simulation time 149124851 ps
CPU time 4.6 seconds
Started Feb 25 02:50:04 PM PST 24
Finished Feb 25 02:50:08 PM PST 24
Peak memory 222932 kb
Host smart-5a3e0b7a-9eef-4c66-ba51-62ba153eb7e0
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994255082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.sram_ctrl_max_throughput.994255082
Directory /workspace/46.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_partial_access.506074242
Short name T340
Test name
Test status
Simulation time 525215838 ps
CPU time 4.9 seconds
Started Feb 25 02:50:13 PM PST 24
Finished Feb 25 02:50:18 PM PST 24
Peak memory 211768 kb
Host smart-be9512ed-320a-45e0-a590-88b30239f836
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506074242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.sram_ctrl_mem_partial_access.506074242
Directory /workspace/46.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_mem_walk.3012242231
Short name T543
Test name
Test status
Simulation time 2716274757 ps
CPU time 10.33 seconds
Started Feb 25 02:50:11 PM PST 24
Finished Feb 25 02:50:21 PM PST 24
Peak memory 202632 kb
Host smart-19b7dd14-0bdd-4da3-846c-a682649a9232
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012242231 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctr
l_mem_walk.3012242231
Directory /workspace/46.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/46.sram_ctrl_multiple_keys.1468700633
Short name T539
Test name
Test status
Simulation time 26223840133 ps
CPU time 1161.5 seconds
Started Feb 25 02:50:03 PM PST 24
Finished Feb 25 03:09:24 PM PST 24
Peak memory 369396 kb
Host smart-594d74be-7e8a-4b37-88f3-ceddd8b5599e
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468700633 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_multi
ple_keys.1468700633
Directory /workspace/46.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access.1796241620
Short name T614
Test name
Test status
Simulation time 901169897 ps
CPU time 19.11 seconds
Started Feb 25 02:50:02 PM PST 24
Finished Feb 25 02:50:21 PM PST 24
Peak memory 265908 kb
Host smart-ca034ad9-36be-47f1-9766-5de3a3cc330d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796241620 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
sram_ctrl_partial_access.1796241620
Directory /workspace/46.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3878163827
Short name T774
Test name
Test status
Simulation time 12320982109 ps
CPU time 312.7 seconds
Started Feb 25 02:50:03 PM PST 24
Finished Feb 25 02:55:16 PM PST 24
Peak memory 202808 kb
Host smart-b3491c37-f98f-4450-ba57-c14a7bd96120
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878163827 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_partial_access_b2b.3878163827
Directory /workspace/46.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/46.sram_ctrl_ram_cfg.1083625450
Short name T664
Test name
Test status
Simulation time 36599039 ps
CPU time 1.53 seconds
Started Feb 25 02:50:02 PM PST 24
Finished Feb 25 02:50:04 PM PST 24
Peak memory 202776 kb
Host smart-a697238f-a2b9-411d-adea-0bef05c23c1a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083625450 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_ram_cfg.1083625450
Directory /workspace/46.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/46.sram_ctrl_regwen.2666420893
Short name T24
Test name
Test status
Simulation time 47335275903 ps
CPU time 462.85 seconds
Started Feb 25 02:50:01 PM PST 24
Finished Feb 25 02:57:44 PM PST 24
Peak memory 367564 kb
Host smart-ad5a5d1a-7cf3-4f95-871b-b8825125eee5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666420893 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_regwen.2666420893
Directory /workspace/46.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/46.sram_ctrl_smoke.2472187287
Short name T793
Test name
Test status
Simulation time 408677076 ps
CPU time 7.75 seconds
Started Feb 25 02:50:03 PM PST 24
Finished Feb 25 02:50:11 PM PST 24
Peak memory 202628 kb
Host smart-5fa742c0-0bc2-4659-958d-82f0019e18b2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472187287 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sram_ctrl_smoke.2472187287
Directory /workspace/46.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_all.864231297
Short name T170
Test name
Test status
Simulation time 11646745452 ps
CPU time 3098.58 seconds
Started Feb 25 02:50:10 PM PST 24
Finished Feb 25 03:41:49 PM PST 24
Peak memory 375496 kb
Host smart-6400d7ba-a2d5-4bb2-ad78-2af7ec810f95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864231297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 46.sram_ctrl_stress_all.864231297
Directory /workspace/46.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2896023420
Short name T205
Test name
Test status
Simulation time 2886209814 ps
CPU time 273.54 seconds
Started Feb 25 02:50:03 PM PST 24
Finished Feb 25 02:54:37 PM PST 24
Peak memory 202684 kb
Host smart-4764f07c-a7e7-4716-b7b1-269c24bf9a18
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896023420 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.sram_ctrl_stress_pipeline.2896023420
Directory /workspace/46.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3018017171
Short name T753
Test name
Test status
Simulation time 546472752 ps
CPU time 146.1 seconds
Started Feb 25 02:50:04 PM PST 24
Finished Feb 25 02:52:30 PM PST 24
Peak memory 365744 kb
Host smart-6a6ee53e-14bb-4067-9456-f5de59f5cdc8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018017171 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sram_ctrl_throughput_w_partial_write.3018017171
Directory /workspace/46.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3216389692
Short name T168
Test name
Test status
Simulation time 16621149552 ps
CPU time 1121.37 seconds
Started Feb 25 02:50:12 PM PST 24
Finished Feb 25 03:08:54 PM PST 24
Peak memory 373436 kb
Host smart-ee0acd08-7f95-4a0e-bcd2-2179b35c2b5a
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216389692 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 47.sram_ctrl_access_during_key_req.3216389692
Directory /workspace/47.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/47.sram_ctrl_alert_test.1299704971
Short name T829
Test name
Test status
Simulation time 14252635 ps
CPU time 0.65 seconds
Started Feb 25 02:50:12 PM PST 24
Finished Feb 25 02:50:13 PM PST 24
Peak memory 201700 kb
Host smart-44bae84e-64bb-412d-832a-7751489cd6e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299704971 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.sram_ctrl_alert_test.1299704971
Directory /workspace/47.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sram_ctrl_bijection.3815540005
Short name T844
Test name
Test status
Simulation time 34560118323 ps
CPU time 93.59 seconds
Started Feb 25 02:50:12 PM PST 24
Finished Feb 25 02:51:45 PM PST 24
Peak memory 202620 kb
Host smart-d964650c-180d-4527-9073-40296d4ac829
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815540005 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_bijection
.3815540005
Directory /workspace/47.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/47.sram_ctrl_executable.1314621772
Short name T573
Test name
Test status
Simulation time 28585552407 ps
CPU time 879.18 seconds
Started Feb 25 02:50:15 PM PST 24
Finished Feb 25 03:04:54 PM PST 24
Peak memory 372780 kb
Host smart-0d94f82e-e2bf-42a0-b60b-b542e57f09f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314621772 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_executab
le.1314621772
Directory /workspace/47.sram_ctrl_executable/latest

Test location /workspace/coverage/default/47.sram_ctrl_lc_escalation.3988352294
Short name T479
Test name
Test status
Simulation time 2145177426 ps
CPU time 8.21 seconds
Started Feb 25 02:50:12 PM PST 24
Finished Feb 25 02:50:21 PM PST 24
Peak memory 210804 kb
Host smart-eb9420f9-e97d-401d-aa59-05aedf560f8c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988352294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_lc_es
calation.3988352294
Directory /workspace/47.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/47.sram_ctrl_max_throughput.965904897
Short name T876
Test name
Test status
Simulation time 113229813 ps
CPU time 66.67 seconds
Started Feb 25 02:50:14 PM PST 24
Finished Feb 25 02:51:20 PM PST 24
Peak memory 311248 kb
Host smart-95e46579-66d3-4774-8c62-6a2e3c2d0523
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965904897 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.sram_ctrl_max_throughput.965904897
Directory /workspace/47.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_partial_access.1682925312
Short name T478
Test name
Test status
Simulation time 68224951 ps
CPU time 5.17 seconds
Started Feb 25 02:50:13 PM PST 24
Finished Feb 25 02:50:18 PM PST 24
Peak memory 212140 kb
Host smart-fed75798-d6be-4135-afff-989c51d94ed0
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682925312 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_mem_partial_access.1682925312
Directory /workspace/47.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_mem_walk.1265017761
Short name T840
Test name
Test status
Simulation time 2056153979 ps
CPU time 6.34 seconds
Started Feb 25 02:50:13 PM PST 24
Finished Feb 25 02:50:20 PM PST 24
Peak memory 202576 kb
Host smart-b7214429-030a-4f52-a2d2-23a65d1e3cce
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265017761 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctr
l_mem_walk.1265017761
Directory /workspace/47.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/47.sram_ctrl_multiple_keys.469612582
Short name T682
Test name
Test status
Simulation time 11799861926 ps
CPU time 601.03 seconds
Started Feb 25 02:50:15 PM PST 24
Finished Feb 25 03:00:16 PM PST 24
Peak memory 371772 kb
Host smart-ca09ef3c-df31-4f21-8ed5-8d2526e1d26d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469612582 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_multip
le_keys.469612582
Directory /workspace/47.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access.1219023238
Short name T861
Test name
Test status
Simulation time 571040077 ps
CPU time 82.09 seconds
Started Feb 25 02:50:18 PM PST 24
Finished Feb 25 02:51:40 PM PST 24
Peak memory 334368 kb
Host smart-5eb082d1-1413-4e29-a17e-318d45d07d7d
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219023238 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
sram_ctrl_partial_access.1219023238
Directory /workspace/47.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3962200760
Short name T773
Test name
Test status
Simulation time 8685246651 ps
CPU time 206.97 seconds
Started Feb 25 02:50:11 PM PST 24
Finished Feb 25 02:53:38 PM PST 24
Peak memory 202648 kb
Host smart-b9e1baa3-b994-4326-bf41-2b1bd327efd8
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962200760 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 47.sram_ctrl_partial_access_b2b.3962200760
Directory /workspace/47.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/47.sram_ctrl_ram_cfg.2081584979
Short name T563
Test name
Test status
Simulation time 30809316 ps
CPU time 1.09 seconds
Started Feb 25 02:50:11 PM PST 24
Finished Feb 25 02:50:13 PM PST 24
Peak memory 202836 kb
Host smart-f006a77b-82f1-4197-b7f9-76066d322b55
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081584979 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_ram_cfg.2081584979
Directory /workspace/47.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/47.sram_ctrl_regwen.554616860
Short name T438
Test name
Test status
Simulation time 16022163781 ps
CPU time 907.27 seconds
Started Feb 25 02:50:18 PM PST 24
Finished Feb 25 03:05:25 PM PST 24
Peak memory 365192 kb
Host smart-c0535dff-1c6c-4484-b16f-1f28e7803f67
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554616860 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_regwen.554616860
Directory /workspace/47.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/47.sram_ctrl_smoke.332097416
Short name T432
Test name
Test status
Simulation time 218837621 ps
CPU time 73.18 seconds
Started Feb 25 02:50:13 PM PST 24
Finished Feb 25 02:51:26 PM PST 24
Peak memory 319880 kb
Host smart-c39245d7-784e-4380-8433-d5b42c09d305
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332097416 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sram_ctrl_smoke.332097416
Directory /workspace/47.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_all.1016185297
Short name T483
Test name
Test status
Simulation time 17537561270 ps
CPU time 2210.67 seconds
Started Feb 25 02:50:19 PM PST 24
Finished Feb 25 03:27:10 PM PST 24
Peak memory 382624 kb
Host smart-a9084fb7-1cab-4cc3-b04a-ebfb5ac8366e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016185297 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 47.sram_ctrl_stress_all.1016185297
Directory /workspace/47.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2371901387
Short name T850
Test name
Test status
Simulation time 2466534405 ps
CPU time 237 seconds
Started Feb 25 02:50:14 PM PST 24
Finished Feb 25 02:54:11 PM PST 24
Peak memory 202636 kb
Host smart-868e0783-a169-437a-a97c-b3e1820b4cb8
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371901387 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.sram_ctrl_stress_pipeline.2371901387
Directory /workspace/47.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1952429645
Short name T247
Test name
Test status
Simulation time 1295549957 ps
CPU time 86.19 seconds
Started Feb 25 02:50:11 PM PST 24
Finished Feb 25 02:51:38 PM PST 24
Peak memory 337484 kb
Host smart-74c35962-30d5-40dc-9b26-1104c7f17a6c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952429645 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sram_ctrl_throughput_w_partial_write.1952429645
Directory /workspace/47.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1347146612
Short name T827
Test name
Test status
Simulation time 4082502292 ps
CPU time 1155.45 seconds
Started Feb 25 02:50:21 PM PST 24
Finished Feb 25 03:09:37 PM PST 24
Peak memory 373456 kb
Host smart-241422f2-ab9a-4c3c-a25e-2e9fc28d06c0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347146612 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 48.sram_ctrl_access_during_key_req.1347146612
Directory /workspace/48.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/48.sram_ctrl_alert_test.1020792793
Short name T26
Test name
Test status
Simulation time 25500356 ps
CPU time 0.68 seconds
Started Feb 25 02:50:21 PM PST 24
Finished Feb 25 02:50:22 PM PST 24
Peak memory 201720 kb
Host smart-1a7e4b0d-7d28-480d-9207-0df2f6c5a643
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020792793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.sram_ctrl_alert_test.1020792793
Directory /workspace/48.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sram_ctrl_bijection.535283349
Short name T251
Test name
Test status
Simulation time 877645995 ps
CPU time 28.21 seconds
Started Feb 25 02:50:11 PM PST 24
Finished Feb 25 02:50:39 PM PST 24
Peak memory 202612 kb
Host smart-bb1b110b-5734-4f10-80c0-0fb8fefaf245
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535283349 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijec
tion_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_bijection.
535283349
Directory /workspace/48.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/48.sram_ctrl_executable.398703719
Short name T285
Test name
Test status
Simulation time 1866798338 ps
CPU time 142.18 seconds
Started Feb 25 02:50:20 PM PST 24
Finished Feb 25 02:52:42 PM PST 24
Peak memory 311880 kb
Host smart-9937fa5e-928e-49c7-a89f-0b1b6e0fcc06
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398703719 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_executabl
e.398703719
Directory /workspace/48.sram_ctrl_executable/latest

Test location /workspace/coverage/default/48.sram_ctrl_lc_escalation.1428268793
Short name T675
Test name
Test status
Simulation time 623744854 ps
CPU time 8.57 seconds
Started Feb 25 02:50:21 PM PST 24
Finished Feb 25 02:50:30 PM PST 24
Peak memory 210828 kb
Host smart-8ab99d4f-f39a-45f2-8608-6f217f611600
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428268793 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_lc_es
calation.1428268793
Directory /workspace/48.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/48.sram_ctrl_max_throughput.77834073
Short name T613
Test name
Test status
Simulation time 97883294 ps
CPU time 28.61 seconds
Started Feb 25 02:50:21 PM PST 24
Finished Feb 25 02:50:49 PM PST 24
Peak memory 284072 kb
Host smart-0dc1b959-da47-4c41-bc52-6611495bb6e8
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77834073 -assert nopostproc +UVM_TESTNAME=sram_ctrl_bas
e_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.sram_ctrl_max_throughput.77834073
Directory /workspace/48.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_partial_access.867713021
Short name T519
Test name
Test status
Simulation time 1583195783 ps
CPU time 5.46 seconds
Started Feb 25 02:50:20 PM PST 24
Finished Feb 25 02:50:26 PM PST 24
Peak memory 210792 kb
Host smart-7d248e35-3063-44ec-9c49-f711959420b7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867713021 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.sram_ctrl_mem_partial_access.867713021
Directory /workspace/48.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_mem_walk.1121755381
Short name T768
Test name
Test status
Simulation time 1337668288 ps
CPU time 4.76 seconds
Started Feb 25 02:50:22 PM PST 24
Finished Feb 25 02:50:27 PM PST 24
Peak memory 202580 kb
Host smart-d667b4c6-4ea4-407a-91e4-0b8e4c24bb34
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121755381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctr
l_mem_walk.1121755381
Directory /workspace/48.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/48.sram_ctrl_multiple_keys.1638401145
Short name T632
Test name
Test status
Simulation time 58481662027 ps
CPU time 1136.83 seconds
Started Feb 25 02:50:13 PM PST 24
Finished Feb 25 03:09:10 PM PST 24
Peak memory 354976 kb
Host smart-ee6170de-06e2-41a8-b4ac-9c730df122f9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638401145 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_multi
ple_keys.1638401145
Directory /workspace/48.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/48.sram_ctrl_partial_access.2044887635
Short name T480
Test name
Test status
Simulation time 735800556 ps
CPU time 136.67 seconds
Started Feb 25 02:50:20 PM PST 24
Finished Feb 25 02:52:36 PM PST 24
Peak memory 367128 kb
Host smart-4f405b7f-7fa3-4438-8f65-889e4fd85c73
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044887635 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
sram_ctrl_partial_access.2044887635
Directory /workspace/48.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/48.sram_ctrl_ram_cfg.1643267465
Short name T261
Test name
Test status
Simulation time 237980464 ps
CPU time 0.83 seconds
Started Feb 25 02:50:23 PM PST 24
Finished Feb 25 02:50:24 PM PST 24
Peak memory 202604 kb
Host smart-17fad406-44a6-4e36-a1cc-3058784cf7f2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643267465 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_ram_cfg.1643267465
Directory /workspace/48.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/48.sram_ctrl_regwen.2592996235
Short name T725
Test name
Test status
Simulation time 1823867948 ps
CPU time 540.32 seconds
Started Feb 25 02:50:23 PM PST 24
Finished Feb 25 02:59:23 PM PST 24
Peak memory 370316 kb
Host smart-d5e16008-2812-4e93-b736-85afa214b3e3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592996235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_regwen.2592996235
Directory /workspace/48.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/48.sram_ctrl_smoke.4139182004
Short name T715
Test name
Test status
Simulation time 491639182 ps
CPU time 33.2 seconds
Started Feb 25 02:50:12 PM PST 24
Finished Feb 25 02:50:45 PM PST 24
Peak memory 288920 kb
Host smart-f76e7224-805c-482e-8058-5a4a5fd8ab0d
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139182004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sram_ctrl_smoke.4139182004
Directory /workspace/48.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_all.3833505959
Short name T31
Test name
Test status
Simulation time 35483751850 ps
CPU time 4242.36 seconds
Started Feb 25 02:50:22 PM PST 24
Finished Feb 25 04:01:04 PM PST 24
Peak memory 375064 kb
Host smart-b1ae6d4e-d18e-404e-ab6e-b6ea5612b5ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833505959 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 48.sram_ctrl_stress_all.3833505959
Directory /workspace/48.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sram_ctrl_stress_pipeline.3275027143
Short name T775
Test name
Test status
Simulation time 6354422567 ps
CPU time 156.05 seconds
Started Feb 25 02:50:13 PM PST 24
Finished Feb 25 02:52:49 PM PST 24
Peak memory 202676 kb
Host smart-5d1f98f8-00df-4875-8c60-dc8c4269180e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275027143 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.sram_ctrl_stress_pipeline.3275027143
Directory /workspace/48.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3512411722
Short name T536
Test name
Test status
Simulation time 54699605 ps
CPU time 4.2 seconds
Started Feb 25 02:50:22 PM PST 24
Finished Feb 25 02:50:26 PM PST 24
Peak memory 218952 kb
Host smart-78cce26e-4459-4b6a-a5bd-264dcc6c7dca
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512411722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sram_ctrl_throughput_w_partial_write.3512411722
Directory /workspace/48.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2344607817
Short name T237
Test name
Test status
Simulation time 3917195080 ps
CPU time 1511.04 seconds
Started Feb 25 02:50:32 PM PST 24
Finished Feb 25 03:15:44 PM PST 24
Peak memory 373452 kb
Host smart-50062c1b-9fee-4d95-bbe9-2ecaf98af663
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344607817 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 49.sram_ctrl_access_during_key_req.2344607817
Directory /workspace/49.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/49.sram_ctrl_alert_test.2087341780
Short name T256
Test name
Test status
Simulation time 12526604 ps
CPU time 0.66 seconds
Started Feb 25 02:50:33 PM PST 24
Finished Feb 25 02:50:34 PM PST 24
Peak memory 201500 kb
Host smart-bc6e73d7-def9-4909-a816-d274bebe2067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087341780 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.sram_ctrl_alert_test.2087341780
Directory /workspace/49.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sram_ctrl_bijection.2210254995
Short name T262
Test name
Test status
Simulation time 728186368 ps
CPU time 22.97 seconds
Started Feb 25 02:50:21 PM PST 24
Finished Feb 25 02:50:44 PM PST 24
Peak memory 202616 kb
Host smart-516c2fd8-a335-4465-af26-cf952822132c
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210254995 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_bijection
.2210254995
Directory /workspace/49.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/49.sram_ctrl_executable.775186960
Short name T515
Test name
Test status
Simulation time 15736394305 ps
CPU time 309.05 seconds
Started Feb 25 02:50:34 PM PST 24
Finished Feb 25 02:55:43 PM PST 24
Peak memory 372296 kb
Host smart-2012cfcf-610f-4f9a-858d-868a1949bc43
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775186960 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_executabl
e.775186960
Directory /workspace/49.sram_ctrl_executable/latest

Test location /workspace/coverage/default/49.sram_ctrl_max_throughput.3479309034
Short name T634
Test name
Test status
Simulation time 444066057 ps
CPU time 83.04 seconds
Started Feb 25 02:50:32 PM PST 24
Finished Feb 25 02:51:56 PM PST 24
Peak memory 335324 kb
Host smart-6ceb0732-44d1-433b-9d9a-04f7e71a085b
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479309034 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_max_throughput.3479309034
Directory /workspace/49.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1647509690
Short name T278
Test name
Test status
Simulation time 410672308 ps
CPU time 3.16 seconds
Started Feb 25 02:50:34 PM PST 24
Finished Feb 25 02:50:38 PM PST 24
Peak memory 210836 kb
Host smart-3365bedf-043b-4601-a0a5-251bf2063d10
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647509690 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.sram_ctrl_mem_partial_access.1647509690
Directory /workspace/49.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_mem_walk.1015520875
Short name T257
Test name
Test status
Simulation time 937469570 ps
CPU time 10.01 seconds
Started Feb 25 02:50:36 PM PST 24
Finished Feb 25 02:50:46 PM PST 24
Peak memory 202564 kb
Host smart-e1bb4501-aae0-4e95-9db9-b86381484853
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015520875 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctr
l_mem_walk.1015520875
Directory /workspace/49.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/49.sram_ctrl_multiple_keys.1379483142
Short name T641
Test name
Test status
Simulation time 5296932464 ps
CPU time 1008.32 seconds
Started Feb 25 02:50:22 PM PST 24
Finished Feb 25 03:07:10 PM PST 24
Peak memory 374612 kb
Host smart-4c710e36-1998-414b-b6af-d8430edea971
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379483142 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_multi
ple_keys.1379483142
Directory /workspace/49.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access.1233542762
Short name T398
Test name
Test status
Simulation time 130190722 ps
CPU time 28.68 seconds
Started Feb 25 02:50:37 PM PST 24
Finished Feb 25 02:51:06 PM PST 24
Peak memory 277588 kb
Host smart-5cc172e1-5415-4a6b-8e8f-a04964f1aa87
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233542762 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
sram_ctrl_partial_access.1233542762
Directory /workspace/49.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3274290528
Short name T685
Test name
Test status
Simulation time 19697799063 ps
CPU time 493.27 seconds
Started Feb 25 02:50:34 PM PST 24
Finished Feb 25 02:58:48 PM PST 24
Peak memory 202672 kb
Host smart-1ef46653-7eea-46f5-b6ef-cf35abc4cca6
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274290528 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_partial_access_b2b.3274290528
Directory /workspace/49.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/49.sram_ctrl_ram_cfg.2523746471
Short name T140
Test name
Test status
Simulation time 70975672 ps
CPU time 0.89 seconds
Started Feb 25 02:50:34 PM PST 24
Finished Feb 25 02:50:36 PM PST 24
Peak memory 202564 kb
Host smart-01ade2a9-4b23-4b40-b60b-8eab8ca81c4b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523746471 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_ram_cfg.2523746471
Directory /workspace/49.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/49.sram_ctrl_regwen.2164093227
Short name T30
Test name
Test status
Simulation time 61349121 ps
CPU time 10.2 seconds
Started Feb 25 02:50:33 PM PST 24
Finished Feb 25 02:50:44 PM PST 24
Peak memory 245488 kb
Host smart-1352bd95-7e8b-42bd-8c37-c2d1248d8ea0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164093227 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_regwen.2164093227
Directory /workspace/49.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/49.sram_ctrl_smoke.2713598294
Short name T279
Test name
Test status
Simulation time 191623112 ps
CPU time 11.55 seconds
Started Feb 25 02:50:20 PM PST 24
Finished Feb 25 02:50:31 PM PST 24
Peak memory 202620 kb
Host smart-0a458115-ee34-47dd-8570-bc5eb90f56c2
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713598294 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sram_ctrl_smoke.2713598294
Directory /workspace/49.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_all.693185533
Short name T177
Test name
Test status
Simulation time 281108400106 ps
CPU time 3478.22 seconds
Started Feb 25 02:50:35 PM PST 24
Finished Feb 25 03:48:33 PM PST 24
Peak memory 375476 kb
Host smart-80d6c359-a46b-4b33-9502-a69b9c1d5131
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693185533 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 49.sram_ctrl_stress_all.693185533
Directory /workspace/49.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sram_ctrl_stress_pipeline.357588586
Short name T828
Test name
Test status
Simulation time 3626109584 ps
CPU time 179.98 seconds
Started Feb 25 02:50:22 PM PST 24
Finished Feb 25 02:53:22 PM PST 24
Peak memory 202692 kb
Host smart-604c8d82-481f-439b-a064-a90ac84a0341
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357588586 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.sram_ctrl_stress_pipeline.357588586
Directory /workspace/49.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.196948041
Short name T147
Test name
Test status
Simulation time 675936552 ps
CPU time 172.41 seconds
Started Feb 25 02:50:37 PM PST 24
Finished Feb 25 02:53:30 PM PST 24
Peak memory 365688 kb
Host smart-3d3f1d48-b98c-4bf2-ac99-cae61cc88f53
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196948041 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sram_ctrl_throughput_w_partial_write.196948041
Directory /workspace/49.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/5.sram_ctrl_access_during_key_req.4234616012
Short name T136
Test name
Test status
Simulation time 875370184 ps
CPU time 90.91 seconds
Started Feb 25 02:46:05 PM PST 24
Finished Feb 25 02:47:36 PM PST 24
Peak memory 310960 kb
Host smart-c8ee71de-01e4-44b6-aa4b-bf32e4264fe0
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234616012 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 5.sram_ctrl_access_during_key_req.4234616012
Directory /workspace/5.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/5.sram_ctrl_alert_test.3793939806
Short name T280
Test name
Test status
Simulation time 37658546 ps
CPU time 0.64 seconds
Started Feb 25 02:46:04 PM PST 24
Finished Feb 25 02:46:05 PM PST 24
Peak memory 201688 kb
Host smart-6cc827dc-3ad1-4083-b141-c873f940640a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793939806 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.sram_ctrl_alert_test.3793939806
Directory /workspace/5.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sram_ctrl_bijection.4094799927
Short name T751
Test name
Test status
Simulation time 16768086802 ps
CPU time 62.99 seconds
Started Feb 25 02:46:08 PM PST 24
Finished Feb 25 02:47:11 PM PST 24
Peak memory 202692 kb
Host smart-b8bbb968-74a4-44f9-9314-503d0b7ba024
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094799927 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_bijection.
4094799927
Directory /workspace/5.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/5.sram_ctrl_executable.4005636156
Short name T174
Test name
Test status
Simulation time 2728340583 ps
CPU time 819.42 seconds
Started Feb 25 02:46:02 PM PST 24
Finished Feb 25 02:59:42 PM PST 24
Peak memory 362180 kb
Host smart-2058e12e-525b-4bc0-a25e-23ea8ff36953
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005636156 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_executabl
e.4005636156
Directory /workspace/5.sram_ctrl_executable/latest

Test location /workspace/coverage/default/5.sram_ctrl_lc_escalation.3866535049
Short name T230
Test name
Test status
Simulation time 1598861462 ps
CPU time 5.47 seconds
Started Feb 25 02:45:59 PM PST 24
Finished Feb 25 02:46:05 PM PST 24
Peak memory 210776 kb
Host smart-30ab59e5-4f29-42ca-8e7d-62371e4091bf
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866535049 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_lc_esc
alation.3866535049
Directory /workspace/5.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/5.sram_ctrl_max_throughput.1812531578
Short name T344
Test name
Test status
Simulation time 842814444 ps
CPU time 34.06 seconds
Started Feb 25 02:46:05 PM PST 24
Finished Feb 25 02:46:39 PM PST 24
Peak memory 286452 kb
Host smart-db959965-7dca-4988-8d07-27d7b3d68e18
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812531578 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sram_ctrl_max_throughput.1812531578
Directory /workspace/5.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2701623853
Short name T299
Test name
Test status
Simulation time 83605754 ps
CPU time 3.1 seconds
Started Feb 25 02:46:00 PM PST 24
Finished Feb 25 02:46:03 PM PST 24
Peak memory 210844 kb
Host smart-0ecdde70-bf52-4429-9d73-9e7d15a916d7
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701623853 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.sram_ctrl_mem_partial_access.2701623853
Directory /workspace/5.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_mem_walk.1431111082
Short name T310
Test name
Test status
Simulation time 344299286 ps
CPU time 5.74 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 02:46:07 PM PST 24
Peak memory 202588 kb
Host smart-c328c5a2-0733-455d-80d1-4d685a0a543a
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431111082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl
_mem_walk.1431111082
Directory /workspace/5.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/5.sram_ctrl_multiple_keys.1428693063
Short name T44
Test name
Test status
Simulation time 8964340276 ps
CPU time 791.65 seconds
Started Feb 25 02:46:00 PM PST 24
Finished Feb 25 02:59:12 PM PST 24
Peak memory 356752 kb
Host smart-fe21a930-9fb9-4b76-91ee-a85a507b8e9a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428693063 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_multip
le_keys.1428693063
Directory /workspace/5.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access.360897381
Short name T318
Test name
Test status
Simulation time 395833657 ps
CPU time 116.52 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 02:47:58 PM PST 24
Peak memory 357604 kb
Host smart-e98aa888-ad9a-43cb-814f-197a2e0945e4
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360897381 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sr
am_ctrl_partial_access.360897381
Directory /workspace/5.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1897543712
Short name T752
Test name
Test status
Simulation time 6416906713 ps
CPU time 242.37 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 02:50:03 PM PST 24
Peak memory 202676 kb
Host smart-f00fbeda-7ba6-4221-82c0-891009c62f1b
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897543712 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_partial_access_b2b.1897543712
Directory /workspace/5.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/5.sram_ctrl_ram_cfg.1307431281
Short name T821
Test name
Test status
Simulation time 90857325 ps
CPU time 3.19 seconds
Started Feb 25 02:45:59 PM PST 24
Finished Feb 25 02:46:03 PM PST 24
Peak memory 202752 kb
Host smart-d8635f02-7f60-452f-a647-00c0924f9ea4
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307431281 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_ram_cfg.1307431281
Directory /workspace/5.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/5.sram_ctrl_regwen.2241546872
Short name T524
Test name
Test status
Simulation time 2316429566 ps
CPU time 601.93 seconds
Started Feb 25 02:46:03 PM PST 24
Finished Feb 25 02:56:05 PM PST 24
Peak memory 367288 kb
Host smart-84506ad0-af33-466e-8178-9dfce9865427
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241546872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_regwen.2241546872
Directory /workspace/5.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/5.sram_ctrl_smoke.366929740
Short name T495
Test name
Test status
Simulation time 1387842154 ps
CPU time 5.93 seconds
Started Feb 25 02:45:59 PM PST 24
Finished Feb 25 02:46:05 PM PST 24
Peak memory 224560 kb
Host smart-6cbb56b1-ae59-4d54-95b2-c6d867622a60
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366929740 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sram_ctrl_smoke.366929740
Directory /workspace/5.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_all.252988082
Short name T194
Test name
Test status
Simulation time 51456922974 ps
CPU time 3551.84 seconds
Started Feb 25 02:46:04 PM PST 24
Finished Feb 25 03:45:17 PM PST 24
Peak memory 373288 kb
Host smart-0e626999-8945-43eb-9ff2-243027fa0af8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252988082 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 5.sram_ctrl_stress_all.252988082
Directory /workspace/5.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sram_ctrl_stress_pipeline.900199831
Short name T516
Test name
Test status
Simulation time 2608677234 ps
CPU time 237.47 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 02:49:58 PM PST 24
Peak memory 202704 kb
Host smart-4930af77-4be3-43b0-b612-9e4d77f0db30
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900199831 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
sram_ctrl_stress_pipeline.900199831
Directory /workspace/5.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.60196499
Short name T687
Test name
Test status
Simulation time 286378017 ps
CPU time 17.5 seconds
Started Feb 25 02:46:02 PM PST 24
Finished Feb 25 02:46:20 PM PST 24
Peak memory 260776 kb
Host smart-a829a39c-7a63-4523-877e-5ae3bc452642
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60196499 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.sram_ctrl_throughput_w_partial_write.60196499
Directory /workspace/5.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/6.sram_ctrl_access_during_key_req.4090270052
Short name T697
Test name
Test status
Simulation time 13012498740 ps
CPU time 282.68 seconds
Started Feb 25 02:45:59 PM PST 24
Finished Feb 25 02:50:42 PM PST 24
Peak memory 364268 kb
Host smart-99b8c771-6b8d-423a-a7f4-a6e0146adcc7
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090270052 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 6.sram_ctrl_access_during_key_req.4090270052
Directory /workspace/6.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/6.sram_ctrl_alert_test.1144150546
Short name T610
Test name
Test status
Simulation time 14363682 ps
CPU time 0.68 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 02:46:02 PM PST 24
Peak memory 201512 kb
Host smart-72de6d5c-1c98-40dd-95f4-d9aec2bded23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144150546 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.sram_ctrl_alert_test.1144150546
Directory /workspace/6.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sram_ctrl_bijection.3419757026
Short name T249
Test name
Test status
Simulation time 10998478572 ps
CPU time 87.98 seconds
Started Feb 25 02:46:06 PM PST 24
Finished Feb 25 02:47:34 PM PST 24
Peak memory 202656 kb
Host smart-a9574cb1-7455-4186-8bbb-901bd4389e7f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419757026 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_bijection.
3419757026
Directory /workspace/6.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/6.sram_ctrl_executable.1691542856
Short name T651
Test name
Test status
Simulation time 37069409819 ps
CPU time 899.57 seconds
Started Feb 25 02:46:06 PM PST 24
Finished Feb 25 03:01:05 PM PST 24
Peak memory 374408 kb
Host smart-0adc64d0-a796-42f7-b974-fba14954b567
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691542856 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_executabl
e.1691542856
Directory /workspace/6.sram_ctrl_executable/latest

Test location /workspace/coverage/default/6.sram_ctrl_lc_escalation.2086190852
Short name T702
Test name
Test status
Simulation time 1954222879 ps
CPU time 16.59 seconds
Started Feb 25 02:46:04 PM PST 24
Finished Feb 25 02:46:21 PM PST 24
Peak memory 210880 kb
Host smart-a00a42c3-e6fc-420b-8a7a-7bdbddb8143a
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086190852 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_lc_esc
alation.2086190852
Directory /workspace/6.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/6.sram_ctrl_max_throughput.2441746069
Short name T547
Test name
Test status
Simulation time 71632778 ps
CPU time 2.64 seconds
Started Feb 25 02:46:05 PM PST 24
Finished Feb 25 02:46:08 PM PST 24
Peak memory 210864 kb
Host smart-3bea846c-a639-4a06-9ce6-7f62c1e6df3d
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441746069 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 6.sram_ctrl_max_throughput.2441746069
Directory /workspace/6.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_partial_access.3202819646
Short name T420
Test name
Test status
Simulation time 168322626 ps
CPU time 5.55 seconds
Started Feb 25 02:46:08 PM PST 24
Finished Feb 25 02:46:14 PM PST 24
Peak memory 210872 kb
Host smart-d0658002-2ddb-48b1-a341-5330d6647fdd
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202819646 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_mem_partial_access.3202819646
Directory /workspace/6.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_mem_walk.3220839079
Short name T749
Test name
Test status
Simulation time 462324481 ps
CPU time 5.4 seconds
Started Feb 25 02:46:00 PM PST 24
Finished Feb 25 02:46:06 PM PST 24
Peak memory 202564 kb
Host smart-3ddebc6e-7c2f-4391-bc26-e4a15b2acf89
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220839079 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl
_mem_walk.3220839079
Directory /workspace/6.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/6.sram_ctrl_multiple_keys.329136410
Short name T127
Test name
Test status
Simulation time 3463379272 ps
CPU time 1268.35 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 03:07:10 PM PST 24
Peak memory 371400 kb
Host smart-da3014ac-a824-492a-8e77-67f80180b1ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329136410 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multi
ple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_multipl
e_keys.329136410
Directory /workspace/6.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access.1419630572
Short name T267
Test name
Test status
Simulation time 1319891881 ps
CPU time 131.72 seconds
Started Feb 25 02:46:06 PM PST 24
Finished Feb 25 02:48:18 PM PST 24
Peak memory 373088 kb
Host smart-990a0d19-3717-4f9e-934e-5b8e88998559
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419630572 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.s
ram_ctrl_partial_access.1419630572
Directory /workspace/6.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2106942029
Short name T805
Test name
Test status
Simulation time 34764485701 ps
CPU time 212.46 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 02:49:34 PM PST 24
Peak memory 202656 kb
Host smart-b13433be-0973-405d-8ca1-cb0b3f6f1a63
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106942029 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 6.sram_ctrl_partial_access_b2b.2106942029
Directory /workspace/6.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/6.sram_ctrl_ram_cfg.2142579709
Short name T496
Test name
Test status
Simulation time 50830034 ps
CPU time 1.12 seconds
Started Feb 25 02:45:58 PM PST 24
Finished Feb 25 02:46:00 PM PST 24
Peak memory 202832 kb
Host smart-711004c3-3078-44e1-9c08-0dda78bbb7bd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142579709 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_ram_cfg.2142579709
Directory /workspace/6.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/6.sram_ctrl_regwen.3077518976
Short name T691
Test name
Test status
Simulation time 19332959089 ps
CPU time 975.72 seconds
Started Feb 25 02:46:00 PM PST 24
Finished Feb 25 03:02:16 PM PST 24
Peak memory 374556 kb
Host smart-fea3a415-0e13-4636-8e47-c369d0141ce9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077518976 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_regwen.3077518976
Directory /workspace/6.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/6.sram_ctrl_smoke.2124710671
Short name T771
Test name
Test status
Simulation time 1058372376 ps
CPU time 165.58 seconds
Started Feb 25 02:46:00 PM PST 24
Finished Feb 25 02:48:45 PM PST 24
Peak memory 372528 kb
Host smart-867df21c-731f-4b81-8754-656f973b7bdd
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124710671 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sram_ctrl_smoke.2124710671
Directory /workspace/6.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_all.13968326
Short name T670
Test name
Test status
Simulation time 206687853170 ps
CPU time 1998.38 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 03:19:20 PM PST 24
Peak memory 371380 kb
Host smart-bdcf6ec8-2315-436b-927c-eb9fce763a0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13968326 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +
UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm
_name 6.sram_ctrl_stress_all.13968326
Directory /workspace/6.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2450515914
Short name T791
Test name
Test status
Simulation time 14290907258 ps
CPU time 327.71 seconds
Started Feb 25 02:46:07 PM PST 24
Finished Feb 25 02:51:35 PM PST 24
Peak memory 202696 kb
Host smart-d89e40e9-76e9-48fb-8352-1d253032ab97
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450515914 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.sram_ctrl_stress_pipeline.2450515914
Directory /workspace/6.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4075648674
Short name T796
Test name
Test status
Simulation time 285032299 ps
CPU time 125.34 seconds
Started Feb 25 02:46:08 PM PST 24
Finished Feb 25 02:48:13 PM PST 24
Peak memory 356928 kb
Host smart-471aed77-0a0d-425d-b372-7f80ecd41e9c
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075648674 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sram_ctrl_throughput_w_partial_write.4075648674
Directory /workspace/6.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3835649659
Short name T735
Test name
Test status
Simulation time 3542135581 ps
CPU time 874.5 seconds
Started Feb 25 02:46:03 PM PST 24
Finished Feb 25 03:00:37 PM PST 24
Peak memory 373400 kb
Host smart-e5d3be8e-508f-4673-87a9-9e840b2daa35
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835649659 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 7.sram_ctrl_access_during_key_req.3835649659
Directory /workspace/7.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/7.sram_ctrl_alert_test.2058422031
Short name T206
Test name
Test status
Simulation time 76617461 ps
CPU time 0.67 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 02:46:02 PM PST 24
Peak memory 201500 kb
Host smart-5d200b2d-3cdf-45c1-80a1-e76c1f93c147
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058422031 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.sram_ctrl_alert_test.2058422031
Directory /workspace/7.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sram_ctrl_bijection.4178554086
Short name T413
Test name
Test status
Simulation time 1565281540 ps
CPU time 16.54 seconds
Started Feb 25 02:46:00 PM PST 24
Finished Feb 25 02:46:17 PM PST 24
Peak memory 202604 kb
Host smart-2189403d-d14d-4943-b45d-29e16a8b824b
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178554086 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_bijection.
4178554086
Directory /workspace/7.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/7.sram_ctrl_executable.939117235
Short name T115
Test name
Test status
Simulation time 5144594354 ps
CPU time 275.12 seconds
Started Feb 25 02:46:00 PM PST 24
Finished Feb 25 02:50:35 PM PST 24
Peak memory 372372 kb
Host smart-4da735c0-66ca-4799-98e4-213cb5cf91f0
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939117235 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_execu
table_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_executable
.939117235
Directory /workspace/7.sram_ctrl_executable/latest

Test location /workspace/coverage/default/7.sram_ctrl_lc_escalation.1181608383
Short name T845
Test name
Test status
Simulation time 228211406 ps
CPU time 6.33 seconds
Started Feb 25 02:46:00 PM PST 24
Finished Feb 25 02:46:07 PM PST 24
Peak memory 202648 kb
Host smart-29f7a681-bad8-4d17-b4ec-d70917a3d7a3
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181608383 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_e
scalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_lc_esc
alation.1181608383
Directory /workspace/7.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/7.sram_ctrl_max_throughput.3301275722
Short name T7
Test name
Test status
Simulation time 136163801 ps
CPU time 153.26 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 02:48:35 PM PST 24
Peak memory 366648 kb
Host smart-e112665c-d92b-4928-ae2b-363d5b1c6fb2
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301275722 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_max_throughput.3301275722
Directory /workspace/7.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1015109943
Short name T475
Test name
Test status
Simulation time 272889800 ps
CPU time 2.82 seconds
Started Feb 25 02:46:16 PM PST 24
Finished Feb 25 02:46:19 PM PST 24
Peak memory 211868 kb
Host smart-88eb5566-23af-483c-acc7-051634352038
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015109943 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_mem_partial_access.1015109943
Directory /workspace/7.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_mem_walk.1806996825
Short name T356
Test name
Test status
Simulation time 277761879 ps
CPU time 8.47 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 02:46:10 PM PST 24
Peak memory 202540 kb
Host smart-5177c709-e243-41b7-9b4d-abd908a6e142
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806996825 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl
_mem_walk.1806996825
Directory /workspace/7.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/7.sram_ctrl_multiple_keys.3723551350
Short name T592
Test name
Test status
Simulation time 2858683845 ps
CPU time 932.32 seconds
Started Feb 25 02:45:59 PM PST 24
Finished Feb 25 03:01:31 PM PST 24
Peak memory 368608 kb
Host smart-761a0d0d-945c-4a9b-8b3a-e54c52f935dc
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723551350 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_multip
le_keys.3723551350
Directory /workspace/7.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access.2093957250
Short name T331
Test name
Test status
Simulation time 4014165148 ps
CPU time 119.14 seconds
Started Feb 25 02:46:00 PM PST 24
Finished Feb 25 02:47:59 PM PST 24
Peak memory 373192 kb
Host smart-0f1f8b16-c200-40dc-a387-d8339966eb7a
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093957250 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.s
ram_ctrl_partial_access.2093957250
Directory /workspace/7.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1113771045
Short name T301
Test name
Test status
Simulation time 13516838866 ps
CPU time 246.5 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 02:50:07 PM PST 24
Peak memory 202688 kb
Host smart-5228176a-c7a6-4190-986d-b51769cec660
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113771045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 7.sram_ctrl_partial_access_b2b.1113771045
Directory /workspace/7.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/7.sram_ctrl_ram_cfg.3613266555
Short name T255
Test name
Test status
Simulation time 86380395 ps
CPU time 0.8 seconds
Started Feb 25 02:46:04 PM PST 24
Finished Feb 25 02:46:05 PM PST 24
Peak memory 202652 kb
Host smart-ffc89922-3006-4c8d-89f3-a19316c783ef
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613266555 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_ram_cfg.3613266555
Directory /workspace/7.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/7.sram_ctrl_regwen.782264228
Short name T246
Test name
Test status
Simulation time 11363499994 ps
CPU time 720.13 seconds
Started Feb 25 02:46:07 PM PST 24
Finished Feb 25 02:58:07 PM PST 24
Peak memory 362176 kb
Host smart-e171d252-4090-47ff-bfd1-4c7f848a9537
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782264228 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwe
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_regwen.782264228
Directory /workspace/7.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/7.sram_ctrl_smoke.76107121
Short name T308
Test name
Test status
Simulation time 2658065941 ps
CPU time 143.52 seconds
Started Feb 25 02:46:02 PM PST 24
Finished Feb 25 02:48:26 PM PST 24
Peak memory 369140 kb
Host smart-6746911b-5cee-443a-a56a-1e4a58d4a19f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76107121 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sram_ctrl_smoke.76107121
Directory /workspace/7.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_all.2134172339
Short name T236
Test name
Test status
Simulation time 11829639120 ps
CPU time 2330.99 seconds
Started Feb 25 02:46:16 PM PST 24
Finished Feb 25 03:25:08 PM PST 24
Peak memory 383348 kb
Host smart-392a9944-6ca4-4e2d-b77b-74f038a950bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134172339 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 7.sram_ctrl_stress_all.2134172339
Directory /workspace/7.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1131867388
Short name T399
Test name
Test status
Simulation time 35687159888 ps
CPU time 217.01 seconds
Started Feb 25 02:46:02 PM PST 24
Finished Feb 25 02:49:39 PM PST 24
Peak memory 202672 kb
Host smart-b09792d6-e115-4499-906f-0b22740419ac
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131867388 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.sram_ctrl_stress_pipeline.1131867388
Directory /workspace/7.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.920994316
Short name T214
Test name
Test status
Simulation time 124694914 ps
CPU time 48.01 seconds
Started Feb 25 02:46:00 PM PST 24
Finished Feb 25 02:46:48 PM PST 24
Peak memory 314380 kb
Host smart-5dd06bdb-f3de-4d73-aba7-1a98cb9bd172
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920994316 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 7.sram_ctrl_throughput_w_partial_write.920994316
Directory /workspace/7.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/8.sram_ctrl_access_during_key_req.4062937428
Short name T17
Test name
Test status
Simulation time 127934467 ps
CPU time 36.52 seconds
Started Feb 25 02:46:09 PM PST 24
Finished Feb 25 02:46:46 PM PST 24
Peak memory 285184 kb
Host smart-1082847b-7505-4ae5-8983-d13fff64c38e
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062937428 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 8.sram_ctrl_access_during_key_req.4062937428
Directory /workspace/8.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/8.sram_ctrl_alert_test.2647652329
Short name T617
Test name
Test status
Simulation time 41721767 ps
CPU time 0.66 seconds
Started Feb 25 02:46:26 PM PST 24
Finished Feb 25 02:46:27 PM PST 24
Peak memory 202428 kb
Host smart-f181efc9-e37f-4410-a9ef-157d133c86f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647652329 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.sram_ctrl_alert_test.2647652329
Directory /workspace/8.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sram_ctrl_bijection.1665536968
Short name T867
Test name
Test status
Simulation time 3892809377 ps
CPU time 42.39 seconds
Started Feb 25 02:46:17 PM PST 24
Finished Feb 25 02:46:59 PM PST 24
Peak memory 202604 kb
Host smart-5f04bbf1-f06d-463e-82f1-3c1eda9fac9f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665536968 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_bijection.
1665536968
Directory /workspace/8.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/8.sram_ctrl_executable.1373485845
Short name T13
Test name
Test status
Simulation time 10624002415 ps
CPU time 1121.21 seconds
Started Feb 25 02:46:12 PM PST 24
Finished Feb 25 03:04:53 PM PST 24
Peak memory 371324 kb
Host smart-c500b231-5121-484c-b03e-f9fa6e0e98ae
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373485845 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_executabl
e.1373485845
Directory /workspace/8.sram_ctrl_executable/latest

Test location /workspace/coverage/default/8.sram_ctrl_max_throughput.896865363
Short name T568
Test name
Test status
Simulation time 158959500 ps
CPU time 18.63 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 02:46:20 PM PST 24
Peak memory 268012 kb
Host smart-03bbe1b0-45b1-4ce4-a3c7-1f0fe47a0281
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896865363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_ba
se_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.sram_ctrl_max_throughput.896865363
Directory /workspace/8.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3031058045
Short name T635
Test name
Test status
Simulation time 336802283 ps
CPU time 3.23 seconds
Started Feb 25 02:46:10 PM PST 24
Finished Feb 25 02:46:13 PM PST 24
Peak memory 210936 kb
Host smart-b86f0754-18e3-42a8-91a4-11462a6bea83
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031058045 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_mem_partial_access.3031058045
Directory /workspace/8.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_mem_walk.1453856343
Short name T620
Test name
Test status
Simulation time 438309444 ps
CPU time 5.81 seconds
Started Feb 25 02:46:08 PM PST 24
Finished Feb 25 02:46:14 PM PST 24
Peak memory 202568 kb
Host smart-31b7b5ca-7956-48a7-83fa-6d6a14cb910b
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453856343 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl
_mem_walk.1453856343
Directory /workspace/8.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/8.sram_ctrl_multiple_keys.2306753198
Short name T447
Test name
Test status
Simulation time 28036877150 ps
CPU time 1394.11 seconds
Started Feb 25 02:46:00 PM PST 24
Finished Feb 25 03:09:14 PM PST 24
Peak memory 375480 kb
Host smart-2dfc98f3-5814-49cd-8a48-1e29ab9e35a7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306753198 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_multip
le_keys.2306753198
Directory /workspace/8.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access.2049659872
Short name T312
Test name
Test status
Simulation time 94241228 ps
CPU time 3.04 seconds
Started Feb 25 02:46:17 PM PST 24
Finished Feb 25 02:46:20 PM PST 24
Peak memory 208200 kb
Host smart-d85b4559-488b-4228-b2fb-64f4f27cdfa1
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049659872 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.s
ram_ctrl_partial_access.2049659872
Directory /workspace/8.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3440961643
Short name T218
Test name
Test status
Simulation time 22266563456 ps
CPU time 397.93 seconds
Started Feb 25 02:46:00 PM PST 24
Finished Feb 25 02:52:38 PM PST 24
Peak memory 202728 kb
Host smart-2dc89779-9671-48d1-aeba-9d46dcc89396
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440961643 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 8.sram_ctrl_partial_access_b2b.3440961643
Directory /workspace/8.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/8.sram_ctrl_ram_cfg.2248257789
Short name T730
Test name
Test status
Simulation time 29832736 ps
CPU time 0.84 seconds
Started Feb 25 02:46:11 PM PST 24
Finished Feb 25 02:46:12 PM PST 24
Peak memory 202588 kb
Host smart-51e4f64a-483d-4db4-ac94-156fccae6df1
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248257789 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_ram_cfg.2248257789
Directory /workspace/8.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/8.sram_ctrl_regwen.3512697604
Short name T433
Test name
Test status
Simulation time 18156330998 ps
CPU time 1533.14 seconds
Started Feb 25 02:46:19 PM PST 24
Finished Feb 25 03:11:52 PM PST 24
Peak memory 372764 kb
Host smart-29dae3b8-3609-4641-b4ce-5bf6f6f0745f
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512697604 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_regwen.3512697604
Directory /workspace/8.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/8.sram_ctrl_smoke.2604302321
Short name T686
Test name
Test status
Simulation time 639112430 ps
CPU time 13.78 seconds
Started Feb 25 02:46:16 PM PST 24
Finished Feb 25 02:46:30 PM PST 24
Peak memory 202352 kb
Host smart-ec0a5b93-29f0-44a7-ab73-c643cfd05f77
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604302321 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sram_ctrl_smoke.2604302321
Directory /workspace/8.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_all.1572494260
Short name T668
Test name
Test status
Simulation time 19139054643 ps
CPU time 1082.21 seconds
Started Feb 25 02:46:19 PM PST 24
Finished Feb 25 03:04:21 PM PST 24
Peak memory 374344 kb
Host smart-d4900971-c169-4982-8c5f-27960e71a7dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572494260 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 8.sram_ctrl_stress_all.1572494260
Directory /workspace/8.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1143281363
Short name T209
Test name
Test status
Simulation time 2315719051 ps
CPU time 224.69 seconds
Started Feb 25 02:46:01 PM PST 24
Finished Feb 25 02:49:46 PM PST 24
Peak memory 202672 kb
Host smart-d7358385-c4b8-4a38-ad3e-8bd9c63c75d9
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143281363 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.sram_ctrl_stress_pipeline.1143281363
Directory /workspace/8.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2851750994
Short name T131
Test name
Test status
Simulation time 556354408 ps
CPU time 145.06 seconds
Started Feb 25 02:46:11 PM PST 24
Finished Feb 25 02:48:36 PM PST 24
Peak memory 356980 kb
Host smart-f42643e3-b34c-42c0-95d1-cf2b5e7b72ce
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851750994 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sram_ctrl_throughput_w_partial_write.2851750994
Directory /workspace/8.sram_ctrl_throughput_w_partial_write/latest

Test location /workspace/coverage/default/9.sram_ctrl_access_during_key_req.1378107059
Short name T474
Test name
Test status
Simulation time 2655822607 ps
CPU time 862.98 seconds
Started Feb 25 02:46:11 PM PST 24
Finished Feb 25 03:00:35 PM PST 24
Peak memory 369344 kb
Host smart-9b7103c4-a535-4711-beb4-30274c188426
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378107059 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_access_during_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_
name 9.sram_ctrl_access_during_key_req.1378107059
Directory /workspace/9.sram_ctrl_access_during_key_req/latest

Test location /workspace/coverage/default/9.sram_ctrl_alert_test.1204418360
Short name T426
Test name
Test status
Simulation time 53209310 ps
CPU time 0.66 seconds
Started Feb 25 02:46:07 PM PST 24
Finished Feb 25 02:46:08 PM PST 24
Peak memory 202480 kb
Host smart-ad1d4be5-933b-441f-8c7c-5f8bbb00fe90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204418360 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +U
VM_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.sram_ctrl_alert_test.1204418360
Directory /workspace/9.sram_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sram_ctrl_bijection.1320423575
Short name T125
Test name
Test status
Simulation time 21612507454 ps
CPU time 90.73 seconds
Started Feb 25 02:46:19 PM PST 24
Finished Feb 25 02:47:50 PM PST 24
Peak memory 202652 kb
Host smart-5bbcdcb4-9560-4c60-a7cf-0c8e0e4d1cd5
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320423575 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bije
ction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_bijection.
1320423575
Directory /workspace/9.sram_ctrl_bijection/latest

Test location /workspace/coverage/default/9.sram_ctrl_executable.1947531655
Short name T50
Test name
Test status
Simulation time 13241759438 ps
CPU time 845.26 seconds
Started Feb 25 02:46:27 PM PST 24
Finished Feb 25 03:00:33 PM PST 24
Peak memory 368128 kb
Host smart-9c210c36-c190-43d4-a32b-c63e2c53a5c8
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947531655 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_exec
utable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_executabl
e.1947531655
Directory /workspace/9.sram_ctrl_executable/latest

Test location /workspace/coverage/default/9.sram_ctrl_lc_escalation.163385004
Short name T453
Test name
Test status
Simulation time 826944048 ps
CPU time 8.41 seconds
Started Feb 25 02:46:18 PM PST 24
Finished Feb 25 02:46:26 PM PST 24
Peak memory 210864 kb
Host smart-e6972cea-d6e8-458c-874e-01d74e9eb446
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163385004 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_es
calation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_lc_esca
lation.163385004
Directory /workspace/9.sram_ctrl_lc_escalation/latest

Test location /workspace/coverage/default/9.sram_ctrl_max_throughput.3097619441
Short name T452
Test name
Test status
Simulation time 411420430 ps
CPU time 59.76 seconds
Started Feb 25 02:46:14 PM PST 24
Finished Feb 25 02:47:14 PM PST 24
Peak memory 314100 kb
Host smart-ac27fe1a-f6a3-41b9-831a-436d9d2eab85
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT
Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097619441 -assert nopostproc +UVM_TESTNAME=sram_ctrl_b
ase_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de
v/null -cm_name 9.sram_ctrl_max_throughput.3097619441
Directory /workspace/9.sram_ctrl_max_throughput/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_partial_access.4218123661
Short name T713
Test name
Test status
Simulation time 665410962 ps
CPU time 5.36 seconds
Started Feb 25 02:46:27 PM PST 24
Finished Feb 25 02:46:33 PM PST 24
Peak memory 218936 kb
Host smart-196c5abb-2e5b-448d-bdf0-f7255c8fc008
User root
Command /workspace/default/simv +run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218123661 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM
_TEST_SEQ=sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_mem_partial_access.4218123661
Directory /workspace/9.sram_ctrl_mem_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_mem_walk.4251777290
Short name T379
Test name
Test status
Simulation time 1057897753 ps
CPU time 5.44 seconds
Started Feb 25 02:46:15 PM PST 24
Finished Feb 25 02:46:20 PM PST 24
Peak memory 201804 kb
Host smart-fbda901f-d0e0-4b46-ad76-cbd4525161ef
User root
Command /workspace/default/simv +csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251777290 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=
sram_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl
_mem_walk.4251777290
Directory /workspace/9.sram_ctrl_mem_walk/latest

Test location /workspace/coverage/default/9.sram_ctrl_multiple_keys.1233468242
Short name T872
Test name
Test status
Simulation time 3346682591 ps
CPU time 885.53 seconds
Started Feb 25 02:46:04 PM PST 24
Finished Feb 25 03:00:50 PM PST 24
Peak memory 364960 kb
Host smart-380e6ffd-3dcb-46a5-ac62-440db72b9a74
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233468242 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mult
iple_keys_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_multip
le_keys.1233468242
Directory /workspace/9.sram_ctrl_multiple_keys/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access.376096918
Short name T671
Test name
Test status
Simulation time 2865052625 ps
CPU time 14.05 seconds
Started Feb 25 02:46:18 PM PST 24
Finished Feb 25 02:46:32 PM PST 24
Peak memory 202784 kb
Host smart-e50d7924-fae4-4fe3-9adf-01d2f1d7bf19
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376096918 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_T
EST_SEQ=sram_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sr
am_ctrl_partial_access.376096918
Directory /workspace/9.sram_ctrl_partial_access/latest

Test location /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2847435074
Short name T195
Test name
Test status
Simulation time 4845090713 ps
CPU time 82.31 seconds
Started Feb 25 02:46:14 PM PST 24
Finished Feb 25 02:47:36 PM PST 24
Peak memory 202636 kb
Host smart-db778476-7692-478b-a679-09bfe9c156d2
User root
Command /workspace/default/simv +partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847435074 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_
TEST_SEQ=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c
m_name 9.sram_ctrl_partial_access_b2b.2847435074
Directory /workspace/9.sram_ctrl_partial_access_b2b/latest

Test location /workspace/coverage/default/9.sram_ctrl_ram_cfg.3655339496
Short name T674
Test name
Test status
Simulation time 79175187 ps
CPU time 1.11 seconds
Started Feb 25 02:46:06 PM PST 24
Finished Feb 25 02:46:08 PM PST 24
Peak memory 202832 kb
Host smart-77a3f7c5-3e84-446f-bbe6-41b55543bbe7
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655339496 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_
cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_ram_cfg.3655339496
Directory /workspace/9.sram_ctrl_ram_cfg/latest

Test location /workspace/coverage/default/9.sram_ctrl_regwen.2775456370
Short name T334
Test name
Test status
Simulation time 8170643050 ps
CPU time 729.15 seconds
Started Feb 25 02:46:27 PM PST 24
Finished Feb 25 02:58:37 PM PST 24
Peak memory 375464 kb
Host smart-decf21da-241c-45d0-ac5c-429ca4178a08
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775456370 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regw
en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_regwen.2775456370
Directory /workspace/9.sram_ctrl_regwen/latest

Test location /workspace/coverage/default/9.sram_ctrl_smoke.3260788194
Short name T811
Test name
Test status
Simulation time 2366441988 ps
CPU time 14.95 seconds
Started Feb 25 02:46:10 PM PST 24
Finished Feb 25 02:46:26 PM PST 24
Peak memory 202612 kb
Host smart-e0b94e6a-3fdb-4de9-8196-539c56ecf5e9
User root
Command /workspace/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260788194 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smok
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sram_ctrl_smoke.3260788194
Directory /workspace/9.sram_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_all.2747761919
Short name T892
Test name
Test status
Simulation time 271080737242 ps
CPU time 4853.96 seconds
Started Feb 25 02:46:15 PM PST 24
Finished Feb 25 04:07:09 PM PST 24
Peak memory 374532 kb
Host smart-7cad2793-1708-486b-a6ac-56a8cbca5c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747761919 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test
+UVM_TEST_SEQ=sram_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -
cm_name 9.sram_ctrl_stress_all.2747761919
Directory /workspace/9.sram_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3534535120
Short name T98
Test name
Test status
Simulation time 11575752209 ps
CPU time 195.95 seconds
Started Feb 25 02:46:12 PM PST 24
Finished Feb 25 02:49:29 PM PST 24
Peak memory 202712 kb
Host smart-38b6e674-dea5-4356-86ed-7847e135eb99
User root
Command /workspace/default/simv +zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u
cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534535120 -assert nopostproc +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ
=sram_ctrl_stress_pipeline_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.sram_ctrl_stress_pipeline.3534535120
Directory /workspace/9.sram_ctrl_stress_pipeline/latest

Test location /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2857905170
Short name T128
Test name
Test status
Simulation time 218718163 ps
CPU time 28.24 seconds
Started Feb 25 02:46:07 PM PST 24
Finished Feb 25 02:46:36 PM PST 24
Peak memory 278296 kb
Host smart-85f8f42b-ee81-4f49-a632-3b9831d733aa
User root
Command /workspace/default/simv +zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857905170 -assert nopostproc +UVM_TESTNAME=sram_ctrl_
base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sram_ctrl_throughput_w_partial_write.2857905170
Directory /workspace/9.sram_ctrl_throughput_w_partial_write/latest
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