Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14579316	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

61089083

1

T1

145112

T2

32768

T3

3714

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37782920	1			T1	79568		T2	16384		T3	2069
values[0x0]	17482555	1			T1	38644		T2	8159		T3	986
values[0x1]	20402924	1			T1	41327		T2	8225		T3	1022

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7265253	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

68403146

1

T1

152388

T2

32768

T3

3901

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	300646	1			T1	624		T3	2		T4	8
valid_sources[0x01]	355031	1			T1	593		T2	32768		T3	15
valid_sources[0x02]	328794	1			T1	614		T3	5		T4	4
valid_sources[0x03]	287554	1			T1	617		T3	28		T4	19
valid_sources[0x04]	327372	1			T1	621		T3	10		T4	15
valid_sources[0x05]	285620	1			T1	675		T3	7		T4	7
valid_sources[0x06]	283864	1			T1	513		T3	9		T4	10
valid_sources[0x07]	255944	1			T1	571		T3	26		T4	10
valid_sources[0x08]	293485	1			T1	620		T3	13		T4	10
valid_sources[0x09]	263286	1			T1	662		T3	4		T4	26
valid_sources[0x0a]	260108	1			T1	631		T3	14		T4	6
valid_sources[0x0b]	277503	1			T1	666		T3	28		T4	8
valid_sources[0x0c]	321964	1			T1	638		T3	3		T4	6
valid_sources[0x0d]	307362	1			T1	622		T3	22		T4	6
valid_sources[0x0e]	249102	1			T1	630		T3	17		T4	16
valid_sources[0x0f]	350525	1			T1	696		T3	16		T4	16
valid_sources[0x10]	281965	1			T1	617		T3	18		T4	4
valid_sources[0x11]	283169	1			T1	652		T3	13		T4	10
valid_sources[0x12]	273340	1			T1	576		T3	30		T4	19
valid_sources[0x13]	316750	1			T1	623		T3	15		T4	21
valid_sources[0x14]	313409	1			T1	648		T3	6		T4	11
valid_sources[0x15]	267135	1			T1	582		T3	8		T4	7
valid_sources[0x16]	370067	1			T1	622		T3	7		T4	9
valid_sources[0x17]	293891	1			T1	590		T3	18		T4	11
valid_sources[0x18]	280845	1			T1	625		T3	9		T4	11
valid_sources[0x19]	277831	1			T1	629		T3	5		T4	8
valid_sources[0x1a]	269910	1			T1	625		T3	41		T4	20
valid_sources[0x1b]	304978	1			T1	547		T3	6		T4	10
valid_sources[0x1c]	257391	1			T1	651		T3	22		T4	7
valid_sources[0x1d]	319658	1			T1	648		T3	14		T4	15
valid_sources[0x1e]	333174	1			T1	631		T3	12		T4	10
valid_sources[0x1f]	280192	1			T1	644		T3	53		T4	9
valid_sources[0x20]	264507	1			T1	569		T3	5		T4	8
valid_sources[0x21]	329318	1			T1	598		T3	11		T4	4
valid_sources[0x22]	296191	1			T1	609		T3	23		T4	5
valid_sources[0x23]	272646	1			T1	636		T3	34		T4	12
valid_sources[0x24]	273749	1			T1	626		T3	4		T4	13
valid_sources[0x25]	255497	1			T1	620		T3	3		T4	7
valid_sources[0x26]	265399	1			T1	593		T3	5		T4	11
valid_sources[0x27]	259960	1			T1	633		T3	11		T4	22
valid_sources[0x28]	276391	1			T1	625		T3	11		T4	13
valid_sources[0x29]	324572	1			T1	652		T3	16		T4	11
valid_sources[0x2a]	268644	1			T1	670		T3	21		T4	14
valid_sources[0x2b]	396757	1			T1	604		T3	8		T4	16
valid_sources[0x2c]	310277	1			T1	631		T3	35		T4	4
valid_sources[0x2d]	310204	1			T1	615		T3	4		T4	1
valid_sources[0x2e]	257187	1			T1	601		T3	8		T4	9
valid_sources[0x2f]	289086	1			T1	645		T3	17		T4	4
valid_sources[0x30]	385119	1			T1	645		T3	13		T4	5
valid_sources[0x31]	295102	1			T1	645		T3	12		T4	5
valid_sources[0x32]	291742	1			T1	595		T3	3		T4	5
valid_sources[0x33]	289715	1			T1	629		T3	20		T4	15
valid_sources[0x34]	279659	1			T1	674		T3	30		T4	7
valid_sources[0x35]	297526	1			T1	634		T3	33		T4	3
valid_sources[0x36]	256134	1			T1	625		T3	6		T4	6
valid_sources[0x37]	270845	1			T1	592		T3	16		T4	14
valid_sources[0x38]	311379	1			T1	701		T3	19		T4	6
valid_sources[0x39]	252318	1			T1	576		T3	12		T4	14
valid_sources[0x3a]	390187	1			T1	636		T3	21		T4	11
valid_sources[0x3b]	273738	1			T1	629		T3	5		T4	13
valid_sources[0x3c]	335679	1			T1	652		T3	11		T4	10
valid_sources[0x3d]	364285	1			T1	603		T3	11		T4	17
valid_sources[0x3e]	312698	1			T1	595		T3	8		T4	17
valid_sources[0x3f]	271985	1			T1	646		T3	9		T4	21
valid_sources[0x40]	283245	1			T1	627		T3	7		T4	7
valid_sources[0x41]	267927	1			T1	648		T3	15		T4	14
valid_sources[0x42]	285940	1			T1	623		T3	11		T4	5
valid_sources[0x43]	256131	1			T1	635		T3	11		T4	18
valid_sources[0x44]	317827	1			T1	671		T3	6		T4	9
valid_sources[0x45]	277602	1			T1	625		T3	18		T4	6
valid_sources[0x46]	247410	1			T1	622		T3	18		T4	4
valid_sources[0x47]	256053	1			T1	686		T3	16		T4	9
valid_sources[0x48]	300647	1			T1	672		T3	4		T4	2
valid_sources[0x49]	263969	1			T1	635		T3	19		T4	6
valid_sources[0x4a]	273483	1			T1	570		T3	32		T4	12
valid_sources[0x4b]	304279	1			T1	682		T3	37		T4	13
valid_sources[0x4c]	293888	1			T1	687		T3	17		T4	4
valid_sources[0x4d]	310484	1			T1	621		T3	18		T4	17
valid_sources[0x4e]	284566	1			T1	621		T3	14		T4	16
valid_sources[0x4f]	375892	1			T1	585		T3	26		T4	10
valid_sources[0x50]	308426	1			T1	626		T3	5		T4	12
valid_sources[0x51]	279289	1			T1	638		T3	18		T4	6
valid_sources[0x52]	247450	1			T1	587		T3	18		T4	8
valid_sources[0x53]	403782	1			T1	591		T3	12		T4	13
valid_sources[0x54]	340826	1			T1	610		T3	22		T4	6
valid_sources[0x55]	262945	1			T1	597		T3	8		T4	12
valid_sources[0x56]	303214	1			T1	613		T3	16		T4	3
valid_sources[0x57]	307578	1			T1	586		T3	7		T4	9
valid_sources[0x58]	286145	1			T1	643		T3	25		T4	9
valid_sources[0x59]	327910	1			T1	631		T3	25		T4	11
valid_sources[0x5a]	399545	1			T1	649		T3	16		T4	9
valid_sources[0x5b]	284524	1			T1	646		T3	10		T4	5
valid_sources[0x5c]	263330	1			T1	553		T3	29		T4	8
valid_sources[0x5d]	318962	1			T1	665		T3	14		T4	9
valid_sources[0x5e]	268819	1			T1	659		T3	9		T4	11
valid_sources[0x5f]	295200	1			T1	623		T3	11		T4	17
valid_sources[0x60]	333826	1			T1	601		T3	5		T4	11
valid_sources[0x61]	386127	1			T1	637		T3	6		T4	8
valid_sources[0x62]	300317	1			T1	640		T3	20		T4	7
valid_sources[0x63]	300350	1			T1	707		T3	3		T4	6
valid_sources[0x64]	297508	1			T1	694		T3	3		T4	21
valid_sources[0x65]	255352	1			T1	643		T3	4		T4	16
valid_sources[0x66]	262340	1			T1	630		T3	24		T4	19
valid_sources[0x67]	251178	1			T1	584		T3	29		T4	6
valid_sources[0x68]	252241	1			T1	607		T3	11		T4	19
valid_sources[0x69]	265886	1			T1	610		T3	15		T4	12
valid_sources[0x6a]	306284	1			T1	628		T3	16		T4	15
valid_sources[0x6b]	256226	1			T1	697		T3	18		T4	21
valid_sources[0x6c]	276955	1			T1	605		T3	20		T4	9
valid_sources[0x6d]	297364	1			T1	638		T3	23		T4	5
valid_sources[0x6e]	274187	1			T1	590		T3	16		T4	18
valid_sources[0x6f]	301689	1			T1	608		T3	9		T4	10
valid_sources[0x70]	290526	1			T1	588		T3	7		T4	4
valid_sources[0x71]	274016	1			T1	604		T3	10		T4	10
valid_sources[0x72]	293715	1			T1	640		T3	25		T4	7
valid_sources[0x73]	361338	1			T1	642		T3	28		T4	3
valid_sources[0x74]	298478	1			T1	704		T3	4		T4	20
valid_sources[0x75]	299765	1			T1	552		T3	22		T4	20
valid_sources[0x76]	357804	1			T1	622		T3	22		T4	8
valid_sources[0x77]	262595	1			T1	695		T3	31		T4	13
valid_sources[0x78]	266077	1			T1	668		T3	7		T4	7
valid_sources[0x79]	285506	1			T1	602		T3	23		T4	11
valid_sources[0x7a]	267889	1			T1	667		T3	19		T4	6
valid_sources[0x7b]	287714	1			T1	624		T3	29		T4	11
valid_sources[0x7c]	260139	1			T1	629		T3	28		T4	16
valid_sources[0x7d]	352132	1			T1	587		T3	6		T4	4
valid_sources[0x7e]	284167	1			T1	619		T3	9		T4	6
valid_sources[0x7f]	260982	1			T1	580		T3	20		T4	17
valid_sources[0x80]	289333	1			T1	589		T3	10		T4	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

30499279

1

T1

72458

T2

16384

T3

1890

values[0x0]

all_enables

biggest_size

15293008

1

T1

36402

T2

8159

T3

921

values[0x1]

all_enables

biggest_size

15296796

1

T1

36252

T2

8225

T3

903

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2183694	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

18518

1

T1

2

T2

3

T3

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2173333	1			T1	8348		T2	393		T3	12089
values[0x0]	14246	1			T1	6		T2	7		T3	17
values[0x1]	14633	1			T1	10		T2	9		T3	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1459487	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

742725

1

T1

2749

T2

129

T3

4022

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6761	1			T1	40		T3	50		T4	10
valid_sources[0x01]	8365	1			T1	25		T3	33		T4	14
valid_sources[0x02]	7502	1			T1	34		T3	42		T4	7
valid_sources[0x03]	6827	1			T1	30		T3	42		T4	11
valid_sources[0x04]	7622	1			T1	30		T3	33		T4	4
valid_sources[0x05]	9719	1			T1	33		T3	29		T4	9
valid_sources[0x06]	6496	1			T1	39		T3	48		T4	9
valid_sources[0x07]	9227	1			T1	20		T3	39		T4	7
valid_sources[0x08]	6354	1			T1	38		T3	62		T4	12
valid_sources[0x09]	7093	1			T1	40		T3	62		T4	10
valid_sources[0x0a]	6921	1			T1	29		T3	52		T4	14
valid_sources[0x0b]	17043	1			T1	28		T3	62		T4	17
valid_sources[0x0c]	7026	1			T1	38		T3	38		T4	15
valid_sources[0x0d]	11750	1			T1	43		T3	57		T4	3
valid_sources[0x0e]	6447	1			T1	44		T3	49		T4	7
valid_sources[0x0f]	6160	1			T1	26		T3	52		T4	9
valid_sources[0x10]	8153	1			T1	33		T3	41		T4	5
valid_sources[0x11]	7143	1			T1	32		T3	38		T4	17
valid_sources[0x12]	6865	1			T1	31		T3	57		T4	10
valid_sources[0x13]	6125	1			T1	29		T3	43		T4	6
valid_sources[0x14]	7599	1			T1	32		T3	38		T4	6
valid_sources[0x15]	9779	1			T1	50		T3	59		T4	11
valid_sources[0x16]	7677	1			T1	31		T3	53		T4	9
valid_sources[0x17]	6716	1			T1	43		T3	31		T4	14
valid_sources[0x18]	6023	1			T1	28		T3	41		T4	9
valid_sources[0x19]	6409	1			T1	23		T3	45		T4	7
valid_sources[0x1a]	14621	1			T1	22		T3	45		T4	16
valid_sources[0x1b]	6288	1			T1	30		T3	68		T4	4
valid_sources[0x1c]	10475	1			T1	39		T3	74		T4	13
valid_sources[0x1d]	8429	1			T1	35		T3	52		T4	11
valid_sources[0x1e]	13122	1			T1	24		T3	46		T4	20
valid_sources[0x1f]	7763	1			T1	30		T3	51		T4	11
valid_sources[0x20]	8481	1			T1	37		T3	56		T4	15
valid_sources[0x21]	6599	1			T1	38		T3	59		T4	11
valid_sources[0x22]	6289	1			T1	36		T3	32		T4	5
valid_sources[0x23]	45711	1			T1	37		T3	62		T4	11
valid_sources[0x24]	6688	1			T1	33		T3	51		T4	2
valid_sources[0x25]	6717	1			T1	22		T3	50		T4	4
valid_sources[0x26]	6879	1			T1	30		T3	76		T4	8
valid_sources[0x27]	6782	1			T1	33		T3	27		T4	7
valid_sources[0x28]	6882	1			T1	37		T3	57		T4	18
valid_sources[0x29]	8721	1			T1	33		T3	42		T4	12
valid_sources[0x2a]	6428	1			T1	34		T3	38		T4	14
valid_sources[0x2b]	6574	1			T1	42		T3	73		T4	15
valid_sources[0x2c]	6082	1			T1	34		T3	57		T4	9
valid_sources[0x2d]	6336	1			T1	30		T3	40		T4	2
valid_sources[0x2e]	6414	1			T1	30		T3	53		T4	6
valid_sources[0x2f]	7550	1			T1	28		T3	49		T4	15
valid_sources[0x30]	6193	1			T1	28		T3	44		T4	13
valid_sources[0x31]	7475	1			T1	36		T3	62		T4	12
valid_sources[0x32]	7833	1			T1	26		T3	63		T4	9
valid_sources[0x33]	15053	1			T1	36		T3	39		T4	8
valid_sources[0x34]	6177	1			T1	38		T3	51		T4	11
valid_sources[0x35]	8893	1			T1	30		T3	61		T4	7
valid_sources[0x36]	7094	1			T1	29		T3	55		T4	9
valid_sources[0x37]	6832	1			T1	35		T3	53		T4	15
valid_sources[0x38]	7474	1			T1	27		T3	39		T4	11
valid_sources[0x39]	13759	1			T1	43		T3	36		T4	8
valid_sources[0x3a]	7084	1			T1	30		T3	56		T4	6
valid_sources[0x3b]	6555	1			T1	32		T3	51		T4	12
valid_sources[0x3c]	6463	1			T1	37		T3	44		T4	13
valid_sources[0x3d]	7205	1			T1	33		T3	37		T4	6
valid_sources[0x3e]	6513	1			T1	35		T3	27		T4	15
valid_sources[0x3f]	6134	1			T1	42		T3	32		T4	12
valid_sources[0x40]	6404	1			T1	33		T3	37		T4	11
valid_sources[0x41]	9080	1			T1	39		T3	47		T4	13
valid_sources[0x42]	6537	1			T1	38		T3	42		T4	12
valid_sources[0x43]	6509	1			T1	32		T3	43		T4	8
valid_sources[0x44]	8036	1			T1	25		T3	59		T4	3
valid_sources[0x45]	7343	1			T1	39		T3	52		T4	7
valid_sources[0x46]	6473	1			T1	37		T3	46		T4	4
valid_sources[0x47]	6410	1			T1	41		T3	56		T4	8
valid_sources[0x48]	6784	1			T1	32		T3	66		T4	15
valid_sources[0x49]	7256	1			T1	53		T3	82		T4	17
valid_sources[0x4a]	6836	1			T1	28		T3	29		T4	7
valid_sources[0x4b]	9542	1			T1	32		T3	52		T4	5
valid_sources[0x4c]	14048	1			T1	31		T3	52		T4	9
valid_sources[0x4d]	6128	1			T1	44		T3	52		T4	15
valid_sources[0x4e]	10183	1			T1	40		T3	33		T4	14
valid_sources[0x4f]	9222	1			T1	24		T3	41		T4	16
valid_sources[0x50]	7046	1			T1	28		T3	53		T4	13
valid_sources[0x51]	17913	1			T1	33		T3	30		T4	6
valid_sources[0x52]	7281	1			T1	37		T3	50		T4	3
valid_sources[0x53]	6081	1			T1	32		T3	45		T4	13
valid_sources[0x54]	6318	1			T1	37		T3	60		T4	7
valid_sources[0x55]	8075	1			T1	37		T3	58		T4	10
valid_sources[0x56]	6628	1			T1	27		T3	45		T4	9
valid_sources[0x57]	6221	1			T1	33		T3	39		T4	8
valid_sources[0x58]	6199	1			T1	27		T3	57		T4	12
valid_sources[0x59]	7166	1			T1	36		T3	33		T4	16
valid_sources[0x5a]	10800	1			T1	23		T3	35		T4	11
valid_sources[0x5b]	6453	1			T1	24		T3	58		T4	14
valid_sources[0x5c]	8775	1			T1	38		T3	44		T4	12
valid_sources[0x5d]	9393	1			T1	33		T3	54		T4	8
valid_sources[0x5e]	6515	1			T1	41		T3	31		T4	13
valid_sources[0x5f]	9170	1			T1	24		T3	36		T4	10
valid_sources[0x60]	6323	1			T1	30		T3	52		T4	12
valid_sources[0x61]	7274	1			T1	35		T3	54		T4	11
valid_sources[0x62]	6829	1			T1	29		T3	39		T4	11
valid_sources[0x63]	10005	1			T1	32		T3	51		T4	7
valid_sources[0x64]	6336	1			T1	34		T3	33		T4	15
valid_sources[0x65]	6355	1			T1	20		T3	37		T4	4
valid_sources[0x66]	6275	1			T1	38		T3	27		T4	6
valid_sources[0x67]	8140	1			T1	34		T3	52		T4	16
valid_sources[0x68]	6183	1			T1	33		T3	29		T4	11
valid_sources[0x69]	7859	1			T1	30		T3	40		T4	15
valid_sources[0x6a]	7835	1			T1	32		T3	42		T4	8
valid_sources[0x6b]	16502	1			T1	27		T3	64		T4	13
valid_sources[0x6c]	8679	1			T1	33		T3	59		T4	5
valid_sources[0x6d]	5952	1			T1	40		T3	22		T4	6
valid_sources[0x6e]	6619	1			T1	34		T3	39		T4	6
valid_sources[0x6f]	6309	1			T1	26		T3	46		T4	10
valid_sources[0x70]	8550	1			T1	27		T3	60		T4	6
valid_sources[0x71]	17195	1			T1	34		T3	44		T4	6
valid_sources[0x72]	8003	1			T1	26		T3	50		T4	6
valid_sources[0x73]	14437	1			T1	31		T3	52		T4	7
valid_sources[0x74]	7301	1			T1	33		T3	61		T4	5
valid_sources[0x75]	8342	1			T1	44		T3	40		T4	7
valid_sources[0x76]	8082	1			T1	28		T3	45		T4	11
valid_sources[0x77]	10087	1			T1	39		T3	47		T4	5
valid_sources[0x78]	11534	1			T1	28		T3	53		T4	11
valid_sources[0x79]	6571	1			T1	26		T3	36		T4	9
valid_sources[0x7a]	6480	1			T1	37		T3	49		T4	11
valid_sources[0x7b]	6269	1			T1	35		T3	55		T4	7
valid_sources[0x7c]	6377	1			T1	44		T3	34		T4	8
valid_sources[0x7d]	18642	1			T1	22		T3	58		T4	6
valid_sources[0x7e]	8270	1			T1	47		T3	59		T4	13
valid_sources[0x7f]	18051	1			T1	37		T3	31		T4	7
valid_sources[0x80]	6215	1			T1	25		T3	34		T4	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7049

1

T3

16

T4

14

T7

4

values[0x0]

all_enables

biggest_size

6718

1

T1

2

T2

3

T3

3

values[0x1]

all_enables

biggest_size

4751

1

T3

3

T4

4

T5

4