Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

14048359

1

T1

14427

T3

141

T4

26

full_word

55655142

1

T1

145112

T2

32768

T3

1437

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	69703201	1			T1	159539		T2	32768		T3	1578
auto[TlIntgErrCmd]	97	1			T27	8		T28	5		T29	2
auto[TlIntgErrData]	97	1			T27	5		T28	2		T29	3
auto[TlIntgErrBoth]	106	1			T27	7		T28	3		T29	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31898859

1

T1

79568

T2

16384

T3

791

auto[1]

37804642

1

T1

79971

T2

16384

T3

787

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6751533	1			T1	7110		T3	69		T4	19
auto[TlIntgErrNone]	partial	auto[1]	7296549	1			T1	7317		T3	72		T4	7
auto[TlIntgErrNone]	full_word	auto[0]	25147203	1			T1	72458		T2	16384		T3	722
auto[TlIntgErrNone]	full_word	auto[1]	30507916	1			T1	72654		T2	16384		T3	715
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T27	3		T28	2		T47	1
auto[TlIntgErrCmd]	partial	auto[1]	54	1			T27	3		T28	1		T29	2
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T27	1		T28	1		T92	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T27	1		T28	1		T95	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T27	2		T28	2		T47	2
auto[TlIntgErrData]	partial	auto[1]	51	1			T27	3		T29	3		T47	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T100	1		T101	2		T102	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T98	1		T96	1		T100	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T27	1		T28	3		T29	2
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T27	5		T29	3		T47	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T101	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T27	1		T98	1		T103	1