Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	828476	1			T5	1585		T9	2017		T11	103
auto[1]	10746761	1			T1	43400		T3	703		T4	4
auto[2]	705746	1			T5	1456		T9	1697		T11	73
auto[3]	10628956	1			T1	43512		T3	719		T4	2

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15212372	1			T1	72563		T3	1189		T4	4
auto[1]	2154676	1			T1	6918		T3	111		T4	1
auto[2]	2152216	1			T1	6801		T3	108		T4	1
auto[3]	3390675	1			T1	630		T3	14		T7	1

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9181918

1

T1

86821

T3

1418

T4

6

auto[1]

13728021

1

T1

91

T3

4

T7

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	291497	1			T5	1324		T9	1656		T63	1
auto[0]	auto[0]	auto[1]	29753	1			T5	127		T9	175		T63	1
auto[0]	auto[0]	auto[2]	29649	1			T5	121		T9	165		T11	2
auto[0]	auto[0]	auto[3]	7787	1			T5	11		T9	20		T11	99
auto[0]	auto[1]	auto[0]	3476649	1			T1	36295		T3	585		T4	4
auto[0]	auto[1]	auto[1]	366500	1			T1	3248		T3	53		T7	8
auto[0]	auto[1]	auto[2]	352177	1			T1	3507		T3	57		T7	22
auto[0]	auto[1]	auto[3]	80831	1			T1	307		T3	6		T5	12
auto[0]	auto[2]	auto[0]	257057	1			T5	1259		T9	1413		T18	2675
auto[0]	auto[2]	auto[1]	26482	1			T5	97		T9	163		T11	5
auto[0]	auto[2]	auto[2]	23474	1			T5	86		T9	109		T62	3
auto[0]	auto[2]	auto[3]	6211	1			T5	13		T9	11		T11	68
auto[0]	auto[3]	auto[0]	3439013	1			T1	36198		T3	601		T7	189
auto[0]	auto[3]	auto[1]	348920	1			T1	3661		T3	58		T4	1
auto[0]	auto[3]	auto[2]	361862	1			T1	3283		T3	50		T4	1
auto[0]	auto[3]	auto[3]	84056	1			T1	322		T3	8		T7	1
auto[1]	auto[0]	auto[0]	15943	1			T5	1		T9	1		T63	829
auto[1]	auto[0]	auto[1]	69522	1			T5	1		T63	3811		T65	2021
auto[1]	auto[0]	auto[2]	70391	1			T63	3957		T65	2078		T85	2672
auto[1]	auto[0]	auto[3]	313934	1			T11	2		T63	17328		T65	9240
auto[1]	auto[1]	auto[0]	3861192	1			T1	36		T3	2		T10	32
auto[1]	auto[1]	auto[1]	648321	1			T1	3		T10	4		T12	1
auto[1]	auto[1]	auto[2]	618797	1			T1	3		T10	2		T63	622
auto[1]	auto[1]	auto[3]	1342294	1			T1	1		T6	1		T63	17407
auto[1]	auto[2]	auto[0]	13168	1			T5	1		T9	1		T63	786
auto[1]	auto[2]	auto[1]	58347	1			T63	3508		T65	1208		T85	2498
auto[1]	auto[2]	auto[2]	58111	1			T63	3224		T65	2214		T85	1757
auto[1]	auto[2]	auto[3]	262896	1			T63	14728		T65	10144		T85	8159
auto[1]	auto[3]	auto[0]	3857853	1			T1	34		T3	1		T7	2
auto[1]	auto[3]	auto[1]	606831	1			T1	6		T10	3		T63	289
auto[1]	auto[3]	auto[2]	637755	1			T1	8		T3	1		T9	1
auto[1]	auto[3]	auto[3]	1292666	1			T63	14864		T62	2		T65	11876