Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.89	100.00	97.78	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	328952913	8704	0	0
ctrl_regwen_rd_A	328952913	2269	0	0
exec_rd_A	328952913	2165	0	0
exec_regwen_rd_A	328952913	1971	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328952913	8704	0	0
T30	10608	382	0	0
T42	12802	471	0	0
T43	13278	474	0	0
T44	14017	593	0	0
T45	4016	748	0	0
T46	2865	247	0	0
T47	17095	4	0	0
T48	10271	550	0	0
T49	9351	537	0	0
T50	2420	411	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328952913	2269	0	0
T28	9071	44	0	0
T43	13278	79	0	0
T44	14017	122	0	0
T51	15668	73	0	0
T53	41673	81	0	0
T56	40680	43	0	0
T61	1426	22	0	0
T66	39813	75	0	0
T89	943	1	0	0
T91	16987	395	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328952913	2165	0	0
T28	9071	47	0	0
T43	13278	106	0	0
T44	14017	92	0	0
T51	15668	100	0	0
T53	41673	76	0	0
T56	40680	46	0	0
T61	1426	13	0	0
T66	39813	62	0	0
T91	16987	442	0	0
T92	9432	35	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	328952913	1971	0	0
T28	9071	56	0	0
T43	13278	56	0	0
T44	14017	89	0	0
T51	15668	72	0	0
T53	41673	85	0	0
T56	40680	35	0	0
T60	970	6	0	0
T61	1426	32	0	0
T89	943	7	0	0
T91	16987	396	0	0