Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	116346624	1			T1	73728		T2	2340		T3	316946
instr_valid_dis	89343994	1			T1	73728		T2	2340		T3	316946
instr_en	18956165	1			T4	92912		T18	486		T23	339144

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9767777	1			T4	112752		T17	5282		T23	163624
sram_ifetch_valid_disable	88285345	1			T1	73728		T2	2340		T3	316946
sram_ifetch_enable	18293502	1			T4	285134		T18	486		T23	48618

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	116346624	1			T1	73728		T2	2340		T3	316946
hw_debug_en_valid_off	89562576	1			T1	73728		T2	2340		T3	316946
hw_debug_en_on	17978813	1			T4	238704		T23	208098		T28	222828

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	88285345	1			T1	73728		T2	2340		T3	316946
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	78141175	1			T1	73728		T2	2340		T3	316946
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7243777	1			T4	24694		T23	126902		T28	67964
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4340003	1			T4	58818		T17	5282		T23	58178
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1882223	1			T4	50018		T17	5282		T24	10112
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1820214	1			T4	8800		T23	58178		T28	10674
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3539098	1			T4	40122		T23	65358		T28	22672
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1666334	1			T4	40122		T58	160852		T135	29110
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1154282	1			T23	65358		T28	22672		T57	20000
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7222407	1			T4	56224		T23	126902		T28	54406
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3079702	1			T4	29706		T28	92		T57	81590
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2926030	1			T4	16136		T23	126902		T28	54314

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7955392	1			T4	58708		T18	486		T23	48618
lc_exec_en	7217308	1			T4	142358		T23	15838		T28	145750
valid_exec_dis	84391927	1			T1	73728		T2	2340		T3	316946
invalid_exec_dis	28061279	1			T4	397886		T17	5282		T18	486