Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	32406002	1			T1	36864		T2	61		T3	144055
triple_byte_access	2251501	1			T2	2		T3	2935		T4	2687
halfword_access	3383139	1			T2	1		T3	4302		T4	3940
byte_access	4522028	1			T2	2		T3	5744		T4	5419
zero_access	1138072	1			T3	1437		T4	1286		T7	74

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21797910

1

T1

18432

T2

41

T3

79190

auto[1]

21902832

1

T1

18432

T2

25

T3

79283

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	16151377	1			T1	18432		T2	39		T3	71963
auto[0]	triple_byte_access	1123853	1			T2	1		T3	1463		T4	1351
auto[0]	halfword_access	1687387	1			T3	2222		T4	1962		T7	118
auto[0]	byte_access	2261730	1			T2	1		T3	2827		T4	2786
auto[0]	zero_access	573563	1			T3	715		T4	619		T7	37
auto[1]	word_access	16254625	1			T1	18432		T2	22		T3	72092
auto[1]	triple_byte_access	1127648	1			T2	1		T3	1472		T4	1336
auto[1]	halfword_access	1695752	1			T2	1		T3	2080		T4	1978
auto[1]	byte_access	2260298	1			T2	1		T3	2917		T4	2633
auto[1]	zero_access	564509	1			T3	722		T4	667		T7	37