Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	13646605	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

57052406

1

T1

360248

T2

259825

T3

337828

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	35246244	1			T1	198314		T2	142889		T3	185233
values[0x0]	16355475	1			T1	95768		T2	68755		T3	88868
values[0x1]	19097292	1			T1	102309		T2	74192		T3	95879

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	6796990	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

63902021

1

T1

378443

T2

272874

T3

354011

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	284026	1			T1	1809		T3	1451		T6	673
valid_sources[0x01]	251030	1			T1	1414		T3	1423		T6	706
valid_sources[0x02]	269446	1			T1	1603		T3	1419		T6	700
valid_sources[0x03]	254538	1			T1	1601		T3	1479		T6	609
valid_sources[0x04]	247781	1			T1	1392		T3	1483		T6	638
valid_sources[0x05]	249555	1			T1	1565		T3	1515		T6	704
valid_sources[0x06]	249682	1			T1	1313		T3	1385		T6	750
valid_sources[0x07]	255586	1			T1	1617		T3	1502		T6	672
valid_sources[0x08]	248976	1			T1	1631		T3	1383		T6	753
valid_sources[0x09]	257644	1			T1	1467		T3	1476		T6	681
valid_sources[0x0a]	272502	1			T1	1670		T3	1482		T6	651
valid_sources[0x0b]	232391	1			T1	1585		T3	1417		T6	669
valid_sources[0x0c]	271070	1			T1	1520		T3	1455		T6	633
valid_sources[0x0d]	248155	1			T1	1310		T2	8061		T3	1393
valid_sources[0x0e]	266697	1			T1	1631		T3	1463		T6	626
valid_sources[0x0f]	247884	1			T1	1414		T3	1351		T6	661
valid_sources[0x10]	360915	1			T1	1617		T3	1472		T6	618
valid_sources[0x11]	254650	1			T1	1414		T3	1417		T6	692
valid_sources[0x12]	243305	1			T1	1558		T3	1487		T6	683
valid_sources[0x13]	278444	1			T1	1648		T3	1469		T6	601
valid_sources[0x14]	268106	1			T1	1360		T3	1499		T6	651
valid_sources[0x15]	276048	1			T1	1668		T3	1411		T6	687
valid_sources[0x16]	306410	1			T1	1442		T3	1373		T6	608
valid_sources[0x17]	391477	1			T1	1463		T3	1481		T6	752
valid_sources[0x18]	260047	1			T1	1452		T2	2543		T3	1375
valid_sources[0x19]	268172	1			T1	1884		T3	1370		T6	663
valid_sources[0x1a]	307673	1			T1	1580		T3	1536		T6	686
valid_sources[0x1b]	264614	1			T1	1475		T3	1563		T6	663
valid_sources[0x1c]	318248	1			T1	1426		T3	1460		T6	686
valid_sources[0x1d]	251619	1			T1	1594		T3	1500		T6	686
valid_sources[0x1e]	341816	1			T1	1644		T2	3585		T3	1502
valid_sources[0x1f]	281559	1			T1	1760		T2	11884		T3	1477
valid_sources[0x20]	277583	1			T1	1312		T3	1409		T6	680
valid_sources[0x21]	281409	1			T1	1404		T3	1481		T6	611
valid_sources[0x22]	283968	1			T1	1689		T3	1421		T6	667
valid_sources[0x23]	250092	1			T1	1329		T3	1499		T6	657
valid_sources[0x24]	298558	1			T1	1672		T3	1451		T6	624
valid_sources[0x25]	287523	1			T1	1510		T3	1414		T6	671
valid_sources[0x26]	242146	1			T1	1776		T3	1449		T6	684
valid_sources[0x27]	257076	1			T1	1449		T3	1443		T6	692
valid_sources[0x28]	306972	1			T1	1635		T3	1453		T6	681
valid_sources[0x29]	289502	1			T1	1527		T3	1468		T6	682
valid_sources[0x2a]	267249	1			T1	1534		T3	1463		T6	661
valid_sources[0x2b]	235438	1			T1	1529		T3	1399		T6	627
valid_sources[0x2c]	278020	1			T1	1632		T3	1407		T6	669
valid_sources[0x2d]	314584	1			T1	1549		T3	1492		T6	661
valid_sources[0x2e]	233085	1			T1	1531		T3	1438		T6	628
valid_sources[0x2f]	251041	1			T1	1505		T3	1471		T6	678
valid_sources[0x30]	300799	1			T1	1487		T3	1429		T6	674
valid_sources[0x31]	252581	1			T1	1566		T3	1469		T6	644
valid_sources[0x32]	231433	1			T1	1579		T3	1391		T6	623
valid_sources[0x33]	281983	1			T1	1545		T3	1497		T6	623
valid_sources[0x34]	278307	1			T1	1578		T3	1395		T6	623
valid_sources[0x35]	300123	1			T1	1488		T3	1514		T6	613
valid_sources[0x36]	274415	1			T1	1463		T3	1385		T6	675
valid_sources[0x37]	259442	1			T1	1626		T3	1427		T6	652
valid_sources[0x38]	279993	1			T1	1360		T3	1484		T6	764
valid_sources[0x39]	257405	1			T1	1671		T3	1437		T6	677
valid_sources[0x3a]	266522	1			T1	1697		T2	6629		T3	1452
valid_sources[0x3b]	318156	1			T1	1659		T2	33010		T3	1525
valid_sources[0x3c]	285874	1			T1	1651		T2	35769		T3	1473
valid_sources[0x3d]	297737	1			T1	1498		T3	1486		T6	674
valid_sources[0x3e]	299777	1			T1	1434		T3	1487		T6	670
valid_sources[0x3f]	259245	1			T1	1640		T3	1456		T6	661
valid_sources[0x40]	267808	1			T1	1349		T2	2029		T3	1400
valid_sources[0x41]	386697	1			T1	1345		T3	1415		T6	717
valid_sources[0x42]	345089	1			T1	1598		T3	1471		T6	633
valid_sources[0x43]	252639	1			T1	1394		T3	1430		T6	687
valid_sources[0x44]	272092	1			T1	1542		T3	1445		T6	644
valid_sources[0x45]	289700	1			T1	1468		T3	1360		T6	684
valid_sources[0x46]	238571	1			T1	1627		T3	1413		T6	717
valid_sources[0x47]	267170	1			T1	1420		T3	1503		T6	656
valid_sources[0x48]	251336	1			T1	1616		T3	1454		T6	642
valid_sources[0x49]	316754	1			T1	1490		T3	1461		T6	688
valid_sources[0x4a]	246930	1			T1	1455		T3	1395		T6	696
valid_sources[0x4b]	273423	1			T1	1528		T3	1402		T6	678
valid_sources[0x4c]	273546	1			T1	1405		T3	1479		T6	669
valid_sources[0x4d]	245941	1			T1	1598		T3	1476		T6	567
valid_sources[0x4e]	244891	1			T1	1462		T3	1456		T6	643
valid_sources[0x4f]	252711	1			T1	1604		T3	1418		T6	742
valid_sources[0x50]	287657	1			T1	1473		T3	1498		T6	648
valid_sources[0x51]	251667	1			T1	1502		T3	1454		T6	604
valid_sources[0x52]	257791	1			T1	1844		T3	1443		T6	674
valid_sources[0x53]	240477	1			T1	1562		T3	1474		T6	715
valid_sources[0x54]	242241	1			T1	1461		T3	1393		T6	647
valid_sources[0x55]	233081	1			T1	1517		T3	1423		T6	653
valid_sources[0x56]	276549	1			T1	1585		T3	1429		T6	666
valid_sources[0x57]	305012	1			T1	1500		T3	1459		T6	675
valid_sources[0x58]	255744	1			T1	1563		T3	1518		T6	671
valid_sources[0x59]	276074	1			T1	1442		T3	1443		T6	654
valid_sources[0x5a]	239890	1			T1	1522		T3	1489		T6	683
valid_sources[0x5b]	248841	1			T1	1626		T3	1483		T6	752
valid_sources[0x5c]	331766	1			T1	1549		T3	1501		T6	655
valid_sources[0x5d]	326304	1			T1	1479		T3	1410		T6	641
valid_sources[0x5e]	266075	1			T1	1532		T3	1510		T6	690
valid_sources[0x5f]	250579	1			T1	1638		T2	8151		T3	1446
valid_sources[0x60]	251126	1			T1	1561		T3	1561		T6	718
valid_sources[0x61]	262778	1			T1	1743		T3	1398		T6	662
valid_sources[0x62]	336543	1			T1	1550		T3	1409		T6	675
valid_sources[0x63]	285727	1			T1	1633		T2	36950		T3	1425
valid_sources[0x64]	274185	1			T1	1405		T3	1445		T6	585
valid_sources[0x65]	318626	1			T1	1614		T3	1471		T6	683
valid_sources[0x66]	241134	1			T1	1821		T3	1549		T6	604
valid_sources[0x67]	282454	1			T1	1521		T3	1430		T6	725
valid_sources[0x68]	240829	1			T1	1564		T3	1376		T6	624
valid_sources[0x69]	238013	1			T1	1645		T3	1476		T6	620
valid_sources[0x6a]	267967	1			T1	1572		T3	1499		T6	648
valid_sources[0x6b]	245206	1			T1	1600		T3	1435		T6	691
valid_sources[0x6c]	270891	1			T1	1392		T3	1458		T6	650
valid_sources[0x6d]	244002	1			T1	1599		T3	1455		T6	599
valid_sources[0x6e]	271445	1			T1	1505		T2	13871		T3	1508
valid_sources[0x6f]	232582	1			T1	1773		T3	1395		T6	644
valid_sources[0x70]	265851	1			T1	1356		T3	1439		T6	670
valid_sources[0x71]	327321	1			T1	1643		T2	2189		T3	1398
valid_sources[0x72]	267291	1			T1	1558		T3	1417		T6	703
valid_sources[0x73]	298652	1			T1	1562		T3	1483		T6	661
valid_sources[0x74]	246279	1			T1	1578		T3	1376		T6	676
valid_sources[0x75]	290506	1			T1	1536		T3	1434		T6	677
valid_sources[0x76]	333313	1			T1	1752		T3	1445		T6	664
valid_sources[0x77]	268064	1			T1	1652		T3	1477		T6	653
valid_sources[0x78]	267844	1			T1	1490		T3	1502		T6	658
valid_sources[0x79]	266575	1			T1	1534		T3	1451		T6	711
valid_sources[0x7a]	271898	1			T1	1463		T3	1378		T6	676
valid_sources[0x7b]	300346	1			T1	1417		T3	1472		T6	617
valid_sources[0x7c]	246685	1			T1	1546		T3	1485		T6	623
valid_sources[0x7d]	292302	1			T1	1543		T3	1439		T6	660
valid_sources[0x7e]	250518	1			T1	1644		T3	1425		T6	608
valid_sources[0x7f]	273658	1			T1	1536		T3	1391		T6	614
valid_sources[0x80]	240680	1			T1	1765		T3	1405		T6	639

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

28426305

1

T1

180296

T2

129892

T3

169242

values[0x0]

all_enables

biggest_size

14310158

1

T1

90313

T2

64814

T3

84046

values[0x1]

all_enables

biggest_size

14315943

1

T1

89639

T2

65119

T3

84540

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33381	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

135894

1

T1

45

T2

11

T3

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	49407	1			T1	41		T3	34		T5	26
values[0x0]	58247	1			T1	46		T2	24		T3	38
values[0x1]	61621	1			T1	55		T2	24		T3	47

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25488	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

143787

1

T1

52

T2

18

T3

47

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	671	1			T23	1		T26	1		T147	8
valid_sources[0x01]	579	1			T3	2		T5	5		T22	2
valid_sources[0x02]	897	1			T23	2		T25	319		T26	4
valid_sources[0x03]	505	1			T24	1		T148	1		T25	1
valid_sources[0x04]	785	1			T24	1		T23	2		T149	1
valid_sources[0x05]	467	1			T24	1		T25	1		T52	1
valid_sources[0x06]	501	1			T25	1		T26	5		T150	5
valid_sources[0x07]	1111	1			T26	4		T58	3		T145	1
valid_sources[0x08]	490	1			T23	1		T25	5		T26	6
valid_sources[0x09]	624	1			T3	2		T10	1		T24	1
valid_sources[0x0a]	964	1			T56	1		T26	11		T145	11
valid_sources[0x0b]	768	1			T5	1		T24	2		T26	2
valid_sources[0x0c]	704	1			T72	4		T24	1		T25	1
valid_sources[0x0d]	885	1			T26	3		T50	7		T145	2
valid_sources[0x0e]	566	1			T3	1		T24	2		T151	1
valid_sources[0x0f]	638	1			T26	2		T152	1		T145	6
valid_sources[0x10]	804	1			T3	6		T24	1		T23	1
valid_sources[0x11]	489	1			T3	1		T25	2		T26	3
valid_sources[0x12]	694	1			T153	1		T26	6		T152	1
valid_sources[0x13]	454	1			T3	2		T25	1		T26	6
valid_sources[0x14]	1082	1			T24	1		T23	2		T25	2
valid_sources[0x15]	704	1			T98	1		T26	1		T152	2
valid_sources[0x16]	558	1			T24	1		T26	1		T52	1
valid_sources[0x17]	477	1			T5	2		T25	2		T154	1
valid_sources[0x18]	675	1			T149	1		T26	3		T59	1
valid_sources[0x19]	587	1			T5	1		T26	1		T145	7
valid_sources[0x1a]	709	1			T24	1		T56	4		T155	1
valid_sources[0x1b]	417	1			T24	2		T23	2		T26	1
valid_sources[0x1c]	817	1			T3	3		T10	1		T5	1
valid_sources[0x1d]	537	1			T24	1		T26	20		T156	1
valid_sources[0x1e]	582	1			T153	1		T26	1		T52	1
valid_sources[0x1f]	545	1			T24	1		T25	3		T26	10
valid_sources[0x20]	487	1			T3	1		T5	3		T57	1
valid_sources[0x21]	407	1			T3	2		T5	2		T26	2
valid_sources[0x22]	807	1			T24	1		T30	1		T25	40
valid_sources[0x23]	830	1			T3	1		T24	1		T99	1
valid_sources[0x24]	943	1			T24	4		T23	2		T157	1
valid_sources[0x25]	910	1			T23	1		T52	1		T145	16
valid_sources[0x26]	394	1			T24	2		T26	1		T152	1
valid_sources[0x27]	700	1			T3	1		T5	2		T158	1
valid_sources[0x28]	725	1			T153	1		T24	1		T23	1
valid_sources[0x29]	666	1			T5	2		T56	4		T26	15
valid_sources[0x2a]	656	1			T23	3		T158	1		T25	1
valid_sources[0x2b]	443	1			T26	11		T145	3		T37	22
valid_sources[0x2c]	549	1			T5	5		T26	1		T37	21
valid_sources[0x2d]	524	1			T24	1		T158	1		T155	1
valid_sources[0x2e]	632	1			T56	10		T25	156		T145	5
valid_sources[0x2f]	801	1			T5	1		T25	1		T26	7
valid_sources[0x30]	449	1			T3	5		T10	1		T57	4
valid_sources[0x31]	625	1			T24	2		T23	2		T18	14
valid_sources[0x32]	621	1			T3	4		T29	1		T56	6
valid_sources[0x33]	545	1			T10	1		T23	4		T26	2
valid_sources[0x34]	412	1			T56	1		T26	1		T145	11
valid_sources[0x35]	572	1			T24	1		T23	1		T52	1
valid_sources[0x36]	957	1			T3	2		T153	1		T24	1
valid_sources[0x37]	605	1			T24	1		T23	1		T25	1
valid_sources[0x38]	590	1			T10	1		T23	3		T26	4
valid_sources[0x39]	582	1			T26	5		T152	5		T159	2
valid_sources[0x3a]	754	1			T102	6		T26	3		T37	12
valid_sources[0x3b]	589	1			T57	2		T26	3		T37	14
valid_sources[0x3c]	638	1			T3	1		T160	19		T16	1
valid_sources[0x3d]	484	1			T24	1		T23	1		T161	2
valid_sources[0x3e]	822	1			T10	2		T26	5		T48	10
valid_sources[0x3f]	574	1			T24	3		T25	6		T152	3
valid_sources[0x40]	636	1			T24	2		T23	3		T25	1
valid_sources[0x41]	639	1			T24	1		T23	1		T56	3
valid_sources[0x42]	766	1			T3	2		T24	1		T23	1
valid_sources[0x43]	438	1			T25	1		T26	7		T152	2
valid_sources[0x44]	963	1			T57	9		T25	3		T26	1
valid_sources[0x45]	892	1			T23	3		T162	1		T57	5
valid_sources[0x46]	847	1			T56	3		T25	1		T26	5
valid_sources[0x47]	788	1			T56	7		T26	2		T152	1
valid_sources[0x48]	633	1			T5	2		T70	1		T37	13
valid_sources[0x49]	475	1			T153	1		T24	1		T163	1
valid_sources[0x4a]	559	1			T3	3		T5	2		T158	2
valid_sources[0x4b]	806	1			T24	2		T19	1		T37	25
valid_sources[0x4c]	792	1			T164	2		T25	7		T26	2
valid_sources[0x4d]	750	1			T24	4		T23	6		T144	1
valid_sources[0x4e]	924	1			T24	2		T100	1		T26	6
valid_sources[0x4f]	513	1			T3	3		T5	1		T56	5
valid_sources[0x50]	478	1			T3	1		T56	1		T26	4
valid_sources[0x51]	514	1			T23	2		T25	5		T26	7
valid_sources[0x52]	510	1			T5	1		T24	1		T56	1
valid_sources[0x53]	930	1			T24	1		T25	111		T26	4
valid_sources[0x54]	1034	1			T5	2		T56	5		T25	1
valid_sources[0x55]	796	1			T25	165		T26	3		T58	4
valid_sources[0x56]	512	1			T5	1		T24	2		T23	1
valid_sources[0x57]	697	1			T3	1		T70	1		T24	1
valid_sources[0x58]	547	1			T23	1		T26	3		T145	11
valid_sources[0x59]	498	1			T3	2		T10	1		T11	6
valid_sources[0x5a]	936	1			T26	3		T58	2		T59	2
valid_sources[0x5b]	507	1			T165	1		T26	10		T37	10
valid_sources[0x5c]	523	1			T25	3		T26	2		T152	2
valid_sources[0x5d]	452	1			T24	1		T23	1		T26	1
valid_sources[0x5e]	520	1			T12	1		T26	8		T79	2
valid_sources[0x5f]	570	1			T24	1		T26	3		T145	2
valid_sources[0x60]	580	1			T24	2		T23	2		T26	1
valid_sources[0x61]	518	1			T10	1		T70	1		T24	2
valid_sources[0x62]	638	1			T3	1		T8	3		T5	5
valid_sources[0x63]	590	1			T24	1		T23	1		T25	6
valid_sources[0x64]	536	1			T5	1		T98	1		T26	2
valid_sources[0x65]	481	1			T3	4		T4	2		T23	2
valid_sources[0x66]	437	1			T3	1		T10	1		T23	2
valid_sources[0x67]	570	1			T23	1		T25	3		T26	4
valid_sources[0x68]	1173	1			T3	3		T26	8		T52	1
valid_sources[0x69]	454	1			T24	4		T25	1		T26	8
valid_sources[0x6a]	716	1			T24	1		T155	1		T26	4
valid_sources[0x6b]	1131	1			T10	1		T24	1		T58	2
valid_sources[0x6c]	455	1			T153	1		T24	1		T52	1
valid_sources[0x6d]	694	1			T23	2		T158	1		T25	1
valid_sources[0x6e]	756	1			T3	3		T23	1		T25	3
valid_sources[0x6f]	559	1			T71	2		T24	1		T139	3
valid_sources[0x70]	673	1			T153	1		T25	148		T26	4
valid_sources[0x71]	854	1			T26	1		T145	4		T16	1
valid_sources[0x72]	608	1			T24	3		T25	2		T58	4
valid_sources[0x73]	792	1			T24	3		T23	3		T26	1
valid_sources[0x74]	928	1			T56	5		T25	86		T26	2
valid_sources[0x75]	617	1			T153	1		T24	1		T25	2
valid_sources[0x76]	432	1			T10	1		T24	1		T155	1
valid_sources[0x77]	609	1			T10	1		T23	1		T26	9
valid_sources[0x78]	547	1			T3	1		T25	1		T26	5
valid_sources[0x79]	779	1			T3	1		T10	1		T37	14
valid_sources[0x7a]	676	1			T3	5		T10	1		T57	6
valid_sources[0x7b]	521	1			T3	3		T10	1		T24	1
valid_sources[0x7c]	767	1			T3	3		T24	1		T23	2
valid_sources[0x7d]	527	1			T23	1		T25	2		T26	2
valid_sources[0x7e]	603	1			T5	2		T25	4		T166	1
valid_sources[0x7f]	1194	1			T70	3		T24	4		T161	1
valid_sources[0x80]	504	1			T3	1		T5	1		T23	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

37572

1

T1

24

T3

11

T5

9

values[0x0]

all_enables

biggest_size

50317

1

T1

15

T2

8

T3

14

values[0x1]

all_enables

biggest_size

48005

1

T1

6

T2

3

T3

10