Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

13369904

1

T1

32187

T2

20851

T3

28253

full_word

52316406

1

T1

321270

T2

207775

T3

298954

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	65686030	1			T1	353457		T2	228626		T3	327207
auto[TlIntgErrCmd]	90	1			T104	5		T105	4		T106	1
auto[TlIntgErrData]	98	1			T104	10		T105	11		T106	4
auto[TlIntgErrBoth]	92	1			T104	5		T105	5		T106	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30133891

1

T1

156371

T2

85679

T3

144195

auto[1]

35552419

1

T1

197086

T2

142947

T3

183012

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	6391262	1			T1	14160		T2	7837		T3	12266
auto[TlIntgErrNone]	partial	auto[1]	6978388	1			T1	18027		T2	13014		T3	15987
auto[TlIntgErrNone]	full_word	auto[0]	23742498	1			T1	142211		T2	77842		T3	131929
auto[TlIntgErrNone]	full_word	auto[1]	28573882	1			T1	179059		T2	129933		T3	167025
auto[TlIntgErrCmd]	partial	auto[0]	45	1			T104	3		T127	3		T128	1
auto[TlIntgErrCmd]	partial	auto[1]	38	1			T104	2		T105	4		T106	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T129	2		T130	2		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T131	1		T132	1		T133	1
auto[TlIntgErrData]	partial	auto[0]	37	1			T104	3		T105	5		T106	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T104	3		T105	5		T106	2
auto[TlIntgErrData]	full_word	auto[0]	8	1			T104	1		T106	1		T128	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T104	3		T105	1		T134	1
auto[TlIntgErrBoth]	partial	auto[0]	37	1			T104	4		T105	3		T106	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T104	1		T105	2		T106	2
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T106	1		T135	2		T136	2