Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	565598	1			T3	11347		T5	2421		T12	5
auto[1]	10715393	1			T1	41693		T2	7605		T3	2701
auto[2]	475070	1			T3	10242		T5	2191		T12	4
auto[3]	10631612	1			T1	41821		T2	7574		T3	1560

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14310679	1			T1	69494		T2	12496		T3	20366
auto[1]	2163143	1			T1	6777		T2	1310		T3	2764
auto[2]	2162709	1			T1	6628		T2	1239		T3	2413
auto[3]	3751142	1			T1	615		T2	134		T3	307

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8367987

1

T1

83426

T2

15161

T3

25829

auto[1]

14019686

1

T1

88

T2

18

T3

21

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	226904	1			T3	9378		T5	1992		T12	5
auto[0]	auto[0]	auto[1]	23628	1			T3	947		T5	210		T24	310
auto[0]	auto[0]	auto[2]	23851	1			T3	927		T5	197		T24	323
auto[0]	auto[0]	auto[3]	7896	1			T3	84		T5	20		T24	26
auto[0]	auto[1]	auto[0]	3206394	1			T1	34661		T2	6266		T3	1544
auto[0]	auto[1]	auto[1]	334808	1			T1	3241		T2	670		T3	918
auto[0]	auto[1]	auto[2]	326183	1			T1	3447		T2	596		T3	142
auto[0]	auto[1]	auto[3]	76339	1			T1	303		T2	62		T3	93
auto[0]	auto[2]	auto[0]	192090	1			T3	8685		T5	1841		T12	3
auto[0]	auto[2]	auto[1]	19929	1			T3	824		T5	185		T24	294
auto[0]	auto[2]	auto[2]	19377	1			T3	662		T5	147		T12	1
auto[0]	auto[2]	auto[3]	5784	1			T3	66		T5	15		T24	22
auto[0]	auto[3]	auto[0]	3170097	1			T1	34758		T2	6215		T3	742
auto[0]	auto[3]	auto[1]	321692	1			T1	3530		T2	638		T3	74
auto[0]	auto[3]	auto[2]	333372	1			T1	3174		T2	642		T3	679
auto[0]	auto[3]	auto[3]	79643	1			T1	312		T2	72		T3	64
auto[1]	auto[0]	auto[0]	9759	1			T3	10		T5	1		T24	1
auto[1]	auto[0]	auto[1]	41946	1			T100	3574		T142	4416		T143	2862
auto[1]	auto[0]	auto[2]	41624	1			T3	1		T5	1		T24	1
auto[1]	auto[0]	auto[3]	189990	1			T100	15947		T144	3		T142	20023
auto[1]	auto[1]	auto[0]	3749379	1			T1	32		T2	9		T3	2
auto[1]	auto[1]	auto[1]	702590	1			T1	4		T2	2		T3	1
auto[1]	auto[1]	auto[2]	687202	1			T1	5		T3	1		T6	10510
auto[1]	auto[1]	auto[3]	1632498	1			T6	47802		T7	1		T11	827
auto[1]	auto[2]	auto[0]	8345	1			T3	4		T5	3		T24	1
auto[1]	auto[2]	auto[1]	36233	1			T100	3197		T144	1		T142	4044
auto[1]	auto[2]	auto[2]	35110	1			T3	1		T24	1		T100	2940
auto[1]	auto[2]	auto[3]	158202	1			T100	13493		T142	16821		T143	11100
auto[1]	auto[3]	auto[0]	3747711	1			T1	43		T2	6		T3	1
auto[1]	auto[3]	auto[1]	682317	1			T1	2		T6	10676		T11	8929
auto[1]	auto[3]	auto[2]	695990	1			T1	2		T2	1		T6	10679
auto[1]	auto[3]	auto[3]	1600790	1			T6	47507		T7	2		T11	829