Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	292220914	136529	0	0
ctrl_regwen_rd_A	292220914	5404	0	0
exec_rd_A	292220914	4873	0	0
exec_regwen_rd_A	292220914	5460	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292220914	136529	0	0
T25	60157	3166	0	0
T26	29245	1230	0	0
T27	0	2817	0	0
T37	0	3737	0	0
T42	0	6444	0	0
T43	0	1392	0	0
T44	0	1240	0	0
T45	0	1207	0	0
T46	0	1283	0	0
T47	0	6584	0	0
T48	1218	0	0	0
T49	23131	0	0	0
T50	228150	0	0	0
T51	12925	0	0	0
T52	103468	0	0	0
T53	275620	0	0	0
T54	7103	0	0	0
T55	145726	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292220914	5404	0	0
T108	20571	245	0	0
T109	0	462	0	0
T110	0	263	0	0
T111	0	652	0	0
T112	0	576	0	0
T113	0	224	0	0
T114	0	296	0	0
T115	0	511	0	0
T116	0	304	0	0
T117	0	89	0	0
T118	5720	0	0	0
T119	4898	0	0	0
T120	47601	0	0	0
T121	9803	0	0	0
T122	7622	0	0	0
T123	12999	0	0	0
T124	213304	0	0	0
T125	12556	0	0	0
T126	285262	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292220914	4873	0	0
T108	20571	167	0	0
T109	0	290	0	0
T110	0	214	0	0
T111	0	411	0	0
T112	0	584	0	0
T113	0	201	0	0
T114	0	291	0	0
T115	0	531	0	0
T116	0	356	0	0
T117	0	116	0	0
T118	5720	0	0	0
T119	4898	0	0	0
T120	47601	0	0	0
T121	9803	0	0	0
T122	7622	0	0	0
T123	12999	0	0	0
T124	213304	0	0	0
T125	12556	0	0	0
T126	285262	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	292220914	5460	0	0
T108	20571	206	0	0
T109	0	412	0	0
T110	0	221	0	0
T111	0	556	0	0
T112	0	675	0	0
T113	0	176	0	0
T114	0	323	0	0
T115	0	538	0	0
T116	0	309	0	0
T117	0	44	0	0
T118	5720	0	0	0
T119	4898	0	0	0
T120	47601	0	0	0
T121	9803	0	0	0
T122	7622	0	0	0
T123	12999	0	0	0
T124	213304	0	0	0
T125	12556	0	0	0
T126	285262	0	0	0