Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	145954018	1			T1	6334		T2	2022		T3	841768
instr_valid_dis	113236757	1			T1	6334		T2	2022		T3	289226
instr_en	23777653	1			T3	99034		T12	350784		T44	235050

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11065766	1			T3	134750		T12	190264		T13	63606
sram_ifetch_valid_disable	111917450	1			T1	6334		T2	2022		T3	396998
sram_ifetch_enable	22970802	1			T3	310020		T12	86794		T13	159394

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	145954018	1			T1	6334		T2	2022		T3	841768
hw_debug_en_valid_off	112405560	1			T1	6334		T2	2022		T3	353742
hw_debug_en_on	21872457	1			T3	326014		T12	268362		T13	169184

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	111917450	1			T1	6334		T2	2022		T3	396998
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	98809399	1			T1	6334		T2	2022		T3	156716
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9547728	1			T3	87420		T12	183880		T44	23230
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4454180	1			T3	17934		T12	35562		T13	17638
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2156986	1			T12	8114		T60	78800		T61	102892
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1800908	1			T12	27448		T44	90512		T23	48488
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4236256	1			T3	79840		T12	101762		T13	45968
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1982482	1			T3	32640		T12	16962		T44	87616
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1371546	1			T12	38132		T59	28538		T61	7208
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8448124	1			T3	131156		T12	114532		T13	47370
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3836520	1			T3	38718		T12	16414		T44	17158
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3439208	1			T3	39954		T12	59962		T44	23230

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9999993	1			T3	11614		T12	67846		T44	121308
lc_exec_en	9188077	1			T3	115018		T12	52068		T13	75846
valid_exec_dis	107732948	1			T1	6334		T2	2022		T3	327424
invalid_exec_dis	34036568	1			T3	444770		T12	277058		T13	223000