| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2668126877 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.83954613 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3251753974 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.367544590 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3230604932 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.630416876 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.359279285 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3297656003 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2145280091 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3910994282 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2442920561 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4140698988 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1028901288 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.97606134 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.158521886 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1040413299 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1087783477 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3787458170 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3868283811 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.311405245 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.235572751 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.179069014 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3166890851 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1463907409 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3908745441 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1391715370 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2461542801 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3475473968 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.91816305 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3094469163 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4167410179 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1511185589 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3509512996 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2775429305 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2345388675 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.2278202938 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4121215905 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3683652812 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3525850717 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1841616070 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1133862603 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2856077177 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.537723175 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3965623808 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1016128399 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2184786491 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3285738577 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1142927513 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3245929132 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2513680099 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3580489881 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2662742233 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3939718382 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.209053184 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1012104848 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2648370157 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1368923434 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2059188009 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.559279254 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2156448235 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1784431382 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2839528164 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.215172162 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3022509362 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1813817056 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.75375823 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1364438627 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.4082448686 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2971734036 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2009770241 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1774683927 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4061853675 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1037274399 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.428437625 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1837481623 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1544680297 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3990307208 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2945788475 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1438357783 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1848100254 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1536927152 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.671818399 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.239075382 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2987873851 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4274943109 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2822911772 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2083453187 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1366800015 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.332515508 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3539405934 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4061966045 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3803310331 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3286155922 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.4113465706 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.20796220 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3897449590 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.902728414 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.935731847 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2166126894 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2068863596 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3910208280 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1827670830 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2812548089 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.81389945 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.567438595 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3931682099 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2341207110 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2302994318 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2020598418 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1777037091 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1475578913 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2367691053 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1711910749 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1589400889 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3985375084 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2224558076 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3331056338 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.305693837 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3538684472 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2992765591 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3919108552 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.162701407 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.577646484 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2155480382 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.794363805 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.745144290 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.296495258 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.81277835 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.814696505 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.2189987126 |
| /workspace/coverage/default/0.sram_ctrl_bijection.4172593616 |
| /workspace/coverage/default/0.sram_ctrl_executable.2898774184 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.1515744009 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.131668137 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.4245845553 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.344104386 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.1520884672 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.3373532757 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1712451776 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.1506251788 |
| /workspace/coverage/default/0.sram_ctrl_regwen.442542708 |
| /workspace/coverage/default/0.sram_ctrl_smoke.2814546513 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.2062372869 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.4080147253 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.25413187 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1087113423 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2518200549 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.4138221599 |
| /workspace/coverage/default/1.sram_ctrl_bijection.3050897843 |
| /workspace/coverage/default/1.sram_ctrl_executable.3203287880 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.3264162712 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.249080200 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2027396527 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.863117858 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.2353946657 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.123669035 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.3881186508 |
| /workspace/coverage/default/1.sram_ctrl_regwen.2782566876 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.2513679596 |
| /workspace/coverage/default/1.sram_ctrl_smoke.1088571493 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2170018203 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3179028957 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.377545400 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.1988129880 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.2637135461 |
| /workspace/coverage/default/10.sram_ctrl_bijection.1507681839 |
| /workspace/coverage/default/10.sram_ctrl_executable.1650072018 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.653116146 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.3413613650 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.1685918951 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.953422654 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.1037730330 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.638094606 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.33122689 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.306446003 |
| /workspace/coverage/default/10.sram_ctrl_smoke.2273457588 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.2792453715 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.813129473 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3822271147 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.2528912869 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.2121618331 |
| /workspace/coverage/default/11.sram_ctrl_bijection.4253523357 |
| /workspace/coverage/default/11.sram_ctrl_executable.1884973164 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.2802904267 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.2842800573 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.811277506 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.2600366479 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.1429002326 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.2385423934 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.3551456618 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.1936941237 |
| /workspace/coverage/default/11.sram_ctrl_regwen.1263177043 |
| /workspace/coverage/default/11.sram_ctrl_smoke.3191259169 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.2028552176 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.427915327 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.270368099 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2407164678 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.2533143482 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.3296842667 |
| /workspace/coverage/default/12.sram_ctrl_bijection.1927011104 |
| /workspace/coverage/default/12.sram_ctrl_executable.2027348543 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.1800004152 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.447722680 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.941853841 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.59798883 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.2749267446 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.3194203982 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1951822907 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.1202299398 |
| /workspace/coverage/default/12.sram_ctrl_regwen.1484656587 |
| /workspace/coverage/default/12.sram_ctrl_smoke.2321338759 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.3202207684 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.57477874 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.1202670925 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.337282003 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.236951216 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.614948724 |
| /workspace/coverage/default/13.sram_ctrl_bijection.1001805710 |
| /workspace/coverage/default/13.sram_ctrl_executable.1223611184 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.1412204630 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2467944005 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.4005296126 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.309391494 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.875796682 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.27508577 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.3152847671 |
| /workspace/coverage/default/13.sram_ctrl_regwen.2709220638 |
| /workspace/coverage/default/13.sram_ctrl_smoke.2357966100 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.2305336687 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.4233565449 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3191186697 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.398885899 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.3178495260 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.3838059287 |
| /workspace/coverage/default/14.sram_ctrl_bijection.900616764 |
| /workspace/coverage/default/14.sram_ctrl_executable.277273290 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.2036031552 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2866593327 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.1700259069 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.3700828316 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.818047738 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1067966589 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.3317503891 |
| /workspace/coverage/default/14.sram_ctrl_smoke.1441959204 |
| /workspace/coverage/default/14.sram_ctrl_stress_all.2509779909 |
| /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2608546951 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2277613715 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1126350990 |
| /workspace/coverage/default/15.sram_ctrl_access_during_key_req.3545098508 |
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| /workspace/coverage/default/44.sram_ctrl_alert_test.2008487558 |
| /workspace/coverage/default/44.sram_ctrl_bijection.929381796 |
| /workspace/coverage/default/44.sram_ctrl_executable.3610373969 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.1350469045 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.4228498695 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.4098987189 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.3273424787 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.4229226256 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.2527767667 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1950063395 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.627103070 |
| /workspace/coverage/default/44.sram_ctrl_regwen.3910340977 |
| /workspace/coverage/default/44.sram_ctrl_smoke.946782453 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.1774638788 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2772297002 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3333538681 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1882460148 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.438703207 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.3073774755 |
| /workspace/coverage/default/45.sram_ctrl_bijection.3486187320 |
| /workspace/coverage/default/45.sram_ctrl_executable.2301312877 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.2549133186 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.2089334916 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2613210907 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.541596348 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.3382473425 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.3453013504 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3970589986 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.3615794458 |
| /workspace/coverage/default/45.sram_ctrl_regwen.3693250515 |
| /workspace/coverage/default/45.sram_ctrl_smoke.945635339 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.1595156625 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.576686714 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3572618200 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.2379471467 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2152228815 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.1030911936 |
| /workspace/coverage/default/46.sram_ctrl_bijection.278979340 |
| /workspace/coverage/default/46.sram_ctrl_executable.260765935 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.3911596270 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.1122933226 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.476998533 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.4207028703 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.188937785 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.3261130036 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.440149539 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.2235667773 |
| /workspace/coverage/default/46.sram_ctrl_regwen.939676466 |
| /workspace/coverage/default/46.sram_ctrl_smoke.812786684 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.2100012048 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3001841015 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.2150417425 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1239320072 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3845587731 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.905481922 |
| /workspace/coverage/default/47.sram_ctrl_bijection.964386061 |
| /workspace/coverage/default/47.sram_ctrl_executable.456501732 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.1800916016 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.437697433 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2957846170 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.1468264365 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.3302704834 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.2848006650 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3312768823 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.3244092787 |
| /workspace/coverage/default/47.sram_ctrl_regwen.390525586 |
| /workspace/coverage/default/47.sram_ctrl_smoke.339061525 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.1833082103 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2016097112 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.4201240154 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.426036740 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.402257509 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.383537199 |
| /workspace/coverage/default/48.sram_ctrl_bijection.3701087331 |
| /workspace/coverage/default/48.sram_ctrl_executable.2704055589 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.2066541265 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.1338440384 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.1336290508 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.2790957794 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.1441368813 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3318851797 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.2673192467 |
| /workspace/coverage/default/48.sram_ctrl_regwen.2988519727 |
| /workspace/coverage/default/48.sram_ctrl_smoke.698065479 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.434580221 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.752279912 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.248567535 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1593882423 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.585934817 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.210907310 |
| /workspace/coverage/default/49.sram_ctrl_bijection.3190245788 |
| /workspace/coverage/default/49.sram_ctrl_executable.2747270220 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.4177405301 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.636292094 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2774156734 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.1908028873 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.3159516674 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.1876374696 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1452785629 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.2694102994 |
| /workspace/coverage/default/49.sram_ctrl_regwen.3660810914 |
| /workspace/coverage/default/49.sram_ctrl_smoke.1013340677 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.1687333239 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2177303570 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3063310813 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.2510897332 |
| /workspace/coverage/default/5.sram_ctrl_bijection.4076234797 |
| /workspace/coverage/default/5.sram_ctrl_executable.2450167921 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.4050249290 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.3718305913 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1942670728 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.3117680947 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.248971683 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.1855962097 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1795545214 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.189032433 |
| /workspace/coverage/default/5.sram_ctrl_regwen.2686088205 |
| /workspace/coverage/default/5.sram_ctrl_smoke.3918494052 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.2462392414 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.650329417 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1751254749 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3253908221 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.4100803930 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.3071799688 |
| /workspace/coverage/default/6.sram_ctrl_bijection.3076266500 |
| /workspace/coverage/default/6.sram_ctrl_executable.2995697942 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.759612711 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2975815999 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.73985172 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.993987889 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.2361050681 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2519162855 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.4048469604 |
| /workspace/coverage/default/6.sram_ctrl_regwen.556247292 |
| /workspace/coverage/default/6.sram_ctrl_smoke.4148163467 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.4163905125 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1724190001 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.4163876459 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2897257238 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.2652544982 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.3028186276 |
| /workspace/coverage/default/7.sram_ctrl_bijection.398825736 |
| /workspace/coverage/default/7.sram_ctrl_executable.821313077 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.4085397492 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.558014307 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1772470546 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.1074451445 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.4119144471 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.1650818296 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2099733379 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.2981772696 |
| /workspace/coverage/default/7.sram_ctrl_regwen.1261497647 |
| /workspace/coverage/default/7.sram_ctrl_smoke.3504714712 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.2129030501 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4247892698 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1261024011 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.4273270198 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.1697293248 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.1652916511 |
| /workspace/coverage/default/8.sram_ctrl_bijection.2004028770 |
| /workspace/coverage/default/8.sram_ctrl_executable.3202672146 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.650331576 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.12751470 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.182212668 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.967709419 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.1095984516 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.1509652439 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1209160673 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.2970421251 |
| /workspace/coverage/default/8.sram_ctrl_regwen.925324262 |
| /workspace/coverage/default/8.sram_ctrl_smoke.1547238741 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.554963437 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1473083531 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2684613412 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2189110541 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1173118385 |
| /workspace/coverage/default/9.sram_ctrl_bijection.2619973827 |
| /workspace/coverage/default/9.sram_ctrl_executable.132948384 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.3019795976 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.4264717083 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3166887996 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.4160183603 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.3991720195 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.239715666 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3636308173 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.3710355343 |
| /workspace/coverage/default/9.sram_ctrl_regwen.2372856911 |
| /workspace/coverage/default/9.sram_ctrl_smoke.694734675 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.1288444634 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.882571389 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.4254774550 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2820442490 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.3946699034 |
|
|
Mar 10 02:37:31 PM PDT 24 |
Mar 10 02:37:41 PM PDT 24 |
562874124 ps |
| T2 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3138988760 |
|
|
Mar 10 02:38:17 PM PDT 24 |
Mar 10 02:38:20 PM PDT 24 |
454585858 ps |
| T3 |
/workspace/coverage/default/39.sram_ctrl_stress_all.3317669806 |
|
|
Mar 10 02:40:10 PM PDT 24 |
Mar 10 03:20:07 PM PDT 24 |
30201296229 ps |
| T5 |
/workspace/coverage/default/37.sram_ctrl_partial_access.1069847598 |
|
|
Mar 10 02:39:42 PM PDT 24 |
Mar 10 02:39:48 PM PDT 24 |
269268599 ps |
| T6 |
/workspace/coverage/default/41.sram_ctrl_partial_access.555183137 |
|
|
Mar 10 02:40:26 PM PDT 24 |
Mar 10 02:41:14 PM PDT 24 |
493801127 ps |
| T7 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.4004151575 |
|
|
Mar 10 02:37:07 PM PDT 24 |
Mar 10 02:49:13 PM PDT 24 |
66950939898 ps |
| T8 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.3879395298 |
|
|
Mar 10 02:40:23 PM PDT 24 |
Mar 10 02:45:43 PM PDT 24 |
20036078942 ps |
| T9 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.960297847 |
|
|
Mar 10 02:38:39 PM PDT 24 |
Mar 10 02:40:07 PM PDT 24 |
435899867 ps |
| T10 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2680749775 |
|
|
Mar 10 02:40:14 PM PDT 24 |
Mar 10 02:46:42 PM PDT 24 |
15933675087 ps |
| T11 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.730848788 |
|
|
Mar 10 02:37:20 PM PDT 24 |
Mar 10 02:39:21 PM PDT 24 |
149245444 ps |
| T17 |
/workspace/coverage/default/41.sram_ctrl_alert_test.2835764699 |
|
|
Mar 10 02:40:27 PM PDT 24 |
Mar 10 02:40:28 PM PDT 24 |
31463646 ps |
| T4 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.944891841 |
|
|
Mar 10 02:38:01 PM PDT 24 |
Mar 10 02:38:09 PM PDT 24 |
565386143 ps |
| T12 |
/workspace/coverage/default/28.sram_ctrl_executable.648649013 |
|
|
Mar 10 02:38:29 PM PDT 24 |
Mar 10 03:11:24 PM PDT 24 |
17673707520 ps |
| T90 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.1009575476 |
|
|
Mar 10 02:35:08 PM PDT 24 |
Mar 10 02:39:45 PM PDT 24 |
772898042 ps |
| T14 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.3528509641 |
|
|
Mar 10 02:38:22 PM PDT 24 |
Mar 10 02:56:02 PM PDT 24 |
11704683517 ps |
| T72 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.4276589954 |
|
|
Mar 10 02:40:06 PM PDT 24 |
Mar 10 02:43:48 PM PDT 24 |
9632120518 ps |
| T91 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.549338389 |
|
|
Mar 10 02:37:02 PM PDT 24 |
Mar 10 02:41:04 PM PDT 24 |
2637689345 ps |
| T13 |
/workspace/coverage/default/24.sram_ctrl_regwen.1748596627 |
|
|
Mar 10 02:38:11 PM PDT 24 |
Mar 10 02:55:06 PM PDT 24 |
74829254689 ps |
| T155 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3194203982 |
|
|
Mar 10 02:36:10 PM PDT 24 |
Mar 10 02:36:30 PM PDT 24 |
1197949300 ps |
| T146 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1022210283 |
|
|
Mar 10 02:39:10 PM PDT 24 |
Mar 10 02:39:58 PM PDT 24 |
211610719 ps |
| T164 |
/workspace/coverage/default/29.sram_ctrl_bijection.1169193197 |
|
|
Mar 10 02:38:36 PM PDT 24 |
Mar 10 02:39:04 PM PDT 24 |
1398372434 ps |
| T44 |
/workspace/coverage/default/43.sram_ctrl_executable.278411054 |
|
|
Mar 10 02:40:43 PM PDT 24 |
Mar 10 03:12:54 PM PDT 24 |
93060532458 ps |
| T23 |
/workspace/coverage/default/25.sram_ctrl_stress_all.803857808 |
|
|
Mar 10 02:38:15 PM PDT 24 |
Mar 10 03:38:04 PM PDT 24 |
48385492152 ps |
| T165 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.2491765710 |
|
|
Mar 10 02:38:56 PM PDT 24 |
Mar 10 02:39:02 PM PDT 24 |
205469312 ps |
| T24 |
/workspace/coverage/default/33.sram_ctrl_regwen.2756888235 |
|
|
Mar 10 02:39:14 PM PDT 24 |
Mar 10 02:57:13 PM PDT 24 |
97636132192 ps |
| T166 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3302704834 |
|
|
Mar 10 02:41:19 PM PDT 24 |
Mar 10 03:19:16 PM PDT 24 |
34852302694 ps |
| T59 |
/workspace/coverage/default/9.sram_ctrl_regwen.2372856911 |
|
|
Mar 10 02:35:46 PM PDT 24 |
Mar 10 02:51:30 PM PDT 24 |
8062981873 ps |
| T60 |
/workspace/coverage/default/0.sram_ctrl_regwen.442542708 |
|
|
Mar 10 02:34:46 PM PDT 24 |
Mar 10 02:37:04 PM PDT 24 |
9849285755 ps |
| T167 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.59798883 |
|
|
Mar 10 02:36:09 PM PDT 24 |
Mar 10 02:36:19 PM PDT 24 |
2605902735 ps |
| T15 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.2189110541 |
|
|
Mar 10 02:35:50 PM PDT 24 |
Mar 10 02:45:06 PM PDT 24 |
1966823523 ps |
| T61 |
/workspace/coverage/default/33.sram_ctrl_stress_all.4242429376 |
|
|
Mar 10 02:39:16 PM PDT 24 |
Mar 10 04:16:18 PM PDT 24 |
77904774234 ps |
| T96 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.920932287 |
|
|
Mar 10 02:40:43 PM PDT 24 |
Mar 10 02:48:18 PM PDT 24 |
71795009032 ps |
| T30 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.4254608389 |
|
|
Mar 10 02:38:31 PM PDT 24 |
Mar 10 02:38:32 PM PDT 24 |
115676451 ps |
| T97 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.3191186697 |
|
|
Mar 10 02:36:12 PM PDT 24 |
Mar 10 02:38:31 PM PDT 24 |
2877817462 ps |
| T160 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.2186983985 |
|
|
Mar 10 02:39:36 PM PDT 24 |
Mar 10 02:40:50 PM PDT 24 |
461784361 ps |
| T168 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3822271147 |
|
|
Mar 10 02:35:55 PM PDT 24 |
Mar 10 02:37:26 PM PDT 24 |
148371533 ps |
| T31 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.2209897223 |
|
|
Mar 10 02:38:48 PM PDT 24 |
Mar 10 02:38:49 PM PDT 24 |
30443045 ps |
| T98 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2341646375 |
|
|
Mar 10 02:40:04 PM PDT 24 |
Mar 10 02:43:15 PM PDT 24 |
2607625600 ps |
| T147 |
/workspace/coverage/default/16.sram_ctrl_partial_access.2641318249 |
|
|
Mar 10 02:36:39 PM PDT 24 |
Mar 10 02:36:41 PM PDT 24 |
206279647 ps |
| T99 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3708874321 |
|
|
Mar 10 02:34:48 PM PDT 24 |
Mar 10 02:37:20 PM PDT 24 |
8764112784 ps |
| T100 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2565778574 |
|
|
Mar 10 02:40:43 PM PDT 24 |
Mar 10 02:45:37 PM PDT 24 |
3385019576 ps |
| T16 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.1988129880 |
|
|
Mar 10 02:35:57 PM PDT 24 |
Mar 10 02:51:16 PM PDT 24 |
70184635563 ps |
| T169 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.541596348 |
|
|
Mar 10 02:41:05 PM PDT 24 |
Mar 10 02:41:10 PM PDT 24 |
229839855 ps |
| T156 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3991720195 |
|
|
Mar 10 02:35:46 PM PDT 24 |
Mar 10 02:45:47 PM PDT 24 |
1818667374 ps |
| T161 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.2976439949 |
|
|
Mar 10 02:40:42 PM PDT 24 |
Mar 10 02:42:15 PM PDT 24 |
119326878 ps |
| T27 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.430364730 |
|
|
Mar 10 02:38:17 PM PDT 24 |
Mar 10 02:51:44 PM PDT 24 |
17445387741 ps |
| T52 |
/workspace/coverage/default/29.sram_ctrl_executable.3326939901 |
|
|
Mar 10 02:38:42 PM PDT 24 |
Mar 10 02:59:08 PM PDT 24 |
3974303662 ps |
| T53 |
/workspace/coverage/default/18.sram_ctrl_executable.2304279298 |
|
|
Mar 10 02:37:02 PM PDT 24 |
Mar 10 02:49:35 PM PDT 24 |
10534354330 ps |
| T54 |
/workspace/coverage/default/41.sram_ctrl_regwen.401909549 |
|
|
Mar 10 02:40:26 PM PDT 24 |
Mar 10 02:45:42 PM PDT 24 |
8636574042 ps |
| T55 |
/workspace/coverage/default/48.sram_ctrl_partial_access.1441368813 |
|
|
Mar 10 02:41:31 PM PDT 24 |
Mar 10 02:41:37 PM PDT 24 |
173553946 ps |
| T56 |
/workspace/coverage/default/9.sram_ctrl_bijection.2619973827 |
|
|
Mar 10 02:35:47 PM PDT 24 |
Mar 10 02:36:55 PM PDT 24 |
6686788765 ps |
| T18 |
/workspace/coverage/default/4.sram_ctrl_alert_test.4287232036 |
|
|
Mar 10 02:35:19 PM PDT 24 |
Mar 10 02:35:19 PM PDT 24 |
26229124 ps |
| T19 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1652916511 |
|
|
Mar 10 02:35:45 PM PDT 24 |
Mar 10 02:35:49 PM PDT 24 |
19893323 ps |
| T57 |
/workspace/coverage/default/27.sram_ctrl_smoke.2948518787 |
|
|
Mar 10 02:38:19 PM PDT 24 |
Mar 10 02:38:23 PM PDT 24 |
276015342 ps |
| T58 |
/workspace/coverage/default/5.sram_ctrl_alert_test.2510897332 |
|
|
Mar 10 02:35:26 PM PDT 24 |
Mar 10 02:35:27 PM PDT 24 |
26989736 ps |
| T170 |
/workspace/coverage/default/21.sram_ctrl_alert_test.771546806 |
|
|
Mar 10 02:37:42 PM PDT 24 |
Mar 10 02:37:42 PM PDT 24 |
20168721 ps |
| T157 |
/workspace/coverage/default/40.sram_ctrl_smoke.3822503482 |
|
|
Mar 10 02:40:10 PM PDT 24 |
Mar 10 02:40:15 PM PDT 24 |
279459889 ps |
| T79 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.2866593327 |
|
|
Mar 10 02:36:30 PM PDT 24 |
Mar 10 02:36:33 PM PDT 24 |
175777937 ps |
| T171 |
/workspace/coverage/default/34.sram_ctrl_bijection.1372742495 |
|
|
Mar 10 02:39:19 PM PDT 24 |
Mar 10 02:39:45 PM PDT 24 |
7305745147 ps |
| T143 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.4229226256 |
|
|
Mar 10 02:40:52 PM PDT 24 |
Mar 10 02:50:17 PM PDT 24 |
22999081551 ps |
| T140 |
/workspace/coverage/default/16.sram_ctrl_stress_all.3395120516 |
|
|
Mar 10 02:36:44 PM PDT 24 |
Mar 10 02:47:44 PM PDT 24 |
16810209348 ps |
| T172 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2820442490 |
|
|
Mar 10 02:35:49 PM PDT 24 |
Mar 10 02:37:35 PM PDT 24 |
565265338 ps |
| T135 |
/workspace/coverage/default/6.sram_ctrl_executable.2995697942 |
|
|
Mar 10 02:35:31 PM PDT 24 |
Mar 10 02:35:55 PM PDT 24 |
438468077 ps |
| T80 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.4031965148 |
|
|
Mar 10 02:36:39 PM PDT 24 |
Mar 10 03:00:12 PM PDT 24 |
3047683334 ps |
| T136 |
/workspace/coverage/default/3.sram_ctrl_regwen.781263842 |
|
|
Mar 10 02:35:06 PM PDT 24 |
Mar 10 03:01:11 PM PDT 24 |
16804206430 ps |
| T173 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1520884672 |
|
|
Mar 10 02:34:43 PM PDT 24 |
Mar 10 02:56:02 PM PDT 24 |
3117748509 ps |
| T163 |
/workspace/coverage/default/48.sram_ctrl_bijection.3701087331 |
|
|
Mar 10 02:41:25 PM PDT 24 |
Mar 10 02:42:06 PM PDT 24 |
705837791 ps |
| T32 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.1782682994 |
|
|
Mar 10 02:36:39 PM PDT 24 |
Mar 10 02:36:40 PM PDT 24 |
40547388 ps |
| T81 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.2471845463 |
|
|
Mar 10 02:39:10 PM PDT 24 |
Mar 10 02:42:24 PM PDT 24 |
8556209364 ps |
| T174 |
/workspace/coverage/default/22.sram_ctrl_smoke.3127200026 |
|
|
Mar 10 02:37:42 PM PDT 24 |
Mar 10 02:37:55 PM PDT 24 |
474366995 ps |
| T101 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3244835740 |
|
|
Mar 10 02:36:34 PM PDT 24 |
Mar 10 02:42:55 PM PDT 24 |
27705133160 ps |
| T175 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.573110452 |
|
|
Mar 10 02:35:11 PM PDT 24 |
Mar 10 02:35:48 PM PDT 24 |
143724654 ps |
| T176 |
/workspace/coverage/default/17.sram_ctrl_alert_test.3802434626 |
|
|
Mar 10 02:36:54 PM PDT 24 |
Mar 10 02:36:55 PM PDT 24 |
34982039 ps |
| T148 |
/workspace/coverage/default/7.sram_ctrl_bijection.398825736 |
|
|
Mar 10 02:35:31 PM PDT 24 |
Mar 10 02:36:04 PM PDT 24 |
12142688504 ps |
| T82 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.811277506 |
|
|
Mar 10 02:36:03 PM PDT 24 |
Mar 10 02:36:08 PM PDT 24 |
157182934 ps |
| T159 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1228919950 |
|
|
Mar 10 02:38:18 PM PDT 24 |
Mar 10 02:39:01 PM PDT 24 |
413551219 ps |
| T177 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.2089334916 |
|
|
Mar 10 02:41:00 PM PDT 24 |
Mar 10 02:41:16 PM PDT 24 |
268807177 ps |
| T122 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1741714939 |
|
|
Mar 10 02:39:17 PM PDT 24 |
Mar 10 02:39:38 PM PDT 24 |
1959484467 ps |
| T178 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.639154961 |
|
|
Mar 10 02:38:08 PM PDT 24 |
Mar 10 02:38:10 PM PDT 24 |
82292556 ps |
| T152 |
/workspace/coverage/default/3.sram_ctrl_smoke.4102215959 |
|
|
Mar 10 02:35:03 PM PDT 24 |
Mar 10 02:35:11 PM PDT 24 |
385951199 ps |
| T162 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.1122933226 |
|
|
Mar 10 02:41:15 PM PDT 24 |
Mar 10 02:43:49 PM PDT 24 |
512130075 ps |
| T153 |
/workspace/coverage/default/9.sram_ctrl_executable.132948384 |
|
|
Mar 10 02:35:46 PM PDT 24 |
Mar 10 02:38:43 PM PDT 24 |
5937097936 ps |
| T179 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.2842800573 |
|
|
Mar 10 02:36:00 PM PDT 24 |
Mar 10 02:36:30 PM PDT 24 |
303292777 ps |
| T180 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3273424787 |
|
|
Mar 10 02:40:57 PM PDT 24 |
Mar 10 02:41:02 PM PDT 24 |
311082737 ps |
| T181 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.1920996549 |
|
|
Mar 10 02:40:10 PM PDT 24 |
Mar 10 02:40:18 PM PDT 24 |
155176223 ps |
| T142 |
/workspace/coverage/default/29.sram_ctrl_partial_access.3250134080 |
|
|
Mar 10 02:38:39 PM PDT 24 |
Mar 10 02:38:55 PM PDT 24 |
4630354279 ps |
| T182 |
/workspace/coverage/default/44.sram_ctrl_regwen.3910340977 |
|
|
Mar 10 02:40:55 PM PDT 24 |
Mar 10 03:02:28 PM PDT 24 |
2646899329 ps |
| T183 |
/workspace/coverage/default/30.sram_ctrl_smoke.2150287603 |
|
|
Mar 10 02:38:50 PM PDT 24 |
Mar 10 02:40:29 PM PDT 24 |
479632754 ps |
| T83 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1559588682 |
|
|
Mar 10 02:40:26 PM PDT 24 |
Mar 10 03:19:31 PM PDT 24 |
15474262879 ps |
| T149 |
/workspace/coverage/default/25.sram_ctrl_alert_test.2212714182 |
|
|
Mar 10 02:38:14 PM PDT 24 |
Mar 10 02:38:15 PM PDT 24 |
37267835 ps |
| T184 |
/workspace/coverage/default/18.sram_ctrl_partial_access.1571379590 |
|
|
Mar 10 02:37:02 PM PDT 24 |
Mar 10 02:37:04 PM PDT 24 |
66757740 ps |
| T134 |
/workspace/coverage/default/5.sram_ctrl_stress_all.2462392414 |
|
|
Mar 10 02:35:28 PM PDT 24 |
Mar 10 04:00:57 PM PDT 24 |
74791384871 ps |
| T185 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.761173003 |
|
|
Mar 10 02:38:17 PM PDT 24 |
Mar 10 02:38:21 PM PDT 24 |
148898283 ps |
| T186 |
/workspace/coverage/default/12.sram_ctrl_bijection.1927011104 |
|
|
Mar 10 02:36:08 PM PDT 24 |
Mar 10 02:36:50 PM PDT 24 |
5334337747 ps |
| T187 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2970421251 |
|
|
Mar 10 02:35:45 PM PDT 24 |
Mar 10 02:35:47 PM PDT 24 |
45604589 ps |
| T188 |
/workspace/coverage/default/48.sram_ctrl_smoke.698065479 |
|
|
Mar 10 02:41:23 PM PDT 24 |
Mar 10 02:42:39 PM PDT 24 |
572416951 ps |
| T189 |
/workspace/coverage/default/24.sram_ctrl_smoke.737289206 |
|
|
Mar 10 02:38:10 PM PDT 24 |
Mar 10 02:38:11 PM PDT 24 |
248505329 ps |
| T190 |
/workspace/coverage/default/33.sram_ctrl_bijection.2945106801 |
|
|
Mar 10 02:39:04 PM PDT 24 |
Mar 10 02:39:49 PM PDT 24 |
703976116 ps |
| T191 |
/workspace/coverage/default/40.sram_ctrl_regwen.2104207996 |
|
|
Mar 10 02:40:23 PM PDT 24 |
Mar 10 02:50:03 PM PDT 24 |
41802997778 ps |
| T84 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.1638423458 |
|
|
Mar 10 02:39:01 PM PDT 24 |
Mar 10 02:52:52 PM PDT 24 |
3873285049 ps |
| T150 |
/workspace/coverage/default/46.sram_ctrl_executable.260765935 |
|
|
Mar 10 02:41:13 PM PDT 24 |
Mar 10 03:02:59 PM PDT 24 |
3849423083 ps |
| T192 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.725753119 |
|
|
Mar 10 02:39:32 PM PDT 24 |
Mar 10 02:39:36 PM PDT 24 |
51205742 ps |
| T193 |
/workspace/coverage/default/14.sram_ctrl_bijection.900616764 |
|
|
Mar 10 02:36:24 PM PDT 24 |
Mar 10 02:36:58 PM PDT 24 |
540195001 ps |
| T194 |
/workspace/coverage/default/17.sram_ctrl_executable.3751035978 |
|
|
Mar 10 02:36:54 PM PDT 24 |
Mar 10 02:38:35 PM PDT 24 |
1955300051 ps |
| T141 |
/workspace/coverage/default/7.sram_ctrl_stress_all.2129030501 |
|
|
Mar 10 02:35:48 PM PDT 24 |
Mar 10 03:29:46 PM PDT 24 |
42548927001 ps |
| T195 |
/workspace/coverage/default/47.sram_ctrl_smoke.339061525 |
|
|
Mar 10 02:41:19 PM PDT 24 |
Mar 10 02:42:38 PM PDT 24 |
7134496956 ps |
| T196 |
/workspace/coverage/default/49.sram_ctrl_smoke.1013340677 |
|
|
Mar 10 02:41:35 PM PDT 24 |
Mar 10 02:41:45 PM PDT 24 |
1895284983 ps |
| T197 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.232821325 |
|
|
Mar 10 02:39:09 PM PDT 24 |
Mar 10 02:40:09 PM PDT 24 |
450613049 ps |
| T198 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.1691837129 |
|
|
Mar 10 02:37:16 PM PDT 24 |
Mar 10 03:00:59 PM PDT 24 |
31160332265 ps |
| T199 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.2826928811 |
|
|
Mar 10 02:40:46 PM PDT 24 |
Mar 10 02:40:57 PM PDT 24 |
3303763500 ps |
| T200 |
/workspace/coverage/default/42.sram_ctrl_partial_access.678996535 |
|
|
Mar 10 02:40:32 PM PDT 24 |
Mar 10 02:40:37 PM PDT 24 |
991983439 ps |
| T120 |
/workspace/coverage/default/45.sram_ctrl_stress_all.1595156625 |
|
|
Mar 10 02:41:08 PM PDT 24 |
Mar 10 03:17:22 PM PDT 24 |
36574404279 ps |
| T201 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2528912869 |
|
|
Mar 10 02:36:02 PM PDT 24 |
Mar 10 02:51:20 PM PDT 24 |
2596977316 ps |
| T202 |
/workspace/coverage/default/48.sram_ctrl_stress_all.434580221 |
|
|
Mar 10 02:41:35 PM PDT 24 |
Mar 10 03:55:01 PM PDT 24 |
42498449579 ps |
| T102 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3333538681 |
|
|
Mar 10 02:40:51 PM PDT 24 |
Mar 10 02:45:22 PM PDT 24 |
11275067039 ps |
| T203 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.2419963094 |
|
|
Mar 10 02:37:36 PM PDT 24 |
Mar 10 02:55:36 PM PDT 24 |
17217219825 ps |
| T204 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.1700259069 |
|
|
Mar 10 02:36:29 PM PDT 24 |
Mar 10 02:36:38 PM PDT 24 |
261962977 ps |
| T205 |
/workspace/coverage/default/1.sram_ctrl_executable.3203287880 |
|
|
Mar 10 02:34:52 PM PDT 24 |
Mar 10 02:46:35 PM PDT 24 |
4381403435 ps |
| T206 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3063310813 |
|
|
Mar 10 02:35:21 PM PDT 24 |
Mar 10 02:40:20 PM PDT 24 |
5837350341 ps |
| T207 |
/workspace/coverage/default/21.sram_ctrl_executable.892622771 |
|
|
Mar 10 02:37:29 PM PDT 24 |
Mar 10 02:50:03 PM PDT 24 |
8308131193 ps |
| T158 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.2546731316 |
|
|
Mar 10 02:38:27 PM PDT 24 |
Mar 10 02:59:47 PM PDT 24 |
3510823098 ps |
| T208 |
/workspace/coverage/default/2.sram_ctrl_regwen.368214175 |
|
|
Mar 10 02:35:01 PM PDT 24 |
Mar 10 02:49:55 PM PDT 24 |
59951246449 ps |
| T209 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2533143482 |
|
|
Mar 10 02:36:08 PM PDT 24 |
Mar 10 02:51:03 PM PDT 24 |
2988936315 ps |
| T210 |
/workspace/coverage/default/24.sram_ctrl_alert_test.3305692011 |
|
|
Mar 10 02:38:14 PM PDT 24 |
Mar 10 02:38:15 PM PDT 24 |
43876754 ps |
| T121 |
/workspace/coverage/default/41.sram_ctrl_lc_escalation.730124940 |
|
|
Mar 10 02:40:28 PM PDT 24 |
Mar 10 02:40:43 PM PDT 24 |
802556180 ps |
| T211 |
/workspace/coverage/default/6.sram_ctrl_smoke.4148163467 |
|
|
Mar 10 02:35:27 PM PDT 24 |
Mar 10 02:35:31 PM PDT 24 |
134390488 ps |
| T212 |
/workspace/coverage/default/33.sram_ctrl_executable.2332375765 |
|
|
Mar 10 02:39:08 PM PDT 24 |
Mar 10 02:50:29 PM PDT 24 |
14689766047 ps |
| T25 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.341242760 |
|
|
Mar 10 02:38:30 PM PDT 24 |
Mar 10 02:38:43 PM PDT 24 |
724838773 ps |
| T213 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.4257665367 |
|
|
Mar 10 02:37:20 PM PDT 24 |
Mar 10 02:37:30 PM PDT 24 |
2754273741 ps |
| T214 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.2050097561 |
|
|
Mar 10 02:37:42 PM PDT 24 |
Mar 10 02:41:06 PM PDT 24 |
15090157172 ps |
| T215 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.2243939246 |
|
|
Mar 10 02:38:38 PM PDT 24 |
Mar 10 02:43:02 PM PDT 24 |
20508102591 ps |
| T216 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.1583140399 |
|
|
Mar 10 02:35:00 PM PDT 24 |
Mar 10 02:42:45 PM PDT 24 |
1763445787 ps |
| T217 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.3477667764 |
|
|
Mar 10 02:38:51 PM PDT 24 |
Mar 10 02:47:01 PM PDT 24 |
6304531670 ps |
| T154 |
/workspace/coverage/default/31.sram_ctrl_regwen.3795993901 |
|
|
Mar 10 02:38:55 PM PDT 24 |
Mar 10 02:55:37 PM PDT 24 |
11881076196 ps |
| T218 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.2946469985 |
|
|
Mar 10 02:35:17 PM PDT 24 |
Mar 10 02:35:18 PM PDT 24 |
71805638 ps |
| T219 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1882460148 |
|
|
Mar 10 02:40:57 PM PDT 24 |
Mar 10 02:40:59 PM PDT 24 |
499043791 ps |
| T220 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.2215733396 |
|
|
Mar 10 02:37:33 PM PDT 24 |
Mar 10 02:37:35 PM PDT 24 |
42918898 ps |
| T144 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.2392911264 |
|
|
Mar 10 02:39:08 PM PDT 24 |
Mar 10 02:39:21 PM PDT 24 |
1152057315 ps |
| T145 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.2066601133 |
|
|
Mar 10 02:35:12 PM PDT 24 |
Mar 10 02:35:23 PM PDT 24 |
514959191 ps |
| T221 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3375982244 |
|
|
Mar 10 02:37:04 PM PDT 24 |
Mar 10 02:38:28 PM PDT 24 |
1524593659 ps |
| T222 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3914919951 |
|
|
Mar 10 02:40:32 PM PDT 24 |
Mar 10 02:40:45 PM PDT 24 |
72971806 ps |
| T223 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.1605983426 |
|
|
Mar 10 02:37:29 PM PDT 24 |
Mar 10 02:37:39 PM PDT 24 |
916782570 ps |
| T224 |
/workspace/coverage/default/0.sram_ctrl_stress_all.2062372869 |
|
|
Mar 10 02:34:48 PM PDT 24 |
Mar 10 02:48:57 PM PDT 24 |
20017626964 ps |
| T151 |
/workspace/coverage/default/46.sram_ctrl_alert_test.1030911936 |
|
|
Mar 10 02:41:19 PM PDT 24 |
Mar 10 02:41:20 PM PDT 24 |
16580552 ps |
| T28 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.2276803585 |
|
|
Mar 10 02:35:53 PM PDT 24 |
Mar 10 02:36:53 PM PDT 24 |
769113019 ps |
| T112 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.3178495260 |
|
|
Mar 10 02:36:24 PM PDT 24 |
Mar 10 02:43:35 PM PDT 24 |
6994622016 ps |
| T113 |
/workspace/coverage/default/18.sram_ctrl_alert_test.648377278 |
|
|
Mar 10 02:37:03 PM PDT 24 |
Mar 10 02:37:03 PM PDT 24 |
50693335 ps |
| T26 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.3247037525 |
|
|
Mar 10 02:34:57 PM PDT 24 |
Mar 10 02:35:06 PM PDT 24 |
344307222 ps |
| T114 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.2492662590 |
|
|
Mar 10 02:37:06 PM PDT 24 |
Mar 10 02:37:24 PM PDT 24 |
1303429372 ps |
| T115 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.650331576 |
|
|
Mar 10 02:35:42 PM PDT 24 |
Mar 10 02:36:05 PM PDT 24 |
1539829849 ps |
| T116 |
/workspace/coverage/default/1.sram_ctrl_regwen.2782566876 |
|
|
Mar 10 02:34:53 PM PDT 24 |
Mar 10 02:41:36 PM PDT 24 |
34915547052 ps |
| T117 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.653116146 |
|
|
Mar 10 02:35:52 PM PDT 24 |
Mar 10 02:36:02 PM PDT 24 |
2330567376 ps |
| T118 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.3289405482 |
|
|
Mar 10 02:37:09 PM PDT 24 |
Mar 10 02:37:19 PM PDT 24 |
2748037321 ps |
| T119 |
/workspace/coverage/default/40.sram_ctrl_executable.4206577228 |
|
|
Mar 10 02:40:15 PM PDT 24 |
Mar 10 02:59:34 PM PDT 24 |
10149367469 ps |
| T225 |
/workspace/coverage/default/10.sram_ctrl_partial_access.638094606 |
|
|
Mar 10 02:35:52 PM PDT 24 |
Mar 10 02:37:12 PM PDT 24 |
539826649 ps |
| T226 |
/workspace/coverage/default/20.sram_ctrl_smoke.1464746378 |
|
|
Mar 10 02:37:17 PM PDT 24 |
Mar 10 02:37:33 PM PDT 24 |
3287844344 ps |
| T227 |
/workspace/coverage/default/1.sram_ctrl_alert_test.4138221599 |
|
|
Mar 10 02:34:57 PM PDT 24 |
Mar 10 02:34:59 PM PDT 24 |
11021591 ps |
| T137 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.1253185580 |
|
|
Mar 10 02:37:00 PM PDT 24 |
Mar 10 02:42:27 PM PDT 24 |
25426093189 ps |
| T228 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.3843148171 |
|
|
Mar 10 02:37:30 PM PDT 24 |
Mar 10 02:38:09 PM PDT 24 |
354430979 ps |
| T229 |
/workspace/coverage/default/22.sram_ctrl_regwen.3571998844 |
|
|
Mar 10 02:37:34 PM PDT 24 |
Mar 10 02:44:51 PM PDT 24 |
1798531604 ps |
| T138 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2099733379 |
|
|
Mar 10 02:35:37 PM PDT 24 |
Mar 10 02:44:26 PM PDT 24 |
93988184192 ps |
| T29 |
/workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.1626331481 |
|
|
Mar 10 02:40:09 PM PDT 24 |
Mar 10 02:45:07 PM PDT 24 |
1155478823 ps |
| T230 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.965473046 |
|
|
Mar 10 02:38:28 PM PDT 24 |
Mar 10 02:38:31 PM PDT 24 |
169100339 ps |
| T231 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.1818514169 |
|
|
Mar 10 02:37:01 PM PDT 24 |
Mar 10 02:37:02 PM PDT 24 |
189277730 ps |
| T232 |
/workspace/coverage/default/23.sram_ctrl_regwen.619798409 |
|
|
Mar 10 02:38:11 PM PDT 24 |
Mar 10 02:42:58 PM PDT 24 |
15767375265 ps |
| T233 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1888799442 |
|
|
Mar 10 02:40:27 PM PDT 24 |
Mar 10 02:42:12 PM PDT 24 |
528469350 ps |
| T234 |
/workspace/coverage/default/20.sram_ctrl_stress_all.740993696 |
|
|
Mar 10 02:37:22 PM PDT 24 |
Mar 10 04:01:30 PM PDT 24 |
160799061658 ps |
| T235 |
/workspace/coverage/default/37.sram_ctrl_bijection.753154537 |
|
|
Mar 10 02:39:42 PM PDT 24 |
Mar 10 02:40:27 PM PDT 24 |
9982781303 ps |
| T236 |
/workspace/coverage/default/47.sram_ctrl_executable.456501732 |
|
|
Mar 10 02:41:25 PM PDT 24 |
Mar 10 02:59:52 PM PDT 24 |
10962554956 ps |
| T237 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2235667773 |
|
|
Mar 10 02:41:15 PM PDT 24 |
Mar 10 02:41:17 PM PDT 24 |
91799751 ps |
| T238 |
/workspace/coverage/default/42.sram_ctrl_regwen.1310164282 |
|
|
Mar 10 02:40:38 PM PDT 24 |
Mar 10 02:48:37 PM PDT 24 |
10817496568 ps |
| T239 |
/workspace/coverage/default/29.sram_ctrl_stress_all.1591646059 |
|
|
Mar 10 02:38:49 PM PDT 24 |
Mar 10 03:31:55 PM PDT 24 |
62802199739 ps |
| T240 |
/workspace/coverage/default/48.sram_ctrl_executable.2704055589 |
|
|
Mar 10 02:41:36 PM PDT 24 |
Mar 10 03:24:11 PM PDT 24 |
4694964283 ps |
| T241 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.1373715206 |
|
|
Mar 10 02:40:06 PM PDT 24 |
Mar 10 02:40:53 PM PDT 24 |
470822533 ps |
| T242 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.3011704906 |
|
|
Mar 10 02:38:19 PM PDT 24 |
Mar 10 02:38:39 PM PDT 24 |
84650454 ps |
| T243 |
/workspace/coverage/default/39.sram_ctrl_smoke.3373891913 |
|
|
Mar 10 02:40:00 PM PDT 24 |
Mar 10 02:40:11 PM PDT 24 |
194175510 ps |
| T244 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.814696505 |
|
|
Mar 10 02:34:49 PM PDT 24 |
Mar 10 02:41:04 PM PDT 24 |
26649314948 ps |
| T245 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.460456165 |
|
|
Mar 10 02:39:40 PM PDT 24 |
Mar 10 02:39:49 PM PDT 24 |
370512187 ps |
| T45 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.405114070 |
|
|
Mar 10 02:37:03 PM PDT 24 |
Mar 10 02:38:22 PM PDT 24 |
913838420 ps |
| T246 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.4254774550 |
|
|
Mar 10 02:35:46 PM PDT 24 |
Mar 10 02:38:41 PM PDT 24 |
7113702329 ps |
| T247 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.3368685689 |
|
|
Mar 10 02:35:07 PM PDT 24 |
Mar 10 02:38:03 PM PDT 24 |
5089118875 ps |
| T248 |
/workspace/coverage/default/0.sram_ctrl_executable.2898774184 |
|
|
Mar 10 02:34:47 PM PDT 24 |
Mar 10 02:37:44 PM PDT 24 |
1660888766 ps |
| T249 |
/workspace/coverage/default/22.sram_ctrl_bijection.160964653 |
|
|
Mar 10 02:37:35 PM PDT 24 |
Mar 10 02:38:53 PM PDT 24 |
3648502963 ps |
| T250 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.438368563 |
|
|
Mar 10 02:38:03 PM PDT 24 |
Mar 10 02:51:11 PM PDT 24 |
1909604714 ps |
| T251 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.4218988331 |
|
|
Mar 10 02:35:07 PM PDT 24 |
Mar 10 02:35:08 PM PDT 24 |
28040435 ps |
| T252 |
/workspace/coverage/default/24.sram_ctrl_executable.2551187481 |
|
|
Mar 10 02:38:10 PM PDT 24 |
Mar 10 03:06:13 PM PDT 24 |
5861692999 ps |
| T253 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.189032433 |
|
|
Mar 10 02:35:24 PM PDT 24 |
Mar 10 02:35:25 PM PDT 24 |
51798265 ps |
| T254 |
/workspace/coverage/default/37.sram_ctrl_executable.3136714211 |
|
|
Mar 10 02:39:46 PM PDT 24 |
Mar 10 02:56:06 PM PDT 24 |
33164887944 ps |
| T255 |
/workspace/coverage/default/47.sram_ctrl_alert_test.905481922 |
|
|
Mar 10 02:41:22 PM PDT 24 |
Mar 10 02:41:23 PM PDT 24 |
27881929 ps |
| T256 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.967709419 |
|
|
Mar 10 02:35:45 PM PDT 24 |
Mar 10 02:35:56 PM PDT 24 |
1841108877 ps |
| T257 |
/workspace/coverage/default/32.sram_ctrl_executable.2344223636 |
|
|
Mar 10 02:39:01 PM PDT 24 |
Mar 10 02:46:54 PM PDT 24 |
9090013855 ps |
| T258 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.3336795588 |
|
|
Mar 10 02:39:31 PM PDT 24 |
Mar 10 02:39:59 PM PDT 24 |
626577891 ps |
| T259 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.2066541265 |
|
|
Mar 10 02:41:28 PM PDT 24 |
Mar 10 02:42:55 PM PDT 24 |
410234121 ps |
| T20 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.419239789 |
|
|
Mar 10 02:35:12 PM PDT 24 |
Mar 10 02:35:14 PM PDT 24 |
131355758 ps |
| T35 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.27508577 |
|
|
Mar 10 02:36:12 PM PDT 24 |
Mar 10 02:42:20 PM PDT 24 |
56669303746 ps |
| T36 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.3317503891 |
|
|
Mar 10 02:36:28 PM PDT 24 |
Mar 10 02:36:29 PM PDT 24 |
35384786 ps |
| T37 |
/workspace/coverage/default/15.sram_ctrl_executable.704610987 |
|
|
Mar 10 02:36:33 PM PDT 24 |
Mar 10 02:53:33 PM PDT 24 |
45476216667 ps |
| T38 |
/workspace/coverage/default/39.sram_ctrl_regwen.2672971412 |
|
|
Mar 10 02:40:10 PM PDT 24 |
Mar 10 02:51:04 PM PDT 24 |
1866692186 ps |
| T39 |
/workspace/coverage/default/46.sram_ctrl_stress_all.2100012048 |
|
|
Mar 10 02:41:22 PM PDT 24 |
Mar 10 03:40:30 PM PDT 24 |
123267504658 ps |
| T40 |
/workspace/coverage/default/19.sram_ctrl_partial_access.3635933516 |
|
|
Mar 10 02:37:03 PM PDT 24 |
Mar 10 02:37:13 PM PDT 24 |
842643499 ps |
| T41 |
/workspace/coverage/default/15.sram_ctrl_smoke.112720165 |
|
|
Mar 10 02:36:29 PM PDT 24 |
Mar 10 02:36:31 PM PDT 24 |
463323583 ps |
| T42 |
/workspace/coverage/default/44.sram_ctrl_smoke.946782453 |
|
|
Mar 10 02:40:51 PM PDT 24 |
Mar 10 02:40:58 PM PDT 24 |
472525154 ps |
| T43 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.1043716774 |
|
|
Mar 10 02:39:36 PM PDT 24 |
Mar 10 02:39:49 PM PDT 24 |
794046234 ps |
| T260 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3136272566 |
|
|
Mar 10 02:40:15 PM PDT 24 |
Mar 10 02:44:13 PM PDT 24 |
17672239607 ps |
| T261 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.1924192904 |
|
|
Mar 10 02:37:09 PM PDT 24 |
Mar 10 02:51:33 PM PDT 24 |
2651627651 ps |
| T262 |
/workspace/coverage/default/38.sram_ctrl_bijection.2132532931 |
|
|
Mar 10 02:39:50 PM PDT 24 |
Mar 10 02:40:47 PM PDT 24 |
875814676 ps |
| T263 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.4163876459 |
|
|
Mar 10 02:35:25 PM PDT 24 |
Mar 10 02:37:36 PM PDT 24 |
5748131440 ps |
| T264 |
/workspace/coverage/default/30.sram_ctrl_partial_access.2546729969 |
|
|
Mar 10 02:38:48 PM PDT 24 |
Mar 10 02:39:15 PM PDT 24 |
333810568 ps |
| T265 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.953422654 |
|
|
Mar 10 02:35:58 PM PDT 24 |
Mar 10 02:36:08 PM PDT 24 |
773159766 ps |
| T266 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1800004152 |
|
|
Mar 10 02:36:09 PM PDT 24 |
Mar 10 02:36:13 PM PDT 24 |
282567294 ps |
| T267 |
/workspace/coverage/default/47.sram_ctrl_partial_access.2848006650 |
|
|
Mar 10 02:41:20 PM PDT 24 |
Mar 10 02:41:34 PM PDT 24 |
744238044 ps |
| T268 |
/workspace/coverage/default/32.sram_ctrl_max_throughput.1809196329 |
|
|
Mar 10 02:39:01 PM PDT 24 |
Mar 10 02:39:10 PM PDT 24 |
239419617 ps |
| T269 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1503810781 |
|
|
Mar 10 02:37:03 PM PDT 24 |
Mar 10 02:41:35 PM PDT 24 |
14363055067 ps |
| T270 |
/workspace/coverage/default/32.sram_ctrl_partial_access.2578159791 |
|
|
Mar 10 02:39:02 PM PDT 24 |
Mar 10 02:39:14 PM PDT 24 |
1292130010 ps |
| T271 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.555482405 |
|
|
Mar 10 02:39:51 PM PDT 24 |
Mar 10 02:41:40 PM PDT 24 |
565374098 ps |
| T272 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.33122689 |
|
|
Mar 10 02:35:49 PM PDT 24 |
Mar 10 02:41:45 PM PDT 24 |
13373691861 ps |
| T273 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.248567535 |
|
|
Mar 10 02:41:28 PM PDT 24 |
Mar 10 02:45:57 PM PDT 24 |
5945004294 ps |
| T274 |
/workspace/coverage/default/26.sram_ctrl_executable.1332105955 |
|
|
Mar 10 02:38:17 PM PDT 24 |
Mar 10 02:52:55 PM PDT 24 |
6237373386 ps |
| T275 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.4259487447 |
|
|
Mar 10 02:37:40 PM PDT 24 |
Mar 10 02:54:07 PM PDT 24 |
17525675260 ps |
| T276 |
/workspace/coverage/default/39.sram_ctrl_executable.1947588964 |
|
|
Mar 10 02:40:10 PM PDT 24 |
Mar 10 02:49:48 PM PDT 24 |
2468025598 ps |
| T46 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3747087613 |
|
|
Mar 10 02:38:16 PM PDT 24 |
Mar 10 02:51:46 PM PDT 24 |
3415562390 ps |
| T277 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.3998115287 |
|
|
Mar 10 02:36:46 PM PDT 24 |
Mar 10 02:36:49 PM PDT 24 |
96697000 ps |
| T278 |
/workspace/coverage/default/21.sram_ctrl_partial_access.1047685715 |
|
|
Mar 10 02:37:26 PM PDT 24 |
Mar 10 02:37:28 PM PDT 24 |
76587054 ps |
| T279 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.3205489039 |
|
|
Mar 10 02:38:43 PM PDT 24 |
Mar 10 02:38:44 PM PDT 24 |
73956291 ps |
| T280 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.941853841 |
|
|
Mar 10 02:36:09 PM PDT 24 |
Mar 10 02:36:11 PM PDT 24 |
67478610 ps |
| T281 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.1874978238 |
|
|
Mar 10 02:38:49 PM PDT 24 |
Mar 10 02:38:54 PM PDT 24 |
609438645 ps |
| T282 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.2726373906 |
|
|
Mar 10 02:39:36 PM PDT 24 |
Mar 10 02:39:41 PM PDT 24 |
78502721 ps |
| T283 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1767159445 |
|
|
Mar 10 02:38:14 PM PDT 24 |
Mar 10 02:43:44 PM PDT 24 |
26212968219 ps |
| T284 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.2434814487 |
|
|
Mar 10 02:38:09 PM PDT 24 |
Mar 10 02:38:18 PM PDT 24 |
1245245145 ps |
| T285 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.2167072370 |
|
|
Mar 10 02:39:50 PM PDT 24 |
Mar 10 02:48:47 PM PDT 24 |
4850864753 ps |
| T286 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3103054676 |
|
|
Mar 10 02:35:13 PM PDT 24 |
Mar 10 02:35:41 PM PDT 24 |
838575043 ps |
| T287 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.1260514783 |
|
|
Mar 10 02:40:04 PM PDT 24 |
Mar 10 02:51:51 PM PDT 24 |
3273887775 ps |
| T288 |
/workspace/coverage/default/17.sram_ctrl_regwen.4270978100 |
|
|
Mar 10 02:36:54 PM PDT 24 |
Mar 10 03:00:31 PM PDT 24 |
32025281747 ps |
| T289 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.118791191 |
|
|
Mar 10 02:35:19 PM PDT 24 |
Mar 10 02:35:22 PM PDT 24 |
88334897 ps |
| T290 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.1847724791 |
|
|
Mar 10 02:37:29 PM PDT 24 |
Mar 10 03:14:36 PM PDT 24 |
8718893460 ps |
| T291 |
/workspace/coverage/default/11.sram_ctrl_stress_all.2028552176 |
|
|
Mar 10 02:36:02 PM PDT 24 |
Mar 10 03:50:17 PM PDT 24 |
43696176033 ps |
| T292 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.3067412889 |
|
|
Mar 10 02:38:52 PM PDT 24 |
Mar 10 02:38:58 PM PDT 24 |
2500511309 ps |
| T293 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.2779029688 |
|
|
Mar 10 02:38:46 PM PDT 24 |
Mar 10 02:43:22 PM PDT 24 |
23218412757 ps |
| T294 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1772470546 |
|
|
Mar 10 02:35:45 PM PDT 24 |
Mar 10 02:35:49 PM PDT 24 |
106427648 ps |
| T295 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.4228498695 |
|
|
Mar 10 02:40:52 PM PDT 24 |
Mar 10 02:41:33 PM PDT 24 |
358620987 ps |
| T296 |
/workspace/coverage/default/20.sram_ctrl_executable.1539431178 |
|
|
Mar 10 02:37:20 PM PDT 24 |
Mar 10 02:43:54 PM PDT 24 |
5425830807 ps |
| T297 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.1413445911 |
|
|
Mar 10 02:38:51 PM PDT 24 |
Mar 10 03:01:21 PM PDT 24 |
26791929569 ps |
| T298 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.3117680947 |
|
|
Mar 10 02:35:26 PM PDT 24 |
Mar 10 02:35:36 PM PDT 24 |
687526277 ps |
| T299 |
/workspace/coverage/default/42.sram_ctrl_alert_test.3567418402 |
|
|
Mar 10 02:40:42 PM PDT 24 |
Mar 10 02:40:43 PM PDT 24 |
40798874 ps |
| T300 |
/workspace/coverage/default/23.sram_ctrl_smoke.2080540815 |
|
|
Mar 10 02:37:39 PM PDT 24 |
Mar 10 02:37:53 PM PDT 24 |
2607376470 ps |
| T301 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.3910797058 |
|
|
Mar 10 02:40:11 PM PDT 24 |
Mar 10 03:02:06 PM PDT 24 |
11068372312 ps |
| T302 |
/workspace/coverage/default/15.sram_ctrl_stress_all.575594355 |
|
|
Mar 10 02:36:40 PM PDT 24 |
Mar 10 03:41:13 PM PDT 24 |
347145208268 ps |
| T303 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1067966589 |
|
|
Mar 10 02:36:22 PM PDT 24 |
Mar 10 02:39:39 PM PDT 24 |
51922030432 ps |
| T304 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1979539655 |
|
|
Mar 10 02:35:12 PM PDT 24 |
Mar 10 02:42:08 PM PDT 24 |
6525128929 ps |
| T305 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.82112641 |
|
|
Mar 10 02:39:06 PM PDT 24 |
Mar 10 02:39:08 PM PDT 24 |
86925776 ps |