Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	149550204	1			T1	12410		T2	6142		T3	20000
instr_valid_dis	116579789	1			T1	12410		T2	6142		T3	20000
instr_en	24077683	1			T4	153302		T5	373652		T7	76802

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11494721	1			T4	83898		T5	65054		T7	39256
sram_ifetch_valid_disable	114522009	1			T1	12410		T2	6142		T3	20000
sram_ifetch_enable	23533474	1			T4	282164		T5	236784		T7	273770

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	149550204	1			T1	12410		T2	6142		T3	20000
hw_debug_en_valid_off	114889695	1			T1	12410		T2	6142		T3	20000
hw_debug_en_on	24376278	1			T4	237136		T5	136392		T7	153938

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114522009	1			T1	12410		T2	6142		T3	20000
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102353310	1			T1	12410		T2	6142		T3	20000
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8920252	1			T4	5352		T5	71906		T7	30322
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3702786	1			T5	1464		T7	10908		T27	25958
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1837137	1			T27	25958		T136	18178		T135	21822
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1510265	1			T5	1464		T135	25844		T139	76212
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	5553854	1			T4	83898		T5	63590		T7	28348
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2517428	1			T4	56172		T7	28348		T39	61736
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2289802	1			T5	63590		T39	19258		T8	25798
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8798294	1			T4	38882		T5	13384		T7	74576
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3647352	1			T4	19398		T27	56820		T52	35920
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3689694	1			T5	13384		T7	30322		T39	35688

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	10356268	1			T4	147950		T5	236692		T7	46480
lc_exec_en	10024130	1			T4	114356		T5	59418		T7	51014
valid_exec_dis	111198378	1			T1	12410		T2	6142		T3	20000
invalid_exec_dis	35028195	1			T4	366062		T5	301838		T7	313026