| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.245645126 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2599268007 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2994168740 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1948605562 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3693959151 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.4252973525 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.730534431 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1631428356 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2966138375 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2312864208 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4104061446 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2339488503 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3260244046 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3964731539 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1896283692 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3592066875 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2467466328 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.4042605087 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1456114005 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3553831579 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1561701099 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3597945727 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3926842789 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2978493529 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.258959909 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1825845995 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2001712465 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2974071973 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.4084719732 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3939456797 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2300469158 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1801765722 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1375483624 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.740058598 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3210492509 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.4181736743 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1562262109 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.530128500 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3455383455 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.860708234 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.791751446 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1865583564 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2436233644 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1849080003 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2424942982 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2283208859 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3450212225 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.216143799 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3399388401 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3712487983 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3597565917 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2860206376 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3444832964 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2490077699 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.664806700 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.1309665616 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3818418913 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2087886031 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.728623175 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1094350714 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.1046766882 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4122271492 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.727167063 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1782882411 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1153421935 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2051076096 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.691165268 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3011721627 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1924712845 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2100868321 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.864380554 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3919449436 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.890817909 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1316945209 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1592104771 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1533849856 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2106146780 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.656986394 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1044879706 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.4243857296 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2070960 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3338923590 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.16787342 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2105850915 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2666511399 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3867191395 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.676849127 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3491584201 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2392618792 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.110129039 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2409575791 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3036496748 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3189944682 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.4245486008 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1176980641 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2699180101 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1919509146 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3951228775 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.867590976 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3520248005 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.824013166 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3146367099 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3712099167 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3119138389 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4229463315 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2107373637 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1090456390 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1452368457 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.4194610277 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2133461150 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1169699801 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1565060791 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1913536892 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4280607380 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2963163990 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1325739416 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2167589329 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2183185200 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1067833684 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.208547288 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1720848234 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.46719840 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2799954844 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1944324770 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3144032701 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.659336161 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1790508156 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2483524225 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.3263986418 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.1377790856 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.1970568613 |
| /workspace/coverage/default/0.sram_ctrl_bijection.1178405351 |
| /workspace/coverage/default/0.sram_ctrl_executable.3355496736 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.646648793 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.1501229324 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2923435171 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.2874763095 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.3560090948 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.2343612233 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1017446101 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.1078920911 |
| /workspace/coverage/default/0.sram_ctrl_regwen.1870648514 |
| /workspace/coverage/default/0.sram_ctrl_smoke.1542003438 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.2977838395 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.836037902 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2106617892 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2353281020 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.4019930284 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.3949808870 |
| /workspace/coverage/default/1.sram_ctrl_bijection.2333397262 |
| /workspace/coverage/default/1.sram_ctrl_executable.1487683570 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.2522781928 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.1637918308 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1936548484 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.2656655566 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.3578542464 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.3438377281 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3622664734 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.1027835932 |
| /workspace/coverage/default/1.sram_ctrl_regwen.3143368467 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.133203247 |
| /workspace/coverage/default/1.sram_ctrl_smoke.578119343 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.4014916527 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2100294556 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2183145495 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2412757372 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.1856920873 |
| /workspace/coverage/default/10.sram_ctrl_bijection.89347332 |
| /workspace/coverage/default/10.sram_ctrl_executable.2998241412 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.1668251333 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.256161971 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.937100072 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.2142752546 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.3610744280 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.95878485 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3788653692 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.2305530958 |
| /workspace/coverage/default/10.sram_ctrl_regwen.1586072623 |
| /workspace/coverage/default/10.sram_ctrl_smoke.301742342 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.1823736707 |
| /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.4115246352 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.1486551801 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2450114444 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.865360869 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.574543547 |
| /workspace/coverage/default/11.sram_ctrl_bijection.206689142 |
| /workspace/coverage/default/11.sram_ctrl_executable.1243450326 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.4201308326 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.1118685329 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1204244278 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.1831107456 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.3114575635 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.3572495563 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.90478692 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.1378165920 |
| /workspace/coverage/default/11.sram_ctrl_regwen.1584535663 |
| /workspace/coverage/default/11.sram_ctrl_smoke.1754116711 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.846101626 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3944330539 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.2735082590 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2357175910 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.37838607 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.329115283 |
| /workspace/coverage/default/12.sram_ctrl_bijection.89715720 |
| /workspace/coverage/default/12.sram_ctrl_executable.2467023951 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.215279158 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.4230370137 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.3138143899 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.1179066314 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.1287197319 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.3596716056 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3035087357 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.3986430367 |
| /workspace/coverage/default/12.sram_ctrl_regwen.1108800077 |
| /workspace/coverage/default/12.sram_ctrl_smoke.3316175617 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.1706508017 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1554868936 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.2949273759 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1782688622 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3681626163 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.480638968 |
| /workspace/coverage/default/13.sram_ctrl_bijection.3445620103 |
| /workspace/coverage/default/13.sram_ctrl_executable.2579370490 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.3159244790 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.1151169749 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.458658666 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.1950894952 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.1273297166 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.722804754 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.247917781 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.374731248 |
| /workspace/coverage/default/13.sram_ctrl_regwen.1530406237 |
| /workspace/coverage/default/13.sram_ctrl_smoke.948311162 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.2228476061 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.1443018135 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3931533287 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.4117713985 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2849264714 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.880739472 |
| /workspace/coverage/default/14.sram_ctrl_bijection.1177417498 |
| /workspace/coverage/default/14.sram_ctrl_executable.4230187550 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.1296046566 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.3598943050 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.690620328 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.647992069 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.97785200 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.78260211 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.775752192 |
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| /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.1839214484 |
| /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2026800060 |
| /workspace/coverage/default/43.sram_ctrl_alert_test.577639066 |
| /workspace/coverage/default/43.sram_ctrl_bijection.3909773459 |
| /workspace/coverage/default/43.sram_ctrl_executable.616490599 |
| /workspace/coverage/default/43.sram_ctrl_lc_escalation.3307781098 |
| /workspace/coverage/default/43.sram_ctrl_max_throughput.3977429560 |
| /workspace/coverage/default/43.sram_ctrl_mem_partial_access.2956470113 |
| /workspace/coverage/default/43.sram_ctrl_mem_walk.1476943729 |
| /workspace/coverage/default/43.sram_ctrl_multiple_keys.1371564862 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.2681963818 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3066132786 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.125114138 |
| /workspace/coverage/default/43.sram_ctrl_regwen.322330924 |
| /workspace/coverage/default/43.sram_ctrl_smoke.4071259631 |
| /workspace/coverage/default/43.sram_ctrl_stress_all.3739241274 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2383645707 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2469717367 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3188237724 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1592807288 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.391691585 |
| /workspace/coverage/default/44.sram_ctrl_bijection.2063920518 |
| /workspace/coverage/default/44.sram_ctrl_executable.1659039345 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.1647628255 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.2512962021 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3596784009 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.2317534407 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.1421116510 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.901292310 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.3290541459 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.1694293053 |
| /workspace/coverage/default/44.sram_ctrl_regwen.2000827787 |
| /workspace/coverage/default/44.sram_ctrl_smoke.834216123 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.226597529 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.2896382069 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.2514153861 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.1505949080 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.34582663 |
| /workspace/coverage/default/45.sram_ctrl_bijection.4257197669 |
| /workspace/coverage/default/45.sram_ctrl_executable.3375822804 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.1977046900 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.2540508647 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.4163066489 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.3262991134 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.974943331 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.568518944 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.710285219 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.1600231369 |
| /workspace/coverage/default/45.sram_ctrl_regwen.3123403291 |
| /workspace/coverage/default/45.sram_ctrl_smoke.3220029865 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.2362830932 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1684792872 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.908981748 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1138871682 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2636813825 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.800376330 |
| /workspace/coverage/default/46.sram_ctrl_bijection.925591155 |
| /workspace/coverage/default/46.sram_ctrl_executable.94898083 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.2738937780 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.2192037322 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.1613866512 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.1622264770 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.925149343 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.1893561155 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3209067543 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.2093695308 |
| /workspace/coverage/default/46.sram_ctrl_regwen.2363272033 |
| /workspace/coverage/default/46.sram_ctrl_smoke.254836028 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.2005791336 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2589591770 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1635902098 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3884709395 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2979205548 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.781661136 |
| /workspace/coverage/default/47.sram_ctrl_bijection.936644780 |
| /workspace/coverage/default/47.sram_ctrl_executable.2837968622 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.75791837 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.759554237 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3644423656 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.292637073 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.1440258510 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.111596341 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.1398640497 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.3163131805 |
| /workspace/coverage/default/47.sram_ctrl_regwen.3294321248 |
| /workspace/coverage/default/47.sram_ctrl_smoke.3672974808 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.77255443 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3858953568 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2110616807 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.944658351 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1029723131 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.327996325 |
| /workspace/coverage/default/48.sram_ctrl_bijection.4016028006 |
| /workspace/coverage/default/48.sram_ctrl_executable.937741921 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.2411390436 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.1440689016 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.2512572306 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.505855224 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.4146359770 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.2159495103 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3548593209 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.2302982319 |
| /workspace/coverage/default/48.sram_ctrl_regwen.2510930080 |
| /workspace/coverage/default/48.sram_ctrl_smoke.2513524679 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.784286438 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.92831151 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1797958087 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1165131040 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.3351252045 |
| /workspace/coverage/default/49.sram_ctrl_bijection.1663436444 |
| /workspace/coverage/default/49.sram_ctrl_executable.413111987 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.70109836 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.1956433538 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2682557550 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.1395766489 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.2468981212 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.463587486 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.121161583 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.1202244241 |
| /workspace/coverage/default/49.sram_ctrl_regwen.198515588 |
| /workspace/coverage/default/49.sram_ctrl_smoke.3171397965 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.3251011471 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1371074424 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2489892212 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2313799344 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.2009568882 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.1708738275 |
| /workspace/coverage/default/5.sram_ctrl_bijection.1059531566 |
| /workspace/coverage/default/5.sram_ctrl_executable.3419298624 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.351809053 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.2054998547 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.4083010017 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.389339902 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.223300565 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.3496740488 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2408453383 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.1485622750 |
| /workspace/coverage/default/5.sram_ctrl_regwen.3221040808 |
| /workspace/coverage/default/5.sram_ctrl_smoke.2111565824 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2058873063 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3784915983 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.981199987 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3124322376 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.3012512795 |
| /workspace/coverage/default/6.sram_ctrl_bijection.583028659 |
| /workspace/coverage/default/6.sram_ctrl_executable.1011827385 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.4074371620 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.1811787682 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1044234784 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.3011251522 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.3146549206 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.505374502 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1495716744 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.2567200172 |
| /workspace/coverage/default/6.sram_ctrl_regwen.3085309449 |
| /workspace/coverage/default/6.sram_ctrl_smoke.4208512444 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.2993870603 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1352209495 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.747266886 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.794521929 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.3374509090 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.880823195 |
| /workspace/coverage/default/7.sram_ctrl_bijection.1195012680 |
| /workspace/coverage/default/7.sram_ctrl_executable.2857610188 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.1552754587 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.628283346 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.1406021794 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.1896284977 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.2025821451 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.3553423180 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3723772026 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.3591228731 |
| /workspace/coverage/default/7.sram_ctrl_regwen.243778892 |
| /workspace/coverage/default/7.sram_ctrl_smoke.4060569073 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.2798146840 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.545460254 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1087408481 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2322539261 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.879828043 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.1557779728 |
| /workspace/coverage/default/8.sram_ctrl_bijection.3405466620 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.3795614299 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.824096595 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.962799620 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.50452316 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.17760315 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.3821871176 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4216563142 |
| /workspace/coverage/default/8.sram_ctrl_regwen.896398332 |
| /workspace/coverage/default/8.sram_ctrl_smoke.3913864485 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.4203054942 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3123482529 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.4036169298 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.674924403 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.4171742665 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.3878787007 |
| /workspace/coverage/default/9.sram_ctrl_bijection.465746217 |
| /workspace/coverage/default/9.sram_ctrl_executable.1793707668 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.2144833868 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.4053637765 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.660882831 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.3646503639 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.3538753664 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.1498484006 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.923557505 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.2298478905 |
| /workspace/coverage/default/9.sram_ctrl_regwen.1632078309 |
| /workspace/coverage/default/9.sram_ctrl_smoke.2077477644 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.3438891006 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4091939055 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.256096966 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.677710413 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/22.sram_ctrl_partial_access.2022164459 |
|
|
Mar 17 12:47:28 PM PDT 24 |
Mar 17 12:47:40 PM PDT 24 |
688654095 ps |
| T2 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.164091548 |
|
|
Mar 17 12:48:09 PM PDT 24 |
Mar 17 12:48:14 PM PDT 24 |
78238996 ps |
| T3 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.1151169749 |
|
|
Mar 17 12:47:32 PM PDT 24 |
Mar 17 12:49:18 PM PDT 24 |
541540670 ps |
| T10 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2170066589 |
|
|
Mar 17 12:48:12 PM PDT 24 |
Mar 17 12:48:13 PM PDT 24 |
33726395 ps |
| T11 |
/workspace/coverage/default/8.sram_ctrl_bijection.3405466620 |
|
|
Mar 17 12:47:18 PM PDT 24 |
Mar 17 12:47:39 PM PDT 24 |
1228077274 ps |
| T12 |
/workspace/coverage/default/15.sram_ctrl_alert_test.2000798863 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:47:23 PM PDT 24 |
40775545 ps |
| T4 |
/workspace/coverage/default/5.sram_ctrl_stress_all.4058842548 |
|
|
Mar 17 12:47:19 PM PDT 24 |
Mar 17 01:20:21 PM PDT 24 |
19884464754 ps |
| T5 |
/workspace/coverage/default/36.sram_ctrl_regwen.1813488434 |
|
|
Mar 17 12:48:24 PM PDT 24 |
Mar 17 01:06:29 PM PDT 24 |
10996412657 ps |
| T6 |
/workspace/coverage/default/31.sram_ctrl_partial_access.1438163715 |
|
|
Mar 17 12:48:06 PM PDT 24 |
Mar 17 12:48:20 PM PDT 24 |
303144706 ps |
| T13 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.4253132334 |
|
|
Mar 17 12:47:19 PM PDT 24 |
Mar 17 12:47:22 PM PDT 24 |
31298799 ps |
| T14 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.675520351 |
|
|
Mar 17 12:47:27 PM PDT 24 |
Mar 17 12:47:37 PM PDT 24 |
875978668 ps |
| T7 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3250235596 |
|
|
Mar 17 12:49:06 PM PDT 24 |
Mar 17 01:13:14 PM PDT 24 |
51261467968 ps |
| T15 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.3827793348 |
|
|
Mar 17 12:48:49 PM PDT 24 |
Mar 17 12:48:54 PM PDT 24 |
147946324 ps |
| T16 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1681060651 |
|
|
Mar 17 12:48:11 PM PDT 24 |
Mar 17 12:52:58 PM PDT 24 |
3147570763 ps |
| T17 |
/workspace/coverage/default/28.sram_ctrl_smoke.3585091657 |
|
|
Mar 17 12:47:54 PM PDT 24 |
Mar 17 12:50:10 PM PDT 24 |
198594969 ps |
| T18 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1083769935 |
|
|
Mar 17 12:47:23 PM PDT 24 |
Mar 17 12:48:12 PM PDT 24 |
4245882116 ps |
| T19 |
/workspace/coverage/default/31.sram_ctrl_smoke.2160510476 |
|
|
Mar 17 12:48:03 PM PDT 24 |
Mar 17 12:49:59 PM PDT 24 |
135385760 ps |
| T20 |
/workspace/coverage/default/11.sram_ctrl_partial_access.3572495563 |
|
|
Mar 17 12:47:25 PM PDT 24 |
Mar 17 12:47:35 PM PDT 24 |
447911991 ps |
| T27 |
/workspace/coverage/default/41.sram_ctrl_regwen.1189118162 |
|
|
Mar 17 12:48:59 PM PDT 24 |
Mar 17 12:57:35 PM PDT 24 |
17899239149 ps |
| T49 |
/workspace/coverage/default/6.sram_ctrl_partial_access.505374502 |
|
|
Mar 17 12:47:04 PM PDT 24 |
Mar 17 12:47:16 PM PDT 24 |
91292688 ps |
| T50 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2159495103 |
|
|
Mar 17 12:49:27 PM PDT 24 |
Mar 17 12:49:31 PM PDT 24 |
356295286 ps |
| T51 |
/workspace/coverage/default/17.sram_ctrl_multiple_keys.2503722871 |
|
|
Mar 17 12:47:28 PM PDT 24 |
Mar 17 12:58:24 PM PDT 24 |
20445597689 ps |
| T52 |
/workspace/coverage/default/32.sram_ctrl_regwen.476561411 |
|
|
Mar 17 12:48:10 PM PDT 24 |
Mar 17 12:50:56 PM PDT 24 |
1995503157 ps |
| T21 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.446869998 |
|
|
Mar 17 12:47:46 PM PDT 24 |
Mar 17 12:57:58 PM PDT 24 |
11224048398 ps |
| T30 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.1688466246 |
|
|
Mar 17 12:46:34 PM PDT 24 |
Mar 17 12:46:35 PM PDT 24 |
48412623 ps |
| T66 |
/workspace/coverage/default/8.sram_ctrl_smoke.3913864485 |
|
|
Mar 17 12:47:04 PM PDT 24 |
Mar 17 12:47:13 PM PDT 24 |
188761643 ps |
| T67 |
/workspace/coverage/default/41.sram_ctrl_bijection.3837864711 |
|
|
Mar 17 12:48:52 PM PDT 24 |
Mar 17 12:49:39 PM PDT 24 |
3001969342 ps |
| T9 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.3447111390 |
|
|
Mar 17 12:47:00 PM PDT 24 |
Mar 17 12:47:04 PM PDT 24 |
6113098800 ps |
| T34 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2494629255 |
|
|
Mar 17 12:48:25 PM PDT 24 |
Mar 17 12:55:18 PM PDT 24 |
16757380379 ps |
| T35 |
/workspace/coverage/default/16.sram_ctrl_partial_access.1350589627 |
|
|
Mar 17 12:47:27 PM PDT 24 |
Mar 17 12:47:39 PM PDT 24 |
679759066 ps |
| T36 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3644423656 |
|
|
Mar 17 12:49:28 PM PDT 24 |
Mar 17 12:49:30 PM PDT 24 |
148936549 ps |
| T31 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.3344304249 |
|
|
Mar 17 12:47:27 PM PDT 24 |
Mar 17 12:47:28 PM PDT 24 |
235214731 ps |
| T37 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1937978304 |
|
|
Mar 17 12:48:56 PM PDT 24 |
Mar 17 12:54:21 PM PDT 24 |
5315430753 ps |
| T38 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.3972847575 |
|
|
Mar 17 12:47:54 PM PDT 24 |
Mar 17 12:47:55 PM PDT 24 |
72461799 ps |
| T39 |
/workspace/coverage/default/22.sram_ctrl_executable.744227394 |
|
|
Mar 17 12:47:33 PM PDT 24 |
Mar 17 12:58:40 PM PDT 24 |
40414373007 ps |
| T40 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.595704031 |
|
|
Mar 17 12:48:45 PM PDT 24 |
Mar 17 12:49:02 PM PDT 24 |
163178335 ps |
| T41 |
/workspace/coverage/default/37.sram_ctrl_bijection.3958264378 |
|
|
Mar 17 12:48:29 PM PDT 24 |
Mar 17 12:49:15 PM PDT 24 |
8441763014 ps |
| T154 |
/workspace/coverage/default/15.sram_ctrl_smoke.2922568698 |
|
|
Mar 17 12:47:29 PM PDT 24 |
Mar 17 12:48:57 PM PDT 24 |
668480510 ps |
| T156 |
/workspace/coverage/default/11.sram_ctrl_smoke.1754116711 |
|
|
Mar 17 12:48:54 PM PDT 24 |
Mar 17 12:49:10 PM PDT 24 |
1834572845 ps |
| T153 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.4293755914 |
|
|
Mar 17 12:48:31 PM PDT 24 |
Mar 17 12:52:26 PM PDT 24 |
5230607565 ps |
| T8 |
/workspace/coverage/default/46.sram_ctrl_stress_all.2005791336 |
|
|
Mar 17 12:49:14 PM PDT 24 |
Mar 17 01:31:58 PM PDT 24 |
185657625872 ps |
| T73 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1936548484 |
|
|
Mar 17 12:47:01 PM PDT 24 |
Mar 17 12:47:06 PM PDT 24 |
334699232 ps |
| T157 |
/workspace/coverage/default/10.sram_ctrl_smoke.301742342 |
|
|
Mar 17 12:47:25 PM PDT 24 |
Mar 17 12:48:00 PM PDT 24 |
1552498910 ps |
| T147 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3610744280 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 01:04:31 PM PDT 24 |
11248773277 ps |
| T136 |
/workspace/coverage/default/7.sram_ctrl_executable.2857610188 |
|
|
Mar 17 12:46:59 PM PDT 24 |
Mar 17 12:57:39 PM PDT 24 |
19130715693 ps |
| T148 |
/workspace/coverage/default/35.sram_ctrl_bijection.709480666 |
|
|
Mar 17 12:48:16 PM PDT 24 |
Mar 17 12:49:02 PM PDT 24 |
1577057064 ps |
| T149 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.1440689016 |
|
|
Mar 17 12:49:28 PM PDT 24 |
Mar 17 12:51:10 PM PDT 24 |
131170889 ps |
| T22 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.267345704 |
|
|
Mar 17 12:48:52 PM PDT 24 |
Mar 17 12:55:03 PM PDT 24 |
6330775316 ps |
| T96 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.3670225807 |
|
|
Mar 17 12:48:06 PM PDT 24 |
Mar 17 12:52:23 PM PDT 24 |
10589018230 ps |
| T146 |
/workspace/coverage/default/7.sram_ctrl_bijection.1195012680 |
|
|
Mar 17 12:46:59 PM PDT 24 |
Mar 17 12:47:45 PM PDT 24 |
702247618 ps |
| T97 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.1411792878 |
|
|
Mar 17 12:48:26 PM PDT 24 |
Mar 17 12:51:16 PM PDT 24 |
1735688561 ps |
| T152 |
/workspace/coverage/default/49.sram_ctrl_bijection.1663436444 |
|
|
Mar 17 12:49:34 PM PDT 24 |
Mar 17 12:50:39 PM PDT 24 |
12548754634 ps |
| T151 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.2143980589 |
|
|
Mar 17 12:47:33 PM PDT 24 |
Mar 17 12:56:24 PM PDT 24 |
23920120416 ps |
| T158 |
/workspace/coverage/default/39.sram_ctrl_smoke.1502121668 |
|
|
Mar 17 12:48:44 PM PDT 24 |
Mar 17 12:48:56 PM PDT 24 |
7315441900 ps |
| T98 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1402444302 |
|
|
Mar 17 12:47:23 PM PDT 24 |
Mar 17 12:51:44 PM PDT 24 |
22432894227 ps |
| T159 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.3930117602 |
|
|
Mar 17 12:47:54 PM PDT 24 |
Mar 17 12:48:30 PM PDT 24 |
516419493 ps |
| T160 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.1806504617 |
|
|
Mar 17 12:47:27 PM PDT 24 |
Mar 17 12:47:33 PM PDT 24 |
150175114 ps |
| T135 |
/workspace/coverage/default/28.sram_ctrl_executable.38116851 |
|
|
Mar 17 12:48:03 PM PDT 24 |
Mar 17 01:01:00 PM PDT 24 |
62303702793 ps |
| T53 |
/workspace/coverage/default/27.sram_ctrl_stress_all.4069403896 |
|
|
Mar 17 12:47:51 PM PDT 24 |
Mar 17 01:17:19 PM PDT 24 |
23814417146 ps |
| T99 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.2774514739 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 12:51:26 PM PDT 24 |
11284969610 ps |
| T140 |
/workspace/coverage/default/35.sram_ctrl_executable.1943737596 |
|
|
Mar 17 12:48:17 PM PDT 24 |
Mar 17 12:58:34 PM PDT 24 |
9617786616 ps |
| T100 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.2949273759 |
|
|
Mar 17 12:47:19 PM PDT 24 |
Mar 17 12:51:48 PM PDT 24 |
10791372162 ps |
| T161 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1027835932 |
|
|
Mar 17 12:47:07 PM PDT 24 |
Mar 17 12:47:08 PM PDT 24 |
122006754 ps |
| T54 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.1624959537 |
|
|
Mar 17 12:47:58 PM PDT 24 |
Mar 17 12:48:02 PM PDT 24 |
220950863 ps |
| T150 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.2064928273 |
|
|
Mar 17 12:48:51 PM PDT 24 |
Mar 17 12:54:27 PM PDT 24 |
14136010386 ps |
| T137 |
/workspace/coverage/default/21.sram_ctrl_executable.2480684482 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 12:59:46 PM PDT 24 |
44001308088 ps |
| T55 |
/workspace/coverage/default/17.sram_ctrl_regwen.3185643350 |
|
|
Mar 17 12:47:30 PM PDT 24 |
Mar 17 01:04:34 PM PDT 24 |
46430254522 ps |
| T162 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.2317534407 |
|
|
Mar 17 12:49:04 PM PDT 24 |
Mar 17 12:49:12 PM PDT 24 |
224630280 ps |
| T163 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.3896210224 |
|
|
Mar 17 12:47:30 PM PDT 24 |
Mar 17 12:47:35 PM PDT 24 |
383018694 ps |
| T142 |
/workspace/coverage/default/29.sram_ctrl_partial_access.2860882019 |
|
|
Mar 17 12:48:08 PM PDT 24 |
Mar 17 12:50:31 PM PDT 24 |
1574669812 ps |
| T74 |
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3596784009 |
|
|
Mar 17 12:49:05 PM PDT 24 |
Mar 17 12:49:08 PM PDT 24 |
87654883 ps |
| T23 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2398250061 |
|
|
Mar 17 12:48:05 PM PDT 24 |
Mar 17 01:10:00 PM PDT 24 |
12084939609 ps |
| T145 |
/workspace/coverage/default/26.sram_ctrl_bijection.3036790264 |
|
|
Mar 17 12:47:47 PM PDT 24 |
Mar 17 12:48:44 PM PDT 24 |
2818535591 ps |
| T138 |
/workspace/coverage/default/32.sram_ctrl_executable.1821026673 |
|
|
Mar 17 12:48:09 PM PDT 24 |
Mar 17 12:55:47 PM PDT 24 |
30587082980 ps |
| T164 |
/workspace/coverage/default/39.sram_ctrl_partial_access.1195816358 |
|
|
Mar 17 12:48:43 PM PDT 24 |
Mar 17 12:48:49 PM PDT 24 |
141027883 ps |
| T28 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3449165334 |
|
|
Mar 17 12:48:09 PM PDT 24 |
Mar 17 12:48:19 PM PDT 24 |
1083018131 ps |
| T29 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4091939055 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 12:50:28 PM PDT 24 |
2444207420 ps |
| T165 |
/workspace/coverage/default/37.sram_ctrl_smoke.518471406 |
|
|
Mar 17 12:48:22 PM PDT 24 |
Mar 17 12:48:32 PM PDT 24 |
432476023 ps |
| T166 |
/workspace/coverage/default/9.sram_ctrl_partial_access.1498484006 |
|
|
Mar 17 12:47:26 PM PDT 24 |
Mar 17 12:47:45 PM PDT 24 |
135109120 ps |
| T75 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.2819350301 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 12:58:22 PM PDT 24 |
2259394560 ps |
| T167 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.3841846769 |
|
|
Mar 17 12:47:26 PM PDT 24 |
Mar 17 12:47:27 PM PDT 24 |
43709267 ps |
| T139 |
/workspace/coverage/default/48.sram_ctrl_stress_all.3755921525 |
|
|
Mar 17 12:49:34 PM PDT 24 |
Mar 17 02:36:57 PM PDT 24 |
224146382264 ps |
| T168 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.3725656766 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 12:51:23 PM PDT 24 |
2470576303 ps |
| T169 |
/workspace/coverage/default/16.sram_ctrl_partial_access_b2b.1222456688 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:56:30 PM PDT 24 |
71437410139 ps |
| T155 |
/workspace/coverage/default/35.sram_ctrl_regwen.847632995 |
|
|
Mar 17 12:48:18 PM PDT 24 |
Mar 17 01:09:08 PM PDT 24 |
3485061444 ps |
| T170 |
/workspace/coverage/default/31.sram_ctrl_mem_walk.668685188 |
|
|
Mar 17 12:48:11 PM PDT 24 |
Mar 17 12:48:17 PM PDT 24 |
234954327 ps |
| T171 |
/workspace/coverage/default/12.sram_ctrl_regwen.1108800077 |
|
|
Mar 17 12:48:40 PM PDT 24 |
Mar 17 12:53:54 PM PDT 24 |
7161488422 ps |
| T121 |
/workspace/coverage/default/36.sram_ctrl_stress_all.2572351341 |
|
|
Mar 17 12:48:25 PM PDT 24 |
Mar 17 01:58:40 PM PDT 24 |
76339679997 ps |
| T172 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.389339902 |
|
|
Mar 17 12:46:55 PM PDT 24 |
Mar 17 12:47:01 PM PDT 24 |
337159819 ps |
| T173 |
/workspace/coverage/default/14.sram_ctrl_regwen.2342956924 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 01:00:29 PM PDT 24 |
18504644003 ps |
| T42 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2395911714 |
|
|
Mar 17 12:47:54 PM PDT 24 |
Mar 17 12:49:59 PM PDT 24 |
3450607292 ps |
| T113 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3596716056 |
|
|
Mar 17 12:47:19 PM PDT 24 |
Mar 17 12:47:24 PM PDT 24 |
216061620 ps |
| T114 |
/workspace/coverage/default/27.sram_ctrl_regwen.2536739189 |
|
|
Mar 17 12:47:51 PM PDT 24 |
Mar 17 01:04:43 PM PDT 24 |
17156186381 ps |
| T115 |
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2738937780 |
|
|
Mar 17 12:49:16 PM PDT 24 |
Mar 17 12:49:22 PM PDT 24 |
522319593 ps |
| T116 |
/workspace/coverage/default/28.sram_ctrl_bijection.777000781 |
|
|
Mar 17 12:47:53 PM PDT 24 |
Mar 17 12:48:22 PM PDT 24 |
653030994 ps |
| T117 |
/workspace/coverage/default/43.sram_ctrl_partial_access.2681963818 |
|
|
Mar 17 12:48:55 PM PDT 24 |
Mar 17 12:49:06 PM PDT 24 |
96510638 ps |
| T118 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1777391280 |
|
|
Mar 17 12:48:52 PM PDT 24 |
Mar 17 12:55:27 PM PDT 24 |
22269563306 ps |
| T119 |
/workspace/coverage/default/16.sram_ctrl_stress_all.488285452 |
|
|
Mar 17 12:47:27 PM PDT 24 |
Mar 17 01:31:39 PM PDT 24 |
35615466235 ps |
| T120 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3188237724 |
|
|
Mar 17 12:48:58 PM PDT 24 |
Mar 17 12:49:02 PM PDT 24 |
53017799 ps |
| T76 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.2211306715 |
|
|
Mar 17 12:46:57 PM PDT 24 |
Mar 17 12:47:02 PM PDT 24 |
120045932 ps |
| T174 |
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1797958087 |
|
|
Mar 17 12:49:30 PM PDT 24 |
Mar 17 12:51:15 PM PDT 24 |
151664314 ps |
| T175 |
/workspace/coverage/default/18.sram_ctrl_partial_access.1312286314 |
|
|
Mar 17 12:47:31 PM PDT 24 |
Mar 17 12:48:15 PM PDT 24 |
298410276 ps |
| T176 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.4053637765 |
|
|
Mar 17 12:47:13 PM PDT 24 |
Mar 17 12:47:16 PM PDT 24 |
163690280 ps |
| T77 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.3904735575 |
|
|
Mar 17 12:48:51 PM PDT 24 |
Mar 17 12:48:56 PM PDT 24 |
68059047 ps |
| T177 |
/workspace/coverage/default/26.sram_ctrl_regwen.706168725 |
|
|
Mar 17 12:47:46 PM PDT 24 |
Mar 17 01:01:17 PM PDT 24 |
15056870030 ps |
| T178 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.764130981 |
|
|
Mar 17 12:47:38 PM PDT 24 |
Mar 17 12:47:48 PM PDT 24 |
1374938468 ps |
| T179 |
/workspace/coverage/default/0.sram_ctrl_partial_access.2343612233 |
|
|
Mar 17 12:46:58 PM PDT 24 |
Mar 17 12:47:00 PM PDT 24 |
146070349 ps |
| T180 |
/workspace/coverage/default/40.sram_ctrl_smoke.1084384595 |
|
|
Mar 17 12:48:48 PM PDT 24 |
Mar 17 12:49:34 PM PDT 24 |
1594175536 ps |
| T181 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.1202450554 |
|
|
Mar 17 12:47:57 PM PDT 24 |
Mar 17 12:48:03 PM PDT 24 |
304832966 ps |
| T182 |
/workspace/coverage/default/5.sram_ctrl_bijection.1059531566 |
|
|
Mar 17 12:47:02 PM PDT 24 |
Mar 17 12:47:39 PM PDT 24 |
800212544 ps |
| T183 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2110616807 |
|
|
Mar 17 12:49:21 PM PDT 24 |
Mar 17 12:55:15 PM PDT 24 |
3869108403 ps |
| T184 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.3994063983 |
|
|
Mar 17 12:47:43 PM PDT 24 |
Mar 17 12:47:48 PM PDT 24 |
466878713 ps |
| T185 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.3977429560 |
|
|
Mar 17 12:48:58 PM PDT 24 |
Mar 17 12:49:28 PM PDT 24 |
237056918 ps |
| T186 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.1564325724 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 12:47:32 PM PDT 24 |
275979840 ps |
| T187 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1600231369 |
|
|
Mar 17 12:49:13 PM PDT 24 |
Mar 17 12:49:14 PM PDT 24 |
35825440 ps |
| T188 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1476943729 |
|
|
Mar 17 12:49:05 PM PDT 24 |
Mar 17 12:49:10 PM PDT 24 |
238596838 ps |
| T189 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.1552754587 |
|
|
Mar 17 12:47:02 PM PDT 24 |
Mar 17 12:47:07 PM PDT 24 |
374283966 ps |
| T190 |
/workspace/coverage/default/37.sram_ctrl_partial_access.2533390464 |
|
|
Mar 17 12:48:24 PM PDT 24 |
Mar 17 12:48:33 PM PDT 24 |
853504061 ps |
| T191 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3063758014 |
|
|
Mar 17 12:47:31 PM PDT 24 |
Mar 17 12:51:22 PM PDT 24 |
13331323010 ps |
| T43 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.784286438 |
|
|
Mar 17 12:49:33 PM PDT 24 |
Mar 17 12:51:19 PM PDT 24 |
981558825 ps |
| T192 |
/workspace/coverage/default/2.sram_ctrl_executable.533856000 |
|
|
Mar 17 12:46:31 PM PDT 24 |
Mar 17 12:59:10 PM PDT 24 |
5548533201 ps |
| T24 |
/workspace/coverage/default/3.sram_ctrl_alert_test.1649298439 |
|
|
Mar 17 12:47:01 PM PDT 24 |
Mar 17 12:47:02 PM PDT 24 |
41391220 ps |
| T143 |
/workspace/coverage/default/23.sram_ctrl_stress_all.134741070 |
|
|
Mar 17 12:47:32 PM PDT 24 |
Mar 17 01:40:06 PM PDT 24 |
90919563032 ps |
| T193 |
/workspace/coverage/default/46.sram_ctrl_smoke.254836028 |
|
|
Mar 17 12:49:13 PM PDT 24 |
Mar 17 12:49:29 PM PDT 24 |
480920210 ps |
| T194 |
/workspace/coverage/default/45.sram_ctrl_bijection.4257197669 |
|
|
Mar 17 12:49:17 PM PDT 24 |
Mar 17 12:50:00 PM PDT 24 |
5295288820 ps |
| T195 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.2302982319 |
|
|
Mar 17 12:49:33 PM PDT 24 |
Mar 17 12:49:33 PM PDT 24 |
57596989 ps |
| T196 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.2046139449 |
|
|
Mar 17 12:48:15 PM PDT 24 |
Mar 17 12:48:21 PM PDT 24 |
152265914 ps |
| T197 |
/workspace/coverage/default/27.sram_ctrl_smoke.1233592903 |
|
|
Mar 17 12:47:54 PM PDT 24 |
Mar 17 12:48:24 PM PDT 24 |
1646503058 ps |
| T78 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2009568882 |
|
|
Mar 17 12:46:45 PM PDT 24 |
Mar 17 12:49:11 PM PDT 24 |
2008997310 ps |
| T198 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1087408481 |
|
|
Mar 17 12:47:05 PM PDT 24 |
Mar 17 12:51:25 PM PDT 24 |
2879760454 ps |
| T199 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.975234471 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 01:09:10 PM PDT 24 |
8900226122 ps |
| T200 |
/workspace/coverage/default/38.sram_ctrl_executable.748058327 |
|
|
Mar 17 12:48:30 PM PDT 24 |
Mar 17 01:02:57 PM PDT 24 |
34518178652 ps |
| T201 |
/workspace/coverage/default/20.sram_ctrl_smoke.1128275327 |
|
|
Mar 17 12:47:30 PM PDT 24 |
Mar 17 12:47:45 PM PDT 24 |
831017717 ps |
| T202 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.3598943050 |
|
|
Mar 17 12:47:28 PM PDT 24 |
Mar 17 12:48:16 PM PDT 24 |
104166850 ps |
| T44 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.3228521561 |
|
|
Mar 17 12:47:25 PM PDT 24 |
Mar 17 12:47:32 PM PDT 24 |
362203217 ps |
| T203 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.824096595 |
|
|
Mar 17 12:47:00 PM PDT 24 |
Mar 17 12:48:00 PM PDT 24 |
108235582 ps |
| T204 |
/workspace/coverage/default/49.sram_ctrl_smoke.3171397965 |
|
|
Mar 17 12:49:33 PM PDT 24 |
Mar 17 12:50:50 PM PDT 24 |
2647418089 ps |
| T205 |
/workspace/coverage/default/36.sram_ctrl_smoke.1091823841 |
|
|
Mar 17 12:48:18 PM PDT 24 |
Mar 17 12:48:34 PM PDT 24 |
241919523 ps |
| T141 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2408453383 |
|
|
Mar 17 12:46:55 PM PDT 24 |
Mar 17 12:52:47 PM PDT 24 |
16218192531 ps |
| T206 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.1296046566 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:47:31 PM PDT 24 |
3182122405 ps |
| T207 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.469471406 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:47:25 PM PDT 24 |
47449169 ps |
| T208 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.3419994269 |
|
|
Mar 17 12:47:32 PM PDT 24 |
Mar 17 12:48:24 PM PDT 24 |
198534928 ps |
| T209 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.4173098129 |
|
|
Mar 17 12:47:59 PM PDT 24 |
Mar 17 12:50:13 PM PDT 24 |
19988287886 ps |
| T210 |
/workspace/coverage/default/38.sram_ctrl_smoke.2217139061 |
|
|
Mar 17 12:48:32 PM PDT 24 |
Mar 17 12:49:31 PM PDT 24 |
103705573 ps |
| T211 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.338884855 |
|
|
Mar 17 12:47:29 PM PDT 24 |
Mar 17 12:47:34 PM PDT 24 |
3512075263 ps |
| T25 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.4102784255 |
|
|
Mar 17 12:46:59 PM PDT 24 |
Mar 17 12:47:03 PM PDT 24 |
704833143 ps |
| T212 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.180509933 |
|
|
Mar 17 12:47:19 PM PDT 24 |
Mar 17 12:50:27 PM PDT 24 |
32008274939 ps |
| T213 |
/workspace/coverage/default/24.sram_ctrl_bijection.2982257340 |
|
|
Mar 17 12:47:31 PM PDT 24 |
Mar 17 12:48:37 PM PDT 24 |
41302880190 ps |
| T45 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.4252155493 |
|
|
Mar 17 12:48:22 PM PDT 24 |
Mar 17 12:52:11 PM PDT 24 |
1228335061 ps |
| T214 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1202244241 |
|
|
Mar 17 12:49:34 PM PDT 24 |
Mar 17 12:49:35 PM PDT 24 |
90069714 ps |
| T215 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.2951983651 |
|
|
Mar 17 12:48:26 PM PDT 24 |
Mar 17 12:50:30 PM PDT 24 |
626902552 ps |
| T216 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.1816384204 |
|
|
Mar 17 12:48:18 PM PDT 24 |
Mar 17 12:49:48 PM PDT 24 |
134509425 ps |
| T217 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.1811787682 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 12:47:54 PM PDT 24 |
417259836 ps |
| T218 |
/workspace/coverage/default/27.sram_ctrl_stress_pipeline.3366766468 |
|
|
Mar 17 12:47:58 PM PDT 24 |
Mar 17 12:51:37 PM PDT 24 |
9276748878 ps |
| T219 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.125114138 |
|
|
Mar 17 12:49:03 PM PDT 24 |
Mar 17 12:49:04 PM PDT 24 |
28104736 ps |
| T220 |
/workspace/coverage/default/37.sram_ctrl_max_throughput.1527985726 |
|
|
Mar 17 12:48:28 PM PDT 24 |
Mar 17 12:48:36 PM PDT 24 |
234697907 ps |
| T221 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.2882901503 |
|
|
Mar 17 12:47:19 PM PDT 24 |
Mar 17 12:47:27 PM PDT 24 |
296556531 ps |
| T222 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1845632647 |
|
|
Mar 17 12:48:58 PM PDT 24 |
Mar 17 12:55:34 PM PDT 24 |
35964476760 ps |
| T223 |
/workspace/coverage/default/7.sram_ctrl_stress_all.2798146840 |
|
|
Mar 17 12:47:08 PM PDT 24 |
Mar 17 01:07:45 PM PDT 24 |
17032707300 ps |
| T224 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.681741462 |
|
|
Mar 17 12:47:12 PM PDT 24 |
Mar 17 12:47:13 PM PDT 24 |
32367300 ps |
| T225 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.3011251522 |
|
|
Mar 17 12:46:58 PM PDT 24 |
Mar 17 12:47:04 PM PDT 24 |
1444254795 ps |
| T226 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.1179066314 |
|
|
Mar 17 12:47:18 PM PDT 24 |
Mar 17 12:47:24 PM PDT 24 |
307627865 ps |
| T227 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4216563142 |
|
|
Mar 17 12:47:03 PM PDT 24 |
Mar 17 12:50:17 PM PDT 24 |
7017244352 ps |
| T228 |
/workspace/coverage/default/38.sram_ctrl_regwen.1275217082 |
|
|
Mar 17 12:48:44 PM PDT 24 |
Mar 17 12:52:02 PM PDT 24 |
780333246 ps |
| T229 |
/workspace/coverage/default/25.sram_ctrl_throughput_w_partial_write.1012644995 |
|
|
Mar 17 12:47:53 PM PDT 24 |
Mar 17 12:48:30 PM PDT 24 |
1099218348 ps |
| T230 |
/workspace/coverage/default/13.sram_ctrl_regwen.1530406237 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 01:04:39 PM PDT 24 |
2759622985 ps |
| T231 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.2113826473 |
|
|
Mar 17 12:47:16 PM PDT 24 |
Mar 17 12:47:27 PM PDT 24 |
135182950 ps |
| T232 |
/workspace/coverage/default/47.sram_ctrl_alert_test.781661136 |
|
|
Mar 17 12:49:28 PM PDT 24 |
Mar 17 12:49:29 PM PDT 24 |
13619696 ps |
| T233 |
/workspace/coverage/default/33.sram_ctrl_smoke.1412370785 |
|
|
Mar 17 12:48:14 PM PDT 24 |
Mar 17 12:48:27 PM PDT 24 |
2796868897 ps |
| T234 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.505855224 |
|
|
Mar 17 12:49:33 PM PDT 24 |
Mar 17 12:49:43 PM PDT 24 |
675151655 ps |
| T235 |
/workspace/coverage/default/10.sram_ctrl_executable.2998241412 |
|
|
Mar 17 12:47:15 PM PDT 24 |
Mar 17 12:56:15 PM PDT 24 |
36702588896 ps |
| T46 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.566969864 |
|
|
Mar 17 12:48:16 PM PDT 24 |
Mar 17 12:50:41 PM PDT 24 |
4717273142 ps |
| T236 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.213053658 |
|
|
Mar 17 12:46:32 PM PDT 24 |
Mar 17 12:46:38 PM PDT 24 |
636911313 ps |
| T237 |
/workspace/coverage/default/20.sram_ctrl_alert_test.2782181685 |
|
|
Mar 17 12:47:26 PM PDT 24 |
Mar 17 12:47:27 PM PDT 24 |
16721530 ps |
| T26 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.3306835546 |
|
|
Mar 17 12:46:30 PM PDT 24 |
Mar 17 12:46:32 PM PDT 24 |
144617985 ps |
| T238 |
/workspace/coverage/default/30.sram_ctrl_regwen.2289216561 |
|
|
Mar 17 12:48:08 PM PDT 24 |
Mar 17 12:51:05 PM PDT 24 |
641231401 ps |
| T239 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1060008389 |
|
|
Mar 17 12:48:09 PM PDT 24 |
Mar 17 12:48:12 PM PDT 24 |
56926634 ps |
| T240 |
/workspace/coverage/default/19.sram_ctrl_smoke.1698833705 |
|
|
Mar 17 12:47:23 PM PDT 24 |
Mar 17 12:47:39 PM PDT 24 |
1439140910 ps |
| T241 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1406021794 |
|
|
Mar 17 12:47:08 PM PDT 24 |
Mar 17 12:47:11 PM PDT 24 |
347748851 ps |
| T242 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.3068024317 |
|
|
Mar 17 12:48:26 PM PDT 24 |
Mar 17 12:48:30 PM PDT 24 |
563953466 ps |
| T243 |
/workspace/coverage/default/33.sram_ctrl_regwen.1614188826 |
|
|
Mar 17 12:48:09 PM PDT 24 |
Mar 17 01:07:17 PM PDT 24 |
8578870507 ps |
| T244 |
/workspace/coverage/default/30.sram_ctrl_alert_test.183665377 |
|
|
Mar 17 12:48:06 PM PDT 24 |
Mar 17 12:48:07 PM PDT 24 |
20181941 ps |
| T144 |
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.923557505 |
|
|
Mar 17 12:47:26 PM PDT 24 |
Mar 17 12:51:41 PM PDT 24 |
11695175219 ps |
| T245 |
/workspace/coverage/default/35.sram_ctrl_stress_all.4254482252 |
|
|
Mar 17 12:48:17 PM PDT 24 |
Mar 17 01:39:59 PM PDT 24 |
264044346362 ps |
| T246 |
/workspace/coverage/default/10.sram_ctrl_alert_test.1856920873 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 12:47:24 PM PDT 24 |
13444740 ps |
| T247 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.2395216461 |
|
|
Mar 17 12:46:30 PM PDT 24 |
Mar 17 12:46:35 PM PDT 24 |
158275204 ps |
| T248 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.504627196 |
|
|
Mar 17 12:47:26 PM PDT 24 |
Mar 17 12:47:35 PM PDT 24 |
4975636431 ps |
| T249 |
/workspace/coverage/default/6.sram_ctrl_executable.1011827385 |
|
|
Mar 17 12:47:02 PM PDT 24 |
Mar 17 12:55:18 PM PDT 24 |
6097832488 ps |
| T250 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1377156724 |
|
|
Mar 17 12:47:27 PM PDT 24 |
Mar 17 12:47:45 PM PDT 24 |
368208396 ps |
| T251 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.850818455 |
|
|
Mar 17 12:47:32 PM PDT 24 |
Mar 17 12:47:35 PM PDT 24 |
103152538 ps |
| T252 |
/workspace/coverage/default/39.sram_ctrl_executable.3244680243 |
|
|
Mar 17 12:48:44 PM PDT 24 |
Mar 17 01:15:27 PM PDT 24 |
114513270423 ps |
| T253 |
/workspace/coverage/default/45.sram_ctrl_partial_access.568518944 |
|
|
Mar 17 12:49:17 PM PDT 24 |
Mar 17 12:49:28 PM PDT 24 |
684458019 ps |
| T254 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2682557550 |
|
|
Mar 17 12:49:39 PM PDT 24 |
Mar 17 12:49:42 PM PDT 24 |
41696429 ps |
| T255 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.871902612 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 12:47:44 PM PDT 24 |
605021346 ps |
| T256 |
/workspace/coverage/default/43.sram_ctrl_regwen.322330924 |
|
|
Mar 17 12:48:59 PM PDT 24 |
Mar 17 01:01:20 PM PDT 24 |
68909723712 ps |
| T257 |
/workspace/coverage/default/10.sram_ctrl_partial_access.95878485 |
|
|
Mar 17 12:47:20 PM PDT 24 |
Mar 17 12:47:40 PM PDT 24 |
1205160505 ps |
| T258 |
/workspace/coverage/default/36.sram_ctrl_executable.4269875987 |
|
|
Mar 17 12:48:24 PM PDT 24 |
Mar 17 01:09:02 PM PDT 24 |
38962242490 ps |
| T259 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.1263645194 |
|
|
Mar 17 12:48:03 PM PDT 24 |
Mar 17 12:50:46 PM PDT 24 |
1747257110 ps |
| T260 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.1668763417 |
|
|
Mar 17 12:48:25 PM PDT 24 |
Mar 17 12:57:37 PM PDT 24 |
48910317576 ps |
| T261 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.90478692 |
|
|
Mar 17 12:48:39 PM PDT 24 |
Mar 17 12:51:53 PM PDT 24 |
5852403713 ps |
| T262 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.4217070188 |
|
|
Mar 17 12:48:13 PM PDT 24 |
Mar 17 12:56:04 PM PDT 24 |
18388861130 ps |
| T263 |
/workspace/coverage/default/21.sram_ctrl_bijection.949970219 |
|
|
Mar 17 12:47:23 PM PDT 24 |
Mar 17 12:48:13 PM PDT 24 |
3456398702 ps |
| T264 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.1371564862 |
|
|
Mar 17 12:48:57 PM PDT 24 |
Mar 17 01:15:19 PM PDT 24 |
70586741380 ps |
| T47 |
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3123482529 |
|
|
Mar 17 12:47:23 PM PDT 24 |
Mar 17 12:47:59 PM PDT 24 |
5927618177 ps |
| T265 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.2671969120 |
|
|
Mar 17 12:48:03 PM PDT 24 |
Mar 17 12:48:04 PM PDT 24 |
47474970 ps |
| T48 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2383645707 |
|
|
Mar 17 12:49:03 PM PDT 24 |
Mar 17 12:52:23 PM PDT 24 |
2473485520 ps |
| T266 |
/workspace/coverage/default/1.sram_ctrl_alert_test.3949808870 |
|
|
Mar 17 12:46:26 PM PDT 24 |
Mar 17 12:46:26 PM PDT 24 |
52812256 ps |
| T267 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.1369870030 |
|
|
Mar 17 12:48:05 PM PDT 24 |
Mar 17 12:48:15 PM PDT 24 |
84705650 ps |
| T268 |
/workspace/coverage/default/5.sram_ctrl_smoke.2111565824 |
|
|
Mar 17 12:46:47 PM PDT 24 |
Mar 17 12:46:49 PM PDT 24 |
62436627 ps |
| T269 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3560090948 |
|
|
Mar 17 12:46:53 PM PDT 24 |
Mar 17 01:04:27 PM PDT 24 |
48887136480 ps |
| T270 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2412757372 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:56:48 PM PDT 24 |
10325806226 ps |
| T271 |
/workspace/coverage/default/42.sram_ctrl_partial_access.2062999982 |
|
|
Mar 17 12:48:55 PM PDT 24 |
Mar 17 12:49:13 PM PDT 24 |
934163564 ps |
| T272 |
/workspace/coverage/default/27.sram_ctrl_executable.2506916540 |
|
|
Mar 17 12:48:08 PM PDT 24 |
Mar 17 12:56:29 PM PDT 24 |
7980681246 ps |
| T273 |
/workspace/coverage/default/8.sram_ctrl_alert_test.1557779728 |
|
|
Mar 17 12:47:11 PM PDT 24 |
Mar 17 12:47:12 PM PDT 24 |
103534867 ps |
| T274 |
/workspace/coverage/default/34.sram_ctrl_bijection.1026300664 |
|
|
Mar 17 12:48:14 PM PDT 24 |
Mar 17 12:49:23 PM PDT 24 |
1137419447 ps |
| T275 |
/workspace/coverage/default/42.sram_ctrl_bijection.199720640 |
|
|
Mar 17 12:48:52 PM PDT 24 |
Mar 17 12:49:32 PM PDT 24 |
4572336724 ps |
| T276 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.37838607 |
|
|
Mar 17 12:47:12 PM PDT 24 |
Mar 17 12:48:01 PM PDT 24 |
481340900 ps |
| T277 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.2262161775 |
|
|
Mar 17 12:48:25 PM PDT 24 |
Mar 17 12:50:37 PM PDT 24 |
683025154 ps |
| T278 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3307781098 |
|
|
Mar 17 12:48:57 PM PDT 24 |
Mar 17 12:49:06 PM PDT 24 |
2673899564 ps |
| T279 |
/workspace/coverage/default/14.sram_ctrl_alert_test.880739472 |
|
|
Mar 17 12:47:28 PM PDT 24 |
Mar 17 12:47:28 PM PDT 24 |
19749640 ps |
| T280 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.1109825566 |
|
|
Mar 17 12:47:33 PM PDT 24 |
Mar 17 12:52:18 PM PDT 24 |
3038075815 ps |
| T281 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.3754558286 |
|
|
Mar 17 12:48:11 PM PDT 24 |
Mar 17 12:48:12 PM PDT 24 |
75770446 ps |
| T282 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.113881002 |
|
|
Mar 17 12:47:19 PM PDT 24 |
Mar 17 01:02:59 PM PDT 24 |
36285083363 ps |
| T283 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.57758876 |
|
|
Mar 17 12:48:08 PM PDT 24 |
Mar 17 12:48:47 PM PDT 24 |
119406070 ps |
| T284 |
/workspace/coverage/default/29.sram_ctrl_executable.1265445033 |
|
|
Mar 17 12:48:06 PM PDT 24 |
Mar 17 01:01:17 PM PDT 24 |
34624288561 ps |
| T285 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.2512962021 |
|
|
Mar 17 12:49:05 PM PDT 24 |
Mar 17 12:49:48 PM PDT 24 |
94426848 ps |
| T286 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2223175081 |
|
|
Mar 17 12:46:29 PM PDT 24 |
Mar 17 12:51:19 PM PDT 24 |
1830115784 ps |
| T287 |
/workspace/coverage/default/48.sram_ctrl_regwen.2510930080 |
|
|
Mar 17 12:49:32 PM PDT 24 |
Mar 17 01:05:03 PM PDT 24 |
2721820310 ps |
| T288 |
/workspace/coverage/default/47.sram_ctrl_smoke.3672974808 |
|
|
Mar 17 12:49:36 PM PDT 24 |
Mar 17 12:51:33 PM PDT 24 |
1333625451 ps |
| T289 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.690620328 |
|
|
Mar 17 12:47:18 PM PDT 24 |
Mar 17 12:47:23 PM PDT 24 |
102323119 ps |
| T290 |
/workspace/coverage/default/23.sram_ctrl_smoke.2748582213 |
|
|
Mar 17 12:47:32 PM PDT 24 |
Mar 17 12:49:38 PM PDT 24 |
252232762 ps |
| T291 |
/workspace/coverage/default/40.sram_ctrl_executable.3706961196 |
|
|
Mar 17 12:48:50 PM PDT 24 |
Mar 17 01:15:56 PM PDT 24 |
17244456068 ps |
| T292 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.2423938436 |
|
|
Mar 17 12:48:09 PM PDT 24 |
Mar 17 12:48:12 PM PDT 24 |
978271257 ps |
| T293 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3316014974 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:51:19 PM PDT 24 |
2583847691 ps |
| T294 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.3646503639 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:47:27 PM PDT 24 |
139024956 ps |
| T295 |
/workspace/coverage/default/13.sram_ctrl_executable.2579370490 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:53:42 PM PDT 24 |
18710469212 ps |
| T296 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3191516071 |
|
|
Mar 17 12:47:49 PM PDT 24 |
Mar 17 12:51:43 PM PDT 24 |
7838538631 ps |
| T297 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.1437134018 |
|
|
Mar 17 12:48:03 PM PDT 24 |
Mar 17 12:48:06 PM PDT 24 |
350199301 ps |
| T298 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.3245099525 |
|
|
Mar 17 12:47:21 PM PDT 24 |
Mar 17 12:57:03 PM PDT 24 |
9010041348 ps |
| T299 |
/workspace/coverage/default/47.sram_ctrl_regwen.3294321248 |
|
|
Mar 17 12:49:20 PM PDT 24 |
Mar 17 01:11:02 PM PDT 24 |
12981849657 ps |
| T300 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.3374509090 |
|
|
Mar 17 12:47:15 PM PDT 24 |
Mar 17 12:54:28 PM PDT 24 |
1210417378 ps |
| T301 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2915017861 |
|
|
Mar 17 12:46:57 PM PDT 24 |
Mar 17 12:48:57 PM PDT 24 |
153979530 ps |
| T302 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3986430367 |
|
|
Mar 17 12:47:19 PM PDT 24 |
Mar 17 12:47:23 PM PDT 24 |
77401568 ps |
| T303 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.3983459921 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 12:47:24 PM PDT 24 |
123282407 ps |
| T304 |
/workspace/coverage/default/46.sram_ctrl_bijection.925591155 |
|
|
Mar 17 12:49:15 PM PDT 24 |
Mar 17 12:50:26 PM PDT 24 |
4117030057 ps |
| T305 |
/workspace/coverage/default/25.sram_ctrl_executable.4000572910 |
|
|
Mar 17 12:47:57 PM PDT 24 |
Mar 17 12:51:19 PM PDT 24 |
1925279787 ps |
| T306 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3989972785 |
|
|
Mar 17 12:47:28 PM PDT 24 |
Mar 17 12:47:30 PM PDT 24 |
86814450 ps |
| T307 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1823736707 |
|
|
Mar 17 12:47:22 PM PDT 24 |
Mar 17 01:00:11 PM PDT 24 |
13294333233 ps |
| T308 |
/workspace/coverage/default/23.sram_ctrl_executable.1556902033 |
|
|
Mar 17 12:47:24 PM PDT 24 |
Mar 17 01:03:43 PM PDT 24 |
2528019558 ps |
| T309 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.1578721527 |
|
|
Mar 17 12:48:38 PM PDT 24 |
Mar 17 12:59:08 PM PDT 24 |
4105645485 ps |