Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	45043808	1			T1	1131		T2	3071		T3	10000
triple_byte_access	2507130	1			T1	993		T4	2071		T5	1338
halfword_access	3761105	1			T1	1546		T4	3159		T5	2062
byte_access	5029556	1			T1	2042		T4	4185		T5	2632
zero_access	1264383	1			T1	493		T4	1087		T5	674

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28742895

1

T1

3014

T2

1024

T3

4980

auto[1]

28863087

1

T1

3191

T2

2047

T3

5020

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22467554	1			T1	557		T2	1024		T3	4980
auto[0]	triple_byte_access	1251058	1			T1	475		T4	1063		T5	693
auto[0]	halfword_access	1875807	1			T1	762		T4	1555		T5	984
auto[0]	byte_access	2513673	1			T1	987		T4	2083		T5	1294
auto[0]	zero_access	634803	1			T1	233		T4	552		T5	345
auto[1]	word_access	22576254	1			T1	574		T2	2047		T3	5020
auto[1]	triple_byte_access	1256072	1			T1	518		T4	1008		T5	645
auto[1]	halfword_access	1885298	1			T1	784		T4	1604		T5	1078
auto[1]	byte_access	2515883	1			T1	1055		T4	2102		T5	1338
auto[1]	zero_access	629580	1			T1	260		T4	535		T5	329