Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	145200946	1			T2	417426		T4	385150		T6	45056
instr_valid_dis	114419036	1			T2	417426		T4	385150		T6	45056
instr_en	22016397	1			T15	159638		T21	10818		T9	61134

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11013827	1			T17	24120		T15	60454		T21	10818
sram_ifetch_valid_disable	111637075	1			T2	417426		T4	385150		T6	45056
sram_ifetch_enable	22550044	1			T17	169990		T15	126068		T21	26340

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	145200946	1			T2	417426		T4	385150		T6	45056
hw_debug_en_valid_off	111417791	1			T2	417426		T4	385150		T6	45056
hw_debug_en_on	22156808	1			T17	42160		T15	49798		T21	10818

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	111637075	1			T2	417426		T4	385150		T6	45056
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99283465	1			T2	417426		T4	385150		T6	45056
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9152246	1			T15	29546		T9	18116		T10	232712
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4532970	1			T17	24120		T15	46860		T9	24150
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2244400	1			T17	24120		T15	14032		T44	2094
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1787962	1			T15	32828		T10	111968		T44	2020
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4059771	1			T15	1336		T21	10818		T9	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1962958	1			T44	4830		T45	46184		T60	10166
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1377907	1			T21	10818		T10	4484		T44	29518
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9091777	1			T15	12920		T9	18116		T27	16010
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3954712	1			T44	57660		T143	22192		T142	70248
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3752493	1			T15	12920		T9	18116		T10	93518

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8544776	1			T15	97264		T9	43018		T10	347494
lc_exec_en	9005260	1			T17	42160		T15	35542		T29	15713
valid_exec_dis	108556826	1			T2	417426		T4	385150		T6	45056
invalid_exec_dis	33563871	1			T17	194110		T15	186522		T21	37158