Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42906628	1			T2	189658		T4	175263		T6	22528
triple_byte_access	2501389	1			T2	3875		T4	3445		T5	147
halfword_access	3751922	1			T2	5715		T4	5188		T5	236
byte_access	5013142	1			T2	7515		T4	6955		T5	301
zero_access	1264570	1			T2	1950		T4	1724		T5	72

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27659807

1

T2

104116

T4

96183

T6

11264

auto[1]

27777844

1

T2

104597

T4

96392

T6

11264

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21398108	1			T2	94562		T4	87670		T6	11264
auto[0]	triple_byte_access	1247250	1			T2	1936		T4	1725		T5	84
auto[0]	halfword_access	1871816	1			T2	2849		T4	2544		T5	130
auto[0]	byte_access	2506303	1			T2	3797		T4	3380		T5	134
auto[0]	zero_access	636330	1			T2	972		T4	864		T5	40
auto[1]	word_access	21508520	1			T2	95096		T4	87593		T6	11264
auto[1]	triple_byte_access	1254139	1			T2	1939		T4	1720		T5	63
auto[1]	halfword_access	1880106	1			T2	2866		T4	2644		T5	106
auto[1]	byte_access	2506839	1			T2	3718		T4	3575		T5	167
auto[1]	zero_access	628240	1			T2	978		T4	860		T5	32