Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	148859790	1			T1	9170		T3	2382		T4	11932
instr_valid_dis	116325154	1			T1	9170		T3	2382		T4	11932
instr_en	23736951	1			T17	247320		T18	467758		T140	80070

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10989731	1			T15	62492		T17	136912		T18	31576
sram_ifetch_valid_disable	118984233	1			T1	9170		T3	2382		T4	11932
sram_ifetch_enable	18885826	1			T15	11804		T17	242360		T18	212644

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	148859790	1			T1	9170		T3	2382		T4	11932
hw_debug_en_valid_off	116993220	1			T1	9170		T3	2382		T4	11932
hw_debug_en_on	20067380	1			T15	38712		T17	165284		T18	67630

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	118984233	1			T1	9170		T3	2382		T4	11932
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	105144364	1			T1	9170		T3	2382		T4	11932
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9752652	1			T17	102288		T18	292714		T140	51328
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	3477154	1			T15	32428		T17	108416		T18	19470
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1625558	1			T15	32428		T17	49186		T141	60
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1445082	1			T17	59154		T18	19470		T141	13882
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4712705	1			T15	26846		T18	12106		T140	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1464998	1			T15	26846		T18	12106		T47	35428
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2356721	1			T140	20000		T47	45866		T141	5776
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8125047	1			T15	62		T17	24480		T18	23312
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3128824	1			T15	62		T17	24480		T47	36488
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3413959	1			T18	23312		T140	2608		T62	28938

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8849904	1			T17	57382		T18	155574		T140	8742
lc_exec_en	7229628	1			T15	11804		T17	140804		T18	32212
valid_exec_dis	112917316	1			T1	9170		T3	2382		T4	11932
invalid_exec_dis	29875557	1			T15	74296		T17	379272		T18	244220