Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

---

Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	146704626	1			T1	6142		T2	360866		T3	6142
instr_valid_dis	115133258	1			T1	6142		T2	360866		T3	6142
instr_en	22952598	1			T17	461574		T19	78720		T37	93790

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11731760	1			T4	15792		T17	82872		T19	111182
sram_ifetch_valid_disable	113371382	1			T1	6142		T2	360866		T3	6142
sram_ifetch_enable	21601484	1			T17	288066		T19	273660		T37	80034

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	146704626	1			T1	6142		T2	360866		T3	6142
hw_debug_en_valid_off	113366394	1			T1	6142		T2	360866		T3	6142
hw_debug_en_on	22401035	1			T5	6058		T17	222994		T19	149582

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	113371382	1			T1	6142		T2	360866		T3	6142
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	101234424	1			T1	6142		T2	360866		T3	6142
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8871846	1			T17	90636		T19	8582		T37	13756
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	5233462	1			T17	17680		T19	85864		T35	177406
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1753546	1			T19	56052		T137	54		T50	18486
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	2114296	1			T17	17680		T35	177406		T33	2898
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4218374	1			T17	45192		T19	25318		T35	144824
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1990770	1			T19	9926		T35	9824		T139	80956
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1716180	1			T17	45192		T35	135000		T49	73156
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	9217966	1			T5	6058		T17	74346		T19	38974
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3694026	1			T19	38974		T32	20010		T50	170354
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4169948	1			T17	74346		T49	16500		T138	64

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9526640	1			T17	288066		T19	70138		T37	80034
lc_exec_en	8964695	1			T17	103456		T19	85290		T37	67405
valid_exec_dis	108645853	1			T1	6142		T2	360866		T3	6142
invalid_exec_dis	33333244	1			T4	15792		T17	370938		T19	384842