Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 97.02 100.00 100.00 98.58 99.70 98.52


Total tests in report: 1025
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
86.23 86.23 97.46 97.46 81.62 81.62 93.13 93.13 71.43 71.43 89.94 89.94 95.05 95.05 74.95 74.95 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1279341557
93.77 7.54 99.02 1.56 89.20 7.58 93.63 0.50 100.00 28.57 95.98 6.03 95.05 0.00 83.49 8.53 /workspace/coverage/default/34.sram_ctrl_stress_all.4110671247
94.76 0.99 99.41 0.39 91.39 2.19 94.56 0.93 100.00 0.00 97.70 1.72 95.80 0.75 84.42 0.93 /workspace/coverage/default/3.sram_ctrl_sec_cm.4129040645
95.63 0.88 99.71 0.29 92.16 0.77 95.14 0.57 100.00 0.00 98.56 0.86 96.10 0.30 87.76 3.34 /workspace/coverage/default/23.sram_ctrl_stress_all.916420139
96.43 0.80 99.71 0.00 92.54 0.39 95.14 0.00 100.00 0.00 98.56 0.00 96.10 0.00 92.95 5.19 /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1933869695
97.00 0.57 99.71 0.00 93.19 0.64 96.71 1.57 100.00 0.00 98.56 0.00 97.15 1.05 93.69 0.74 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.878756976
97.41 0.41 99.71 0.00 93.57 0.39 98.43 1.72 100.00 0.00 98.85 0.29 97.60 0.45 93.69 0.00 /workspace/coverage/default/24.sram_ctrl_mem_walk.949493251
97.62 0.21 99.71 0.00 93.57 0.00 98.43 0.00 100.00 0.00 98.85 0.00 97.60 0.00 95.18 1.48 /workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3097408105
97.82 0.20 99.71 0.00 93.57 0.00 98.43 0.00 100.00 0.00 98.85 0.00 98.05 0.45 96.10 0.93 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2345884322
98.00 0.18 99.71 0.00 93.57 0.00 98.50 0.07 100.00 0.00 98.85 0.00 99.25 1.20 96.10 0.00 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1426167789
98.14 0.14 99.80 0.10 93.57 0.00 99.21 0.72 100.00 0.00 98.85 0.00 99.40 0.15 96.10 0.00 /workspace/coverage/default/4.sram_ctrl_ram_cfg.2867394536
98.26 0.12 99.80 0.00 93.57 0.00 99.71 0.50 100.00 0.00 98.85 0.00 99.40 0.00 96.47 0.37 /workspace/coverage/default/40.sram_ctrl_regwen.3203319660
98.35 0.09 99.80 0.00 93.83 0.26 99.71 0.00 100.00 0.00 98.85 0.00 99.40 0.00 96.85 0.37 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3842619030
98.43 0.08 99.80 0.00 93.83 0.00 99.71 0.00 100.00 0.00 98.85 0.00 99.40 0.00 97.40 0.56 /workspace/coverage/default/31.sram_ctrl_stress_all.2773997807
98.49 0.07 99.80 0.00 94.22 0.39 99.79 0.07 100.00 0.00 98.85 0.00 99.40 0.00 97.40 0.00 /workspace/coverage/default/2.sram_ctrl_alert_test.36080219
98.55 0.06 99.80 0.00 94.22 0.00 99.86 0.07 100.00 0.00 98.85 0.00 99.55 0.15 97.59 0.19 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2711305950
98.61 0.05 99.80 0.00 94.22 0.00 99.86 0.00 100.00 0.00 98.85 0.00 99.55 0.00 97.96 0.37 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3732921922
98.66 0.05 99.80 0.00 94.22 0.00 99.86 0.00 100.00 0.00 98.85 0.00 99.55 0.00 98.33 0.37 /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1990243469
98.69 0.03 99.80 0.00 94.34 0.13 99.96 0.11 100.00 0.00 98.85 0.00 99.55 0.00 98.33 0.00 /workspace/coverage/default/32.sram_ctrl_lc_escalation.1305336293
98.72 0.03 99.80 0.00 94.34 0.00 99.96 0.00 100.00 0.00 98.85 0.00 99.55 0.00 98.52 0.19 /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.35845002
98.74 0.02 99.80 0.00 94.34 0.00 99.96 0.00 100.00 0.00 98.85 0.00 99.70 0.15 98.52 0.00 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2883680751
98.76 0.02 99.80 0.00 94.47 0.13 99.96 0.00 100.00 0.00 98.85 0.00 99.70 0.00 98.52 0.00 /workspace/coverage/default/14.sram_ctrl_partial_access.270437100
98.76 0.01 99.80 0.00 94.47 0.00 100.00 0.04 100.00 0.00 98.85 0.00 99.70 0.00 98.52 0.00 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2032998503

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1697444054
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1039730886
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2173366601
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.3974450319
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3868677845
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3321596972
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2286275286
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2941514588
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3856203875
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.1801030624
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3639507692
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3888018285
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.249188212
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3198860456
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.852219120
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.649364483
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2678404105
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.202389860
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.809238571
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1404826338
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2841883496
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.168775806
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2798979501
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3695192215
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2110355165
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3914539623
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4037049824
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3174743180
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2661865068
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4247809309
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4011624628
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2296599876
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2509278285
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1560112743
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2402532863
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2558010467
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.679042325
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2194498301
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3853079980
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2001269507
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2580103114
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2887310715
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.273852785
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.361964258
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.963395948
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1041241530
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3914666507
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3556545718
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1693556843
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.3880880385
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2886137990
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2618311225
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2281870258
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2233794326
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2143769272
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1630935235
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2924137000
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2738306536
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2667539745
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3514016641
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1776921410
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3119106983
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3943176181
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.158111667
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3083173443
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1350062775
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1895286993
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.671446602
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.3431317567
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1159266477
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3073603272
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.69936457
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.143757350
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2293325607
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.978468168
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1727230356
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3603875716
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.438371428
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1935031322
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.10900731
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2274349030
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3517086375
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.636509606
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2873676723
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1287438946
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1256658696
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1709733717
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2230920797
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.111599765
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.4029330283
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4128031440
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.411543871
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3399147108
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3406524761
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2946177856
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3528063825
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.123657774
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3424180803
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3103803619
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1722398095
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3966987934
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2669692386
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2785488649
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3775896464
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2608463359
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3808801845
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2572948368
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3475529001
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2748126345
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3582141904
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3742532961
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2030889273
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.836202785
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2472346793
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1832672930
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1454577777
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1336967853
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1806564204
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.202731621
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1679432912
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.497016482
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.990912280
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1078062794
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3660501365
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2887439542
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2107730492
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.201339199
/workspace/coverage/default/0.sram_ctrl_alert_test.417066290
/workspace/coverage/default/0.sram_ctrl_bijection.2349080545
/workspace/coverage/default/0.sram_ctrl_executable.2906170575
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3586132741
/workspace/coverage/default/0.sram_ctrl_max_throughput.1272361287
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3216155012
/workspace/coverage/default/0.sram_ctrl_mem_walk.8550334
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2328001105
/workspace/coverage/default/0.sram_ctrl_partial_access.3810715672
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3414309832
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3570115250
/workspace/coverage/default/0.sram_ctrl_regwen.3496924964
/workspace/coverage/default/0.sram_ctrl_sec_cm.133736533
/workspace/coverage/default/0.sram_ctrl_smoke.875344446
/workspace/coverage/default/0.sram_ctrl_stress_all.181378135
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3592968334
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2869599750
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3175658380
/workspace/coverage/default/1.sram_ctrl_alert_test.218642493
/workspace/coverage/default/1.sram_ctrl_bijection.1331697938
/workspace/coverage/default/1.sram_ctrl_executable.1155516295
/workspace/coverage/default/1.sram_ctrl_lc_escalation.742091921
/workspace/coverage/default/1.sram_ctrl_max_throughput.394895942
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.2574279238
/workspace/coverage/default/1.sram_ctrl_mem_walk.2412189322
/workspace/coverage/default/1.sram_ctrl_multiple_keys.1893554521
/workspace/coverage/default/1.sram_ctrl_partial_access.138676841
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1831102138
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1773477709
/workspace/coverage/default/1.sram_ctrl_regwen.2266827428
/workspace/coverage/default/1.sram_ctrl_sec_cm.1269190846
/workspace/coverage/default/1.sram_ctrl_smoke.2809459394
/workspace/coverage/default/1.sram_ctrl_stress_all.2381616406
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2653779865
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1953997950
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3833656773
/workspace/coverage/default/10.sram_ctrl_alert_test.3458226108
/workspace/coverage/default/10.sram_ctrl_bijection.2388377870
/workspace/coverage/default/10.sram_ctrl_executable.1796046547
/workspace/coverage/default/10.sram_ctrl_lc_escalation.4195504602
/workspace/coverage/default/10.sram_ctrl_max_throughput.3419161246
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2786010617
/workspace/coverage/default/10.sram_ctrl_mem_walk.2121098596
/workspace/coverage/default/10.sram_ctrl_multiple_keys.4049004560
/workspace/coverage/default/10.sram_ctrl_partial_access.4274644517
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1988913348
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2073950300
/workspace/coverage/default/10.sram_ctrl_regwen.3791209395
/workspace/coverage/default/10.sram_ctrl_smoke.135718271
/workspace/coverage/default/10.sram_ctrl_stress_all.1797708399
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.972136257
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.4105756159
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3831323725
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2616715482
/workspace/coverage/default/11.sram_ctrl_alert_test.761837127
/workspace/coverage/default/11.sram_ctrl_bijection.4143006298
/workspace/coverage/default/11.sram_ctrl_executable.908127995
/workspace/coverage/default/11.sram_ctrl_lc_escalation.4274563988
/workspace/coverage/default/11.sram_ctrl_max_throughput.3227079641
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2122746782
/workspace/coverage/default/11.sram_ctrl_mem_walk.3371326758
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1621470305
/workspace/coverage/default/11.sram_ctrl_partial_access.2127409848
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2875992106
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3524400080
/workspace/coverage/default/11.sram_ctrl_regwen.2832995822
/workspace/coverage/default/11.sram_ctrl_smoke.183445958
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1843842347
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.703364294
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/workspace/coverage/default/43.sram_ctrl_lc_escalation.1067999678
/workspace/coverage/default/43.sram_ctrl_max_throughput.1515319498
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3594108826
/workspace/coverage/default/43.sram_ctrl_mem_walk.3129869127
/workspace/coverage/default/43.sram_ctrl_multiple_keys.739508431
/workspace/coverage/default/43.sram_ctrl_partial_access.1239383128
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3486819279
/workspace/coverage/default/43.sram_ctrl_ram_cfg.281119427
/workspace/coverage/default/43.sram_ctrl_regwen.596527940
/workspace/coverage/default/43.sram_ctrl_smoke.62310660
/workspace/coverage/default/43.sram_ctrl_stress_all.1431836008
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.4096697568
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3084444065
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.827625225
/workspace/coverage/default/44.sram_ctrl_alert_test.2601370075
/workspace/coverage/default/44.sram_ctrl_bijection.491188273
/workspace/coverage/default/44.sram_ctrl_executable.3955182248
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2495615016
/workspace/coverage/default/44.sram_ctrl_max_throughput.1641801265
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3746658398
/workspace/coverage/default/44.sram_ctrl_mem_walk.2952459119
/workspace/coverage/default/44.sram_ctrl_multiple_keys.511924091
/workspace/coverage/default/44.sram_ctrl_partial_access.30011804
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2768946526
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3419148294
/workspace/coverage/default/44.sram_ctrl_regwen.48278982
/workspace/coverage/default/44.sram_ctrl_smoke.3643339504
/workspace/coverage/default/44.sram_ctrl_stress_all.2392796868
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3204386975
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2235397333
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1487535621
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1030970323
/workspace/coverage/default/45.sram_ctrl_alert_test.1268405573
/workspace/coverage/default/45.sram_ctrl_bijection.1991163255
/workspace/coverage/default/45.sram_ctrl_executable.2225025824
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2780121412
/workspace/coverage/default/45.sram_ctrl_max_throughput.610489946
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2331683105
/workspace/coverage/default/45.sram_ctrl_mem_walk.2483856934
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2198100383
/workspace/coverage/default/45.sram_ctrl_partial_access.659296918
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.693215351
/workspace/coverage/default/45.sram_ctrl_ram_cfg.872401199
/workspace/coverage/default/45.sram_ctrl_regwen.1870900854
/workspace/coverage/default/45.sram_ctrl_smoke.389233836
/workspace/coverage/default/45.sram_ctrl_stress_all.2086087525
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.722008222
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.383397858
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1090574686
/workspace/coverage/default/46.sram_ctrl_alert_test.1728360716
/workspace/coverage/default/46.sram_ctrl_bijection.1437387961
/workspace/coverage/default/46.sram_ctrl_executable.3915512462
/workspace/coverage/default/46.sram_ctrl_lc_escalation.2514722142
/workspace/coverage/default/46.sram_ctrl_max_throughput.2454819697
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3759995042
/workspace/coverage/default/46.sram_ctrl_mem_walk.2444620708
/workspace/coverage/default/46.sram_ctrl_multiple_keys.1178193379
/workspace/coverage/default/46.sram_ctrl_partial_access.2962445406
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1683243670
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3525015172
/workspace/coverage/default/46.sram_ctrl_regwen.729347678
/workspace/coverage/default/46.sram_ctrl_smoke.2043720505
/workspace/coverage/default/46.sram_ctrl_stress_all.4023644163
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2131840960
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1123220057
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3249927165
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.2662999515
/workspace/coverage/default/47.sram_ctrl_alert_test.2761901397
/workspace/coverage/default/47.sram_ctrl_bijection.3382785724
/workspace/coverage/default/47.sram_ctrl_executable.3785620924
/workspace/coverage/default/47.sram_ctrl_lc_escalation.972917562
/workspace/coverage/default/47.sram_ctrl_max_throughput.3308616379
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3670936410
/workspace/coverage/default/47.sram_ctrl_mem_walk.1982765783
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3572228495
/workspace/coverage/default/47.sram_ctrl_partial_access.1447294118
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2172460272
/workspace/coverage/default/47.sram_ctrl_ram_cfg.828302286
/workspace/coverage/default/47.sram_ctrl_regwen.42459643
/workspace/coverage/default/47.sram_ctrl_smoke.401658967
/workspace/coverage/default/47.sram_ctrl_stress_all.718812606
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.3727101933
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1104067145
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.805517270
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.895545704
/workspace/coverage/default/48.sram_ctrl_alert_test.1319336028
/workspace/coverage/default/48.sram_ctrl_bijection.4186081523
/workspace/coverage/default/48.sram_ctrl_executable.1853488808
/workspace/coverage/default/48.sram_ctrl_lc_escalation.3192237212
/workspace/coverage/default/48.sram_ctrl_max_throughput.2498368595
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3531989029
/workspace/coverage/default/48.sram_ctrl_mem_walk.3240986164
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2232027859
/workspace/coverage/default/48.sram_ctrl_partial_access.4275364609
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1295799520
/workspace/coverage/default/48.sram_ctrl_ram_cfg.639176653
/workspace/coverage/default/48.sram_ctrl_regwen.1037327727
/workspace/coverage/default/48.sram_ctrl_smoke.2380955537
/workspace/coverage/default/48.sram_ctrl_stress_all.1045441398
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.742390650
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2538742338
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.937861858
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.385236172
/workspace/coverage/default/49.sram_ctrl_alert_test.1925963581
/workspace/coverage/default/49.sram_ctrl_bijection.332624437
/workspace/coverage/default/49.sram_ctrl_executable.1034343810
/workspace/coverage/default/49.sram_ctrl_lc_escalation.827041571
/workspace/coverage/default/49.sram_ctrl_max_throughput.1980484289
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.1586947308
/workspace/coverage/default/49.sram_ctrl_mem_walk.1015402340
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2537728821
/workspace/coverage/default/49.sram_ctrl_partial_access.3604116637
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2594150993
/workspace/coverage/default/49.sram_ctrl_ram_cfg.1584926448
/workspace/coverage/default/49.sram_ctrl_regwen.1447374776
/workspace/coverage/default/49.sram_ctrl_smoke.65568022
/workspace/coverage/default/49.sram_ctrl_stress_all.786498306
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1071816006
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.27198914
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.483693246
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3831482430
/workspace/coverage/default/5.sram_ctrl_alert_test.3744954186
/workspace/coverage/default/5.sram_ctrl_bijection.2433134614
/workspace/coverage/default/5.sram_ctrl_executable.1708973172
/workspace/coverage/default/5.sram_ctrl_lc_escalation.3063766040
/workspace/coverage/default/5.sram_ctrl_max_throughput.3834034557
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3168284961
/workspace/coverage/default/5.sram_ctrl_mem_walk.2710954194
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2197104151
/workspace/coverage/default/5.sram_ctrl_partial_access.2894038795
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.607680334
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1670553439
/workspace/coverage/default/5.sram_ctrl_regwen.1668555531
/workspace/coverage/default/5.sram_ctrl_smoke.3257152211
/workspace/coverage/default/5.sram_ctrl_stress_all.3388915570
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3456312001
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3317134659
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3362735388
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.3312738901
/workspace/coverage/default/6.sram_ctrl_alert_test.3254220321
/workspace/coverage/default/6.sram_ctrl_bijection.1862419072
/workspace/coverage/default/6.sram_ctrl_executable.2536786429
/workspace/coverage/default/6.sram_ctrl_lc_escalation.36160267
/workspace/coverage/default/6.sram_ctrl_max_throughput.3928943664
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3188346013
/workspace/coverage/default/6.sram_ctrl_mem_walk.4159024183
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3220524030
/workspace/coverage/default/6.sram_ctrl_partial_access.3046287200
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.269919430
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2707797633
/workspace/coverage/default/6.sram_ctrl_regwen.3828002117
/workspace/coverage/default/6.sram_ctrl_smoke.2309188317
/workspace/coverage/default/6.sram_ctrl_stress_all.392959166
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1362395309
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.3592758765
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2344963828
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.144380447
/workspace/coverage/default/7.sram_ctrl_alert_test.4245958233
/workspace/coverage/default/7.sram_ctrl_bijection.3675530012
/workspace/coverage/default/7.sram_ctrl_executable.1621594367
/workspace/coverage/default/7.sram_ctrl_lc_escalation.43075143
/workspace/coverage/default/7.sram_ctrl_max_throughput.1788625304
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3260342109
/workspace/coverage/default/7.sram_ctrl_mem_walk.1484276818
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3868103149
/workspace/coverage/default/7.sram_ctrl_partial_access.2890359462
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1955283369
/workspace/coverage/default/7.sram_ctrl_ram_cfg.530844692
/workspace/coverage/default/7.sram_ctrl_regwen.3805574946
/workspace/coverage/default/7.sram_ctrl_smoke.1836062052
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2389028965
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.3814147338
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1746663965
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.2137451341
/workspace/coverage/default/8.sram_ctrl_alert_test.302149991
/workspace/coverage/default/8.sram_ctrl_bijection.3854828464
/workspace/coverage/default/8.sram_ctrl_executable.3105549864
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3616291891
/workspace/coverage/default/8.sram_ctrl_max_throughput.36514766
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.251675002
/workspace/coverage/default/8.sram_ctrl_mem_walk.1709706825
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1026742802
/workspace/coverage/default/8.sram_ctrl_partial_access.415698182
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1360884584
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1203689223
/workspace/coverage/default/8.sram_ctrl_regwen.2419934601
/workspace/coverage/default/8.sram_ctrl_smoke.173257109
/workspace/coverage/default/8.sram_ctrl_stress_all.733358260
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2526737586
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1770777082
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3057980610
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1083971669
/workspace/coverage/default/9.sram_ctrl_alert_test.1548379496
/workspace/coverage/default/9.sram_ctrl_bijection.888500615
/workspace/coverage/default/9.sram_ctrl_executable.2357491546
/workspace/coverage/default/9.sram_ctrl_lc_escalation.966485687
/workspace/coverage/default/9.sram_ctrl_max_throughput.2300309245
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.4029385311
/workspace/coverage/default/9.sram_ctrl_mem_walk.2956787272
/workspace/coverage/default/9.sram_ctrl_multiple_keys.732431696
/workspace/coverage/default/9.sram_ctrl_partial_access.2671941478
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2980206073
/workspace/coverage/default/9.sram_ctrl_ram_cfg.4112790220
/workspace/coverage/default/9.sram_ctrl_regwen.619384986
/workspace/coverage/default/9.sram_ctrl_smoke.2978971001
/workspace/coverage/default/9.sram_ctrl_stress_all.1699780598
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1564833899
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3170649706
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1475042317



Total test records in report: 1025
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/24.sram_ctrl_mem_walk.949493251 Mar 26 02:58:20 PM PDT 24 Mar 26 02:58:26 PM PDT 24 1214022733 ps
T2 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.2706876802 Mar 26 02:58:11 PM PDT 24 Mar 26 03:01:30 PM PDT 24 4220833917 ps
T3 /workspace/coverage/default/27.sram_ctrl_mem_walk.2610390124 Mar 26 02:58:18 PM PDT 24 Mar 26 02:58:24 PM PDT 24 2758009449 ps
T8 /workspace/coverage/default/33.sram_ctrl_max_throughput.1274910730 Mar 26 02:58:35 PM PDT 24 Mar 26 03:00:17 PM PDT 24 125817707 ps
T4 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.3116158988 Mar 26 02:58:36 PM PDT 24 Mar 26 03:00:38 PM PDT 24 368383628 ps
T5 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1279341557 Mar 26 02:58:23 PM PDT 24 Mar 26 03:00:00 PM PDT 24 3302103710 ps
T11 /workspace/coverage/default/6.sram_ctrl_ram_cfg.2707797633 Mar 26 02:57:31 PM PDT 24 Mar 26 02:57:31 PM PDT 24 29437170 ps
T6 /workspace/coverage/default/15.sram_ctrl_mem_walk.2064064669 Mar 26 02:57:49 PM PDT 24 Mar 26 02:58:00 PM PDT 24 2607574850 ps
T12 /workspace/coverage/default/29.sram_ctrl_mem_walk.3579325760 Mar 26 02:58:29 PM PDT 24 Mar 26 02:58:37 PM PDT 24 140946643 ps
T7 /workspace/coverage/default/13.sram_ctrl_lc_escalation.1645683374 Mar 26 02:58:15 PM PDT 24 Mar 26 02:58:19 PM PDT 24 335932351 ps
T20 /workspace/coverage/default/4.sram_ctrl_ram_cfg.2867394536 Mar 26 02:57:30 PM PDT 24 Mar 26 02:57:31 PM PDT 24 91864278 ps
T16 /workspace/coverage/default/33.sram_ctrl_stress_pipeline.1742113306 Mar 26 02:58:34 PM PDT 24 Mar 26 03:04:22 PM PDT 24 7519411319 ps
T17 /workspace/coverage/default/29.sram_ctrl_regwen.1469363685 Mar 26 02:58:27 PM PDT 24 Mar 26 03:27:25 PM PDT 24 62104065987 ps
T18 /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.383397858 Mar 26 02:59:20 PM PDT 24 Mar 26 02:59:24 PM PDT 24 47501492 ps
T9 /workspace/coverage/default/47.sram_ctrl_lc_escalation.972917562 Mar 26 02:59:35 PM PDT 24 Mar 26 02:59:39 PM PDT 24 309429236 ps
T13 /workspace/coverage/default/23.sram_ctrl_multiple_keys.2872481485 Mar 26 02:58:06 PM PDT 24 Mar 26 03:20:56 PM PDT 24 40230727765 ps
T58 /workspace/coverage/default/28.sram_ctrl_bijection.4203379130 Mar 26 02:58:23 PM PDT 24 Mar 26 02:58:37 PM PDT 24 433008081 ps
T19 /workspace/coverage/default/23.sram_ctrl_stress_all.916420139 Mar 26 02:58:12 PM PDT 24 Mar 26 03:52:16 PM PDT 24 51697978463 ps
T60 /workspace/coverage/default/7.sram_ctrl_partial_access.2890359462 Mar 26 02:57:31 PM PDT 24 Mar 26 02:57:47 PM PDT 24 896182148 ps
T71 /workspace/coverage/default/7.sram_ctrl_mem_partial_access.3260342109 Mar 26 02:57:29 PM PDT 24 Mar 26 02:57:32 PM PDT 24 330408295 ps
T14 /workspace/coverage/default/15.sram_ctrl_smoke.3349733512 Mar 26 02:58:03 PM PDT 24 Mar 26 02:58:17 PM PDT 24 3064933314 ps
T21 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.878756976 Mar 26 02:58:22 PM PDT 24 Mar 26 03:11:18 PM PDT 24 4934963493 ps
T72 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2653779865 Mar 26 02:57:27 PM PDT 24 Mar 26 03:00:59 PM PDT 24 2236804510 ps
T75 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2611221833 Mar 26 02:59:10 PM PDT 24 Mar 26 03:02:57 PM PDT 24 34435331709 ps
T76 /workspace/coverage/default/40.sram_ctrl_multiple_keys.2932528317 Mar 26 02:59:04 PM PDT 24 Mar 26 03:04:36 PM PDT 24 18862105893 ps
T10 /workspace/coverage/default/1.sram_ctrl_lc_escalation.742091921 Mar 26 02:57:14 PM PDT 24 Mar 26 02:57:18 PM PDT 24 2137941611 ps
T73 /workspace/coverage/default/37.sram_ctrl_partial_access_b2b.2711305950 Mar 26 02:58:49 PM PDT 24 Mar 26 03:04:48 PM PDT 24 20723066337 ps
T77 /workspace/coverage/default/46.sram_ctrl_stress_pipeline.1123220057 Mar 26 02:59:30 PM PDT 24 Mar 26 03:02:17 PM PDT 24 1824750050 ps
T78 /workspace/coverage/default/41.sram_ctrl_max_throughput.4161477244 Mar 26 02:59:07 PM PDT 24 Mar 26 03:00:30 PM PDT 24 239366924 ps
T74 /workspace/coverage/default/31.sram_ctrl_partial_access_b2b.269424177 Mar 26 02:58:34 PM PDT 24 Mar 26 03:01:43 PM PDT 24 2714155928 ps
T31 /workspace/coverage/default/21.sram_ctrl_lc_escalation.1152850982 Mar 26 02:57:59 PM PDT 24 Mar 26 02:58:01 PM PDT 24 636095324 ps
T103 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.386434514 Mar 26 02:58:03 PM PDT 24 Mar 26 03:03:27 PM PDT 24 4859223742 ps
T104 /workspace/coverage/default/20.sram_ctrl_stress_pipeline.3932048099 Mar 26 02:57:49 PM PDT 24 Mar 26 03:01:40 PM PDT 24 4867994553 ps
T15 /workspace/coverage/default/8.sram_ctrl_multiple_keys.1026742802 Mar 26 02:58:42 PM PDT 24 Mar 26 03:06:07 PM PDT 24 34580351296 ps
T105 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.607680334 Mar 26 02:57:29 PM PDT 24 Mar 26 03:04:07 PM PDT 24 75714808546 ps
T37 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.4188144299 Mar 26 02:58:22 PM PDT 24 Mar 26 03:02:38 PM PDT 24 2033939566 ps
T148 /workspace/coverage/default/14.sram_ctrl_partial_access.270437100 Mar 26 02:58:08 PM PDT 24 Mar 26 02:58:13 PM PDT 24 327186817 ps
T82 /workspace/coverage/default/33.sram_ctrl_mem_partial_access.3589117197 Mar 26 02:58:36 PM PDT 24 Mar 26 02:58:39 PM PDT 24 180202950 ps
T35 /workspace/coverage/default/47.sram_ctrl_stress_all.718812606 Mar 26 02:59:34 PM PDT 24 Mar 26 03:39:19 PM PDT 24 9412526111 ps
T83 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1586947308 Mar 26 02:59:48 PM PDT 24 Mar 26 02:59:53 PM PDT 24 64025422 ps
T23 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.2681009022 Mar 26 02:58:30 PM PDT 24 Mar 26 03:00:20 PM PDT 24 4245220490 ps
T149 /workspace/coverage/default/1.sram_ctrl_partial_access.138676841 Mar 26 02:57:24 PM PDT 24 Mar 26 02:58:00 PM PDT 24 290622967 ps
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T59 /workspace/coverage/default/46.sram_ctrl_lc_escalation.2514722142 Mar 26 02:59:26 PM PDT 24 Mar 26 02:59:30 PM PDT 24 334275286 ps
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T137 /workspace/coverage/default/15.sram_ctrl_executable.4216655897 Mar 26 02:58:03 PM PDT 24 Mar 26 03:02:43 PM PDT 24 2611516673 ps
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T28 /workspace/coverage/default/3.sram_ctrl_sec_cm.4129040645 Mar 26 02:57:27 PM PDT 24 Mar 26 02:57:31 PM PDT 24 658374019 ps
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T42 /workspace/coverage/default/42.sram_ctrl_bijection.1954316732 Mar 26 02:59:10 PM PDT 24 Mar 26 03:00:12 PM PDT 24 11449559842 ps
T43 /workspace/coverage/default/13.sram_ctrl_smoke.3843844345 Mar 26 02:57:31 PM PDT 24 Mar 26 02:57:37 PM PDT 24 740637744 ps
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T46 /workspace/coverage/default/9.sram_ctrl_lc_escalation.966485687 Mar 26 02:57:29 PM PDT 24 Mar 26 02:57:34 PM PDT 24 625335148 ps
T47 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.760154773 Mar 26 02:58:22 PM PDT 24 Mar 26 03:02:18 PM PDT 24 2562693979 ps
T48 /workspace/coverage/default/21.sram_ctrl_bijection.3093298684 Mar 26 02:58:05 PM PDT 24 Mar 26 02:58:28 PM PDT 24 758231241 ps
T154 /workspace/coverage/default/17.sram_ctrl_max_throughput.1452180189 Mar 26 02:57:47 PM PDT 24 Mar 26 02:57:50 PM PDT 24 47214889 ps
T24 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.539390003 Mar 26 02:59:03 PM PDT 24 Mar 26 03:09:55 PM PDT 24 10676685900 ps
T155 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1988913348 Mar 26 02:57:38 PM PDT 24 Mar 26 03:04:51 PM PDT 24 34825848382 ps
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T144 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2594150993 Mar 26 02:59:45 PM PDT 24 Mar 26 03:04:13 PM PDT 24 61430435616 ps
T32 /workspace/coverage/default/44.sram_ctrl_regwen.48278982 Mar 26 02:59:20 PM PDT 24 Mar 26 03:11:11 PM PDT 24 4731888543 ps
T26 /workspace/coverage/default/23.sram_ctrl_alert_test.2896995516 Mar 26 02:58:17 PM PDT 24 Mar 26 02:58:17 PM PDT 24 15576227 ps
T159 /workspace/coverage/default/26.sram_ctrl_smoke.1114714440 Mar 26 02:58:20 PM PDT 24 Mar 26 02:58:42 PM PDT 24 90297476 ps
T33 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1729472570 Mar 26 02:58:03 PM PDT 24 Mar 26 03:08:01 PM PDT 24 4611073800 ps
T49 /workspace/coverage/default/19.sram_ctrl_executable.3553553027 Mar 26 02:57:57 PM PDT 24 Mar 26 03:11:31 PM PDT 24 132460727174 ps
T34 /workspace/coverage/default/40.sram_ctrl_regwen.3203319660 Mar 26 02:59:04 PM PDT 24 Mar 26 03:16:45 PM PDT 24 14992439072 ps
T160 /workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.2437023816 Mar 26 02:57:29 PM PDT 24 Mar 26 02:59:17 PM PDT 24 162594928 ps
T138 /workspace/coverage/default/49.sram_ctrl_executable.1034343810 Mar 26 02:59:49 PM PDT 24 Mar 26 03:05:33 PM PDT 24 3960013434 ps
T161 /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3362735388 Mar 26 02:57:33 PM PDT 24 Mar 26 02:57:35 PM PDT 24 172581492 ps
T84 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.153062475 Mar 26 02:58:45 PM PDT 24 Mar 26 03:16:00 PM PDT 24 6226985789 ps
T162 /workspace/coverage/default/44.sram_ctrl_multiple_keys.511924091 Mar 26 02:59:18 PM PDT 24 Mar 26 03:05:15 PM PDT 24 1919409456 ps
T85 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.1552969544 Mar 26 02:57:41 PM PDT 24 Mar 26 02:57:44 PM PDT 24 420674020 ps
T86 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.1360354208 Mar 26 02:57:28 PM PDT 24 Mar 26 03:05:28 PM PDT 24 3631298205 ps
T163 /workspace/coverage/default/47.sram_ctrl_mem_walk.1982765783 Mar 26 02:59:42 PM PDT 24 Mar 26 02:59:51 PM PDT 24 527680679 ps
T164 /workspace/coverage/default/13.sram_ctrl_multiple_keys.2282312304 Mar 26 02:57:35 PM PDT 24 Mar 26 03:09:14 PM PDT 24 8293406661 ps
T165 /workspace/coverage/default/9.sram_ctrl_smoke.2978971001 Mar 26 02:58:42 PM PDT 24 Mar 26 02:58:50 PM PDT 24 428271232 ps
T166 /workspace/coverage/default/26.sram_ctrl_bijection.3892518145 Mar 26 02:58:21 PM PDT 24 Mar 26 02:58:38 PM PDT 24 670694966 ps
T87 /workspace/coverage/default/47.sram_ctrl_access_during_key_req.2662999515 Mar 26 02:59:33 PM PDT 24 Mar 26 03:22:27 PM PDT 24 5715180190 ps
T167 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.177832615 Mar 26 02:58:40 PM PDT 24 Mar 26 02:58:44 PM PDT 24 45192756 ps
T52 /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2345884322 Mar 26 02:59:26 PM PDT 24 Mar 26 02:59:52 PM PDT 24 747717051 ps
T50 /workspace/coverage/default/41.sram_ctrl_stress_all.1190557245 Mar 26 02:59:09 PM PDT 24 Mar 26 03:37:29 PM PDT 24 36329266680 ps
T51 /workspace/coverage/default/48.sram_ctrl_executable.1853488808 Mar 26 02:59:42 PM PDT 24 Mar 26 03:10:21 PM PDT 24 56724454639 ps
T119 /workspace/coverage/default/34.sram_ctrl_stress_all.4110671247 Mar 26 02:58:36 PM PDT 24 Mar 26 03:49:49 PM PDT 24 93723848148 ps
T120 /workspace/coverage/default/12.sram_ctrl_ram_cfg.2523864219 Mar 26 02:57:29 PM PDT 24 Mar 26 02:57:30 PM PDT 24 84786228 ps
T121 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.127772146 Mar 26 02:58:32 PM PDT 24 Mar 26 02:58:34 PM PDT 24 215638185 ps
T122 /workspace/coverage/default/13.sram_ctrl_max_throughput.1831539981 Mar 26 02:57:54 PM PDT 24 Mar 26 02:58:14 PM PDT 24 155123339 ps
T123 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.402940709 Mar 26 02:58:21 PM PDT 24 Mar 26 02:58:26 PM PDT 24 65094055 ps
T36 /workspace/coverage/default/10.sram_ctrl_stress_all.1797708399 Mar 26 02:57:28 PM PDT 24 Mar 26 03:21:03 PM PDT 24 95567642780 ps
T124 /workspace/coverage/default/35.sram_ctrl_max_throughput.3021638920 Mar 26 02:58:37 PM PDT 24 Mar 26 02:58:48 PM PDT 24 64216306 ps
T168 /workspace/coverage/default/1.sram_ctrl_max_throughput.394895942 Mar 26 02:57:19 PM PDT 24 Mar 26 02:59:03 PM PDT 24 134930300 ps
T169 /workspace/coverage/default/44.sram_ctrl_max_throughput.1641801265 Mar 26 02:59:20 PM PDT 24 Mar 26 03:01:35 PM PDT 24 184860327 ps
T170 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.159037798 Mar 26 02:58:02 PM PDT 24 Mar 26 03:03:03 PM PDT 24 16417046326 ps
T171 /workspace/coverage/default/44.sram_ctrl_ram_cfg.3419148294 Mar 26 02:59:21 PM PDT 24 Mar 26 02:59:22 PM PDT 24 51462065 ps
T140 /workspace/coverage/default/28.sram_ctrl_stress_all.2554205085 Mar 26 02:58:25 PM PDT 24 Mar 26 03:48:53 PM PDT 24 35550606362 ps
T172 /workspace/coverage/default/49.sram_ctrl_stress_all.786498306 Mar 26 02:59:48 PM PDT 24 Mar 26 03:58:32 PM PDT 24 18223616626 ps
T173 /workspace/coverage/default/30.sram_ctrl_max_throughput.1126768736 Mar 26 02:58:30 PM PDT 24 Mar 26 02:58:55 PM PDT 24 83592728 ps
T27 /workspace/coverage/default/27.sram_ctrl_alert_test.927468970 Mar 26 02:58:26 PM PDT 24 Mar 26 02:58:27 PM PDT 24 94961860 ps
T125 /workspace/coverage/default/26.sram_ctrl_lc_escalation.423879419 Mar 26 02:58:28 PM PDT 24 Mar 26 02:58:34 PM PDT 24 1566172011 ps
T143 /workspace/coverage/default/1.sram_ctrl_executable.1155516295 Mar 26 02:57:24 PM PDT 24 Mar 26 03:13:48 PM PDT 24 14172833946 ps
T174 /workspace/coverage/default/17.sram_ctrl_access_during_key_req.1482095634 Mar 26 02:57:57 PM PDT 24 Mar 26 03:10:42 PM PDT 24 2853248109 ps
T175 /workspace/coverage/default/6.sram_ctrl_executable.2536786429 Mar 26 02:57:29 PM PDT 24 Mar 26 03:15:42 PM PDT 24 48577287533 ps
T176 /workspace/coverage/default/24.sram_ctrl_access_during_key_req.680558397 Mar 26 02:58:08 PM PDT 24 Mar 26 03:08:20 PM PDT 24 2857931600 ps
T177 /workspace/coverage/default/49.sram_ctrl_mem_walk.1015402340 Mar 26 02:59:48 PM PDT 24 Mar 26 02:59:53 PM PDT 24 75448367 ps
T53 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2117663546 Mar 26 02:58:20 PM PDT 24 Mar 26 02:59:04 PM PDT 24 199363059 ps
T178 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3312738901 Mar 26 02:57:34 PM PDT 24 Mar 26 03:14:35 PM PDT 24 14074928995 ps
T179 /workspace/coverage/default/8.sram_ctrl_partial_access.415698182 Mar 26 02:57:54 PM PDT 24 Mar 26 02:58:05 PM PDT 24 4391265428 ps
T147 /workspace/coverage/default/37.sram_ctrl_partial_access.236445004 Mar 26 02:58:44 PM PDT 24 Mar 26 02:59:31 PM PDT 24 1062052140 ps
T180 /workspace/coverage/default/31.sram_ctrl_max_throughput.1719614027 Mar 26 02:58:28 PM PDT 24 Mar 26 02:58:43 PM PDT 24 276981888 ps
T181 /workspace/coverage/default/3.sram_ctrl_mem_walk.1166949376 Mar 26 02:57:29 PM PDT 24 Mar 26 02:57:39 PM PDT 24 2328989021 ps
T182 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.2032998503 Mar 26 02:57:35 PM PDT 24 Mar 26 03:10:34 PM PDT 24 9473455574 ps
T183 /workspace/coverage/default/29.sram_ctrl_executable.2835002085 Mar 26 02:58:21 PM PDT 24 Mar 26 03:04:36 PM PDT 24 7465348605 ps
T184 /workspace/coverage/default/24.sram_ctrl_mem_partial_access.742523004 Mar 26 02:58:23 PM PDT 24 Mar 26 02:58:25 PM PDT 24 48203630 ps
T185 /workspace/coverage/default/2.sram_ctrl_stress_all.3074497461 Mar 26 02:57:34 PM PDT 24 Mar 26 04:06:47 PM PDT 24 30630063330 ps
T186 /workspace/coverage/default/25.sram_ctrl_lc_escalation.1393722390 Mar 26 02:58:15 PM PDT 24 Mar 26 02:58:19 PM PDT 24 715072351 ps
T187 /workspace/coverage/default/5.sram_ctrl_regwen.1668555531 Mar 26 02:57:30 PM PDT 24 Mar 26 03:09:14 PM PDT 24 10131596751 ps
T188 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3170649706 Mar 26 02:58:43 PM PDT 24 Mar 26 03:04:46 PM PDT 24 16547965069 ps
T189 /workspace/coverage/default/38.sram_ctrl_bijection.3271016595 Mar 26 02:59:12 PM PDT 24 Mar 26 02:59:54 PM PDT 24 679098232 ps
T145 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.3216155012 Mar 26 02:57:26 PM PDT 24 Mar 26 02:57:30 PM PDT 24 385923294 ps
T190 /workspace/coverage/default/1.sram_ctrl_ram_cfg.1773477709 Mar 26 02:57:24 PM PDT 24 Mar 26 02:57:25 PM PDT 24 229252055 ps
T191 /workspace/coverage/default/7.sram_ctrl_smoke.1836062052 Mar 26 02:57:28 PM PDT 24 Mar 26 02:57:45 PM PDT 24 1104869207 ps
T192 /workspace/coverage/default/33.sram_ctrl_mem_walk.1340290243 Mar 26 02:58:32 PM PDT 24 Mar 26 02:58:40 PM PDT 24 529591660 ps
T193 /workspace/coverage/default/27.sram_ctrl_stress_all.925522002 Mar 26 02:58:32 PM PDT 24 Mar 26 03:08:14 PM PDT 24 49497221168 ps
T194 /workspace/coverage/default/37.sram_ctrl_multiple_keys.2299854904 Mar 26 02:58:44 PM PDT 24 Mar 26 03:13:45 PM PDT 24 9272611012 ps
T195 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2344963828 Mar 26 02:57:49 PM PDT 24 Mar 26 02:58:09 PM PDT 24 91663676 ps
T196 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.320167635 Mar 26 02:58:18 PM PDT 24 Mar 26 02:58:23 PM PDT 24 589946895 ps
T197 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.4029385311 Mar 26 02:57:30 PM PDT 24 Mar 26 02:57:35 PM PDT 24 158660349 ps
T198 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1039136791 Mar 26 02:57:35 PM PDT 24 Mar 26 03:03:32 PM PDT 24 58673327309 ps
T199 /workspace/coverage/default/11.sram_ctrl_max_throughput.3227079641 Mar 26 02:57:34 PM PDT 24 Mar 26 02:57:54 PM PDT 24 541201851 ps
T200 /workspace/coverage/default/26.sram_ctrl_ram_cfg.1257556111 Mar 26 02:58:23 PM PDT 24 Mar 26 02:58:24 PM PDT 24 94207986 ps
T201 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.3084444065 Mar 26 02:59:12 PM PDT 24 Mar 26 03:01:16 PM PDT 24 603993431 ps
T202 /workspace/coverage/default/30.sram_ctrl_smoke.2328570229 Mar 26 02:58:26 PM PDT 24 Mar 26 03:01:00 PM PDT 24 631472601 ps
T203 /workspace/coverage/default/23.sram_ctrl_partial_access_b2b.244500985 Mar 26 02:58:15 PM PDT 24 Mar 26 03:01:37 PM PDT 24 2833717542 ps
T204 /workspace/coverage/default/9.sram_ctrl_bijection.888500615 Mar 26 02:57:50 PM PDT 24 Mar 26 02:58:24 PM PDT 24 3776454385 ps
T205 /workspace/coverage/default/11.sram_ctrl_mem_walk.3371326758 Mar 26 02:58:01 PM PDT 24 Mar 26 02:58:09 PM PDT 24 142030854 ps
T206 /workspace/coverage/default/9.sram_ctrl_alert_test.1548379496 Mar 26 02:57:50 PM PDT 24 Mar 26 02:57:51 PM PDT 24 16210431 ps
T141 /workspace/coverage/default/33.sram_ctrl_executable.3528610037 Mar 26 02:58:35 PM PDT 24 Mar 26 03:19:44 PM PDT 24 5325418162 ps
T207 /workspace/coverage/default/32.sram_ctrl_lc_escalation.1305336293 Mar 26 02:58:29 PM PDT 24 Mar 26 02:58:34 PM PDT 24 721798913 ps
T208 /workspace/coverage/default/23.sram_ctrl_ram_cfg.752461056 Mar 26 02:58:16 PM PDT 24 Mar 26 02:58:17 PM PDT 24 51091242 ps
T209 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.29673450 Mar 26 02:57:19 PM PDT 24 Mar 26 03:00:39 PM PDT 24 20408031585 ps
T210 /workspace/coverage/default/16.sram_ctrl_stress_pipeline.1569419250 Mar 26 02:58:04 PM PDT 24 Mar 26 03:01:41 PM PDT 24 2358839838 ps
T211 /workspace/coverage/default/46.sram_ctrl_executable.3915512462 Mar 26 02:59:28 PM PDT 24 Mar 26 03:09:43 PM PDT 24 2430931089 ps
T212 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1475042317 Mar 26 02:57:41 PM PDT 24 Mar 26 02:58:08 PM PDT 24 551367312 ps
T142 /workspace/coverage/default/36.sram_ctrl_regwen.3809759957 Mar 26 02:58:52 PM PDT 24 Mar 26 03:07:20 PM PDT 24 19122414752 ps
T213 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.2906315732 Mar 26 02:58:31 PM PDT 24 Mar 26 02:58:39 PM PDT 24 218436830 ps
T214 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2619317735 Mar 26 02:58:43 PM PDT 24 Mar 26 02:58:48 PM PDT 24 89238483 ps
T215 /workspace/coverage/default/18.sram_ctrl_multiple_keys.3737324121 Mar 26 02:57:42 PM PDT 24 Mar 26 03:18:37 PM PDT 24 55649938490 ps
T216 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3057980610 Mar 26 02:57:39 PM PDT 24 Mar 26 02:58:47 PM PDT 24 479361685 ps
T217 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.371503640 Mar 26 02:58:24 PM PDT 24 Mar 26 03:03:03 PM PDT 24 2959389087 ps
T218 /workspace/coverage/default/30.sram_ctrl_executable.2833771707 Mar 26 02:58:20 PM PDT 24 Mar 26 03:04:20 PM PDT 24 4560196031 ps
T219 /workspace/coverage/default/29.sram_ctrl_partial_access_b2b.3684945577 Mar 26 02:58:27 PM PDT 24 Mar 26 03:03:49 PM PDT 24 18532517214 ps
T220 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1996649909 Mar 26 02:57:24 PM PDT 24 Mar 26 03:02:20 PM PDT 24 47835142809 ps
T221 /workspace/coverage/default/15.sram_ctrl_lc_escalation.1711399382 Mar 26 02:57:36 PM PDT 24 Mar 26 02:57:39 PM PDT 24 539696239 ps
T222 /workspace/coverage/default/18.sram_ctrl_partial_access.3272756131 Mar 26 02:58:02 PM PDT 24 Mar 26 02:58:19 PM PDT 24 3390541176 ps
T223 /workspace/coverage/default/5.sram_ctrl_executable.1708973172 Mar 26 02:57:44 PM PDT 24 Mar 26 03:09:13 PM PDT 24 9339127705 ps
T224 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.3303395535 Mar 26 02:58:13 PM PDT 24 Mar 26 03:07:18 PM PDT 24 1468338013 ps
T225 /workspace/coverage/default/17.sram_ctrl_executable.3458890321 Mar 26 02:57:50 PM PDT 24 Mar 26 03:08:28 PM PDT 24 12859162361 ps
T226 /workspace/coverage/default/41.sram_ctrl_partial_access.2457197633 Mar 26 02:59:03 PM PDT 24 Mar 26 02:59:05 PM PDT 24 175692261 ps
T227 /workspace/coverage/default/5.sram_ctrl_lc_escalation.3063766040 Mar 26 02:57:27 PM PDT 24 Mar 26 02:57:33 PM PDT 24 902270125 ps
T54 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3444058182 Mar 26 02:57:13 PM PDT 24 Mar 26 02:57:30 PM PDT 24 1216470026 ps
T228 /workspace/coverage/default/34.sram_ctrl_multiple_keys.1519070325 Mar 26 02:58:35 PM PDT 24 Mar 26 03:23:20 PM PDT 24 26338927662 ps
T229 /workspace/coverage/default/4.sram_ctrl_max_throughput.449380782 Mar 26 02:57:27 PM PDT 24 Mar 26 02:58:48 PM PDT 24 889917116 ps
T230 /workspace/coverage/default/10.sram_ctrl_stress_pipeline.4105756159 Mar 26 02:57:31 PM PDT 24 Mar 26 03:02:11 PM PDT 24 13655757142 ps
T231 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2855342904 Mar 26 02:58:30 PM PDT 24 Mar 26 02:58:35 PM PDT 24 66145954 ps
T232 /workspace/coverage/default/26.sram_ctrl_max_throughput.258466220 Mar 26 02:58:29 PM PDT 24 Mar 26 02:58:34 PM PDT 24 100968627 ps
T233 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2768946526 Mar 26 02:59:19 PM PDT 24 Mar 26 03:03:14 PM PDT 24 6330143255 ps
T234 /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.269919430 Mar 26 02:57:41 PM PDT 24 Mar 26 03:06:28 PM PDT 24 86236612746 ps
T235 /workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3427226806 Mar 26 02:58:53 PM PDT 24 Mar 26 03:05:52 PM PDT 24 90138118824 ps
T236 /workspace/coverage/default/12.sram_ctrl_max_throughput.565385740 Mar 26 02:57:48 PM PDT 24 Mar 26 02:58:08 PM PDT 24 303363508 ps
T237 /workspace/coverage/default/2.sram_ctrl_smoke.1276111256 Mar 26 02:57:26 PM PDT 24 Mar 26 02:57:47 PM PDT 24 276792994 ps
T238 /workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.110106352 Mar 26 02:59:13 PM PDT 24 Mar 26 03:00:57 PM PDT 24 557235477 ps
T239 /workspace/coverage/default/14.sram_ctrl_ram_cfg.1785004716 Mar 26 02:57:54 PM PDT 24 Mar 26 02:57:55 PM PDT 24 141025306 ps
T240 /workspace/coverage/default/8.sram_ctrl_mem_walk.1709706825 Mar 26 02:57:43 PM PDT 24 Mar 26 02:57:47 PM PDT 24 82781628 ps
T241 /workspace/coverage/default/5.sram_ctrl_bijection.2433134614 Mar 26 02:57:27 PM PDT 24 Mar 26 02:58:09 PM PDT 24 3935354625 ps
T242 /workspace/coverage/default/0.sram_ctrl_executable.2906170575 Mar 26 02:57:19 PM PDT 24 Mar 26 03:16:09 PM PDT 24 17226354720 ps
T55 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.2680301135 Mar 26 02:58:19 PM PDT 24 Mar 26 03:15:36 PM PDT 24 3718662802 ps
T243 /workspace/coverage/default/39.sram_ctrl_max_throughput.971524401 Mar 26 02:59:16 PM PDT 24 Mar 26 02:59:33 PM PDT 24 75626449 ps
T244 /workspace/coverage/default/24.sram_ctrl_throughput_w_partial_write.1170252349 Mar 26 02:58:19 PM PDT 24 Mar 26 02:59:32 PM PDT 24 1091013213 ps
T245 /workspace/coverage/default/49.sram_ctrl_partial_access.3604116637 Mar 26 02:59:41 PM PDT 24 Mar 26 02:59:48 PM PDT 24 146994156 ps
T56 /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1843842347 Mar 26 02:57:44 PM PDT 24 Mar 26 03:02:24 PM PDT 24 8044783285 ps
T246 /workspace/coverage/default/31.sram_ctrl_stress_all.2773997807 Mar 26 02:58:34 PM PDT 24 Mar 26 04:14:56 PM PDT 24 12316786585 ps
T247 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.430451506 Mar 26 02:59:25 PM PDT 24 Mar 26 02:59:28 PM PDT 24 172477415 ps
T248 /workspace/coverage/default/20.sram_ctrl_regwen.2843781209 Mar 26 02:57:53 PM PDT 24 Mar 26 03:01:14 PM PDT 24 631736222 ps
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T250 /workspace/coverage/default/32.sram_ctrl_stress_all.3249273013 Mar 26 02:58:32 PM PDT 24 Mar 26 03:15:12 PM PDT 24 39477173362 ps
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T252 /workspace/coverage/default/16.sram_ctrl_partial_access.4071271680 Mar 26 02:57:39 PM PDT 24 Mar 26 03:00:09 PM PDT 24 752804494 ps
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T254 /workspace/coverage/default/48.sram_ctrl_lc_escalation.3192237212 Mar 26 02:59:34 PM PDT 24 Mar 26 02:59:38 PM PDT 24 2299025853 ps
T57 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.993723041 Mar 26 02:59:16 PM PDT 24 Mar 26 03:00:48 PM PDT 24 870767629 ps
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T269 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.385236172 Mar 26 02:59:42 PM PDT 24 Mar 26 03:17:40 PM PDT 24 7313250274 ps
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T292 /workspace/coverage/default/21.sram_ctrl_alert_test.2787277356 Mar 26 02:58:04 PM PDT 24 Mar 26 02:58:05 PM PDT 24 21760986 ps
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T294 /workspace/coverage/default/35.sram_ctrl_alert_test.840729526 Mar 26 02:58:53 PM PDT 24 Mar 26 02:58:54 PM PDT 24 17721964 ps
T295 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1295799520 Mar 26 02:59:33 PM PDT 24 Mar 26 03:05:48 PM PDT 24 31394078076 ps
T296 /workspace/coverage/default/34.sram_ctrl_ram_cfg.2330978345 Mar 26 02:58:30 PM PDT 24 Mar 26 02:58:30 PM PDT 24 58317426 ps
T297 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3565951298 Mar 26 02:57:27 PM PDT 24 Mar 26 02:57:52 PM PDT 24 110026034 ps
T298 /workspace/coverage/default/48.sram_ctrl_alert_test.1319336028 Mar 26 02:59:42 PM PDT 24 Mar 26 02:59:43 PM PDT 24 12715628 ps
T299 /workspace/coverage/default/7.sram_ctrl_ram_cfg.530844692 Mar 26 02:57:36 PM PDT 24 Mar 26 02:57:37 PM PDT 24 50090399 ps
T300 /workspace/coverage/default/34.sram_ctrl_max_throughput.1576463431 Mar 26 02:58:34 PM PDT 24 Mar 26 02:58:54 PM PDT 24 146259884 ps
T301 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1403135425 Mar 26 02:58:20 PM PDT 24 Mar 26 03:04:14 PM PDT 24 185268567440 ps
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T303 /workspace/coverage/default/25.sram_ctrl_mem_partial_access.2794118025 Mar 26 02:58:16 PM PDT 24 Mar 26 02:58:20 PM PDT 24 64163579 ps
T304 /workspace/coverage/default/8.sram_ctrl_executable.3105549864 Mar 26 02:57:56 PM PDT 24 Mar 26 03:01:38 PM PDT 24 3584779673 ps
T305 /workspace/coverage/default/12.sram_ctrl_lc_escalation.962171831 Mar 26 02:57:31 PM PDT 24 Mar 26 02:57:36 PM PDT 24 2472409258 ps
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