Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44418033	1			T1	3071		T2	164320		T3	3071
triple_byte_access	2530871	1			T2	3180		T4	209		T5	56
halfword_access	3798849	1			T2	4792		T4	286		T5	93
byte_access	5071237	1			T2	6547		T4	366		T5	107
zero_access	1275231	1			T2	1594		T4	92		T5	35

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28487057

1

T1

1024

T2

90113

T3

1024

auto[1]

28607164

1

T1

2047

T2

90320

T3

2047

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22152036	1			T1	1024		T2	82056		T3	1024
auto[0]	triple_byte_access	1261345	1			T2	1600		T4	94		T5	23
auto[0]	halfword_access	1896357	1			T2	2408		T4	159		T5	55
auto[0]	byte_access	2535220	1			T2	3236		T4	184		T5	50
auto[0]	zero_access	642099	1			T2	813		T4	42		T5	18
auto[1]	word_access	22265997	1			T1	2047		T2	82264		T3	2047
auto[1]	triple_byte_access	1269526	1			T2	1580		T4	115		T5	33
auto[1]	halfword_access	1902492	1			T2	2384		T4	127		T5	38
auto[1]	byte_access	2536017	1			T2	3311		T4	182		T5	57
auto[1]	zero_access	633132	1			T2	781		T4	50		T5	17