Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	147501660	1			T1	4056		T3	248058		T4	1932
instr_valid_dis	116345771	1			T1	4056		T3	235090		T4	1932
instr_en	22613124	1			T3	12968		T32	786032		T62	247744

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	11546026	1			T3	17696		T9	79672		T32	225274
sram_ifetch_valid_disable	114249331	1			T1	4056		T3	56970		T4	1932
sram_ifetch_enable	21706303	1			T3	173392		T9	62542		T32	402690

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	147501660	1			T1	4056		T3	248058		T4	1932
hw_debug_en_valid_off	114870052	1			T1	4056		T3	116246		T4	1932
hw_debug_en_on	20971395	1			T3	96944		T9	157082		T32	386780

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	114249331	1			T1	4056		T3	56970		T4	1932
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	101515410	1			T1	4056		T3	56970		T4	1932
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9095752	1			T32	295886		T62	78730		T63	30380
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4757646	1			T9	7102		T32	111392		T62	57364
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	2410264	1			T63	12092		T27	61656		T128	60106
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1661258	1			T32	111392		T62	57364		T63	52326
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4610742	1			T3	8986		T9	56450		T32	113882
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	2002384	1			T3	8986		T62	50		T63	75548
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1891980	1			T32	113882		T62	19196		T55	6134
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	7314314	1			T9	50252		T32	100992		T62	15398
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	2694556	1			T27	22258		T55	32642		T41	42538
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3483376	1			T32	100992		T62	15398		T63	20592

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9112722	1			T3	12968		T32	264872		T62	92454
lc_exec_en	9046339	1			T3	87958		T9	50380		T32	171906
valid_exec_dis	111081018	1			T1	4056		T3	217394		T4	1932
invalid_exec_dis	33252329	1			T3	191088		T9	142214		T32	627964