Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 97.02 100.00 100.00 98.58 99.70 98.52


Total tests in report: 1020
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
78.23 78.23 97.56 97.56 77.38 77.38 66.81 66.81 71.43 71.43 90.52 90.52 94.75 94.75 49.17 49.17 /workspace/coverage/default/27.sram_ctrl_regwen.2089850243
86.55 8.31 97.95 0.39 84.45 7.07 96.14 29.33 71.43 0.00 91.95 1.44 96.55 1.80 67.35 18.18 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1218212506
93.25 6.71 99.22 1.27 87.02 2.57 96.49 0.36 100.00 28.57 94.83 2.87 96.55 0.00 78.66 11.32 /workspace/coverage/default/20.sram_ctrl_stress_all.4198762632
94.91 1.66 99.22 0.00 89.20 2.19 96.49 0.00 100.00 0.00 96.26 1.44 96.55 0.00 86.64 7.98 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.3439177307
95.88 0.97 99.61 0.39 91.39 2.19 97.42 0.93 100.00 0.00 97.99 1.72 97.15 0.60 87.57 0.93 /workspace/coverage/default/4.sram_ctrl_sec_cm.3048598667
96.60 0.73 99.61 0.00 92.03 0.64 97.42 0.00 100.00 0.00 97.99 0.00 97.15 0.00 92.02 4.45 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.970725807
97.17 0.57 99.61 0.00 92.67 0.64 99.14 1.72 100.00 0.00 97.99 0.00 98.20 1.05 92.58 0.56 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2551693433
97.73 0.56 99.71 0.10 93.70 1.03 99.14 0.00 100.00 0.00 98.56 0.57 98.20 0.00 94.81 2.23 /workspace/coverage/default/10.sram_ctrl_stress_all.659426816
98.03 0.30 99.71 0.00 94.09 0.39 99.14 0.00 100.00 0.00 98.85 0.29 98.35 0.15 96.10 1.30 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1538230958
98.26 0.23 99.71 0.00 94.09 0.00 99.21 0.07 100.00 0.00 98.85 0.00 99.70 1.35 96.29 0.19 /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.2492295288
98.40 0.13 99.71 0.00 94.09 0.00 99.21 0.00 100.00 0.00 98.85 0.00 99.70 0.00 97.22 0.93 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3804573548
98.51 0.12 99.80 0.10 94.09 0.00 99.93 0.72 100.00 0.00 98.85 0.00 99.70 0.00 97.22 0.00 /workspace/coverage/default/1.sram_ctrl_ram_cfg.3295413314
98.59 0.08 99.80 0.00 94.09 0.00 99.93 0.00 100.00 0.00 98.85 0.00 99.70 0.00 97.77 0.56 /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4210753458
98.66 0.07 99.80 0.00 94.47 0.39 100.00 0.07 100.00 0.00 98.85 0.00 99.70 0.00 97.77 0.00 /workspace/coverage/default/0.sram_ctrl_alert_test.968029706
98.71 0.05 99.80 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 98.14 0.37 /workspace/coverage/default/13.sram_ctrl_regwen.2940391361
98.74 0.03 99.80 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 98.33 0.19 /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2831561569
98.76 0.03 99.80 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 98.52 0.19 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2734008295

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1110352674
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3903186662
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1624683540
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.2005442432
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2016141731
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.98527943
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.635720172
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4014225588
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1851123024
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.903883331
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4135558997
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.833127207
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2271478466
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1211049897
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.28936187
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.47108078
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2139304097
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3834706656
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2345790560
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1023120744
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.138106853
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2803883941
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1501856379
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3786796298
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3076603216
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.348063177
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.974903106
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2465249179
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.852943285
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3903844791
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.287576515
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3567323308
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1774348878
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3031425526
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3630230580
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3457003912
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.792697365
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1710340223
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2343557466
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1164434950
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2701174855
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1203252253
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1076369672
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.652902145
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.873476401
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4191434597
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.254171077
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3329942034
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2136409033
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2538804477
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1298473068
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.115756320
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3714670395
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4027577098
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2577710799
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3090574296
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3208617350
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3786553577
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2886232108
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.109198092
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2175619172
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3220887303
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3856107489
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2271758975
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3304724021
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1985264548
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2923477103
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1535920887
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3564957747
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2388858987
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4215223226
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2933988094
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1897004451
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.4113074049
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1234546443
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1926676836
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2313524331
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3860647626
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.548558437
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1025846051
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.821170779
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3008314099
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.2062624537
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2260227719
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1601113999
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.336553790
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2241480902
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2632156158
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2702233200
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1955265116
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4228941760
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2007796581
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2150438303
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.973763578
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3836073691
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3571746731
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2888415309
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1423438870
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1275761439
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3217767553
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1061116315
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1768924479
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3316114401
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2197867560
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.358323499
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2518749460
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3170340382
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2984167111
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4254424504
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3978345088
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2951372067
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3847328164
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3015010175
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3812451640
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.558834812
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.309410751
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1483460745
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3200004402
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.644463474
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.534941400
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.696485964
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3804908908
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2720370273
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4108676780
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3596948064
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1905210165
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.661823049
/workspace/coverage/default/0.sram_ctrl_bijection.4031911846
/workspace/coverage/default/0.sram_ctrl_executable.3639831731
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2884434328
/workspace/coverage/default/0.sram_ctrl_max_throughput.1163519247
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.4204308287
/workspace/coverage/default/0.sram_ctrl_mem_walk.3062496123
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1245070544
/workspace/coverage/default/0.sram_ctrl_partial_access.956412841
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3526742131
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1630554846
/workspace/coverage/default/0.sram_ctrl_regwen.2517195177
/workspace/coverage/default/0.sram_ctrl_sec_cm.3797885988
/workspace/coverage/default/0.sram_ctrl_smoke.2709002301
/workspace/coverage/default/0.sram_ctrl_stress_all.4252541632
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.42537961
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1827981746
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3797643495
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.590284653
/workspace/coverage/default/1.sram_ctrl_alert_test.1654071766
/workspace/coverage/default/1.sram_ctrl_bijection.2499010525
/workspace/coverage/default/1.sram_ctrl_executable.60300558
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1373566484
/workspace/coverage/default/1.sram_ctrl_max_throughput.3083287145
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1355099491
/workspace/coverage/default/1.sram_ctrl_mem_walk.352430191
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2270113729
/workspace/coverage/default/1.sram_ctrl_partial_access.3861158457
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2548651404
/workspace/coverage/default/1.sram_ctrl_regwen.1538434001
/workspace/coverage/default/1.sram_ctrl_sec_cm.652485178
/workspace/coverage/default/1.sram_ctrl_smoke.1470131514
/workspace/coverage/default/1.sram_ctrl_stress_all.3970401305
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.1856096017
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.4057413602
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3900848030
/workspace/coverage/default/10.sram_ctrl_alert_test.1839599993
/workspace/coverage/default/10.sram_ctrl_bijection.378024135
/workspace/coverage/default/10.sram_ctrl_executable.2550086522
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3568627894
/workspace/coverage/default/10.sram_ctrl_max_throughput.1725926182
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3426652224
/workspace/coverage/default/10.sram_ctrl_mem_walk.2294352192
/workspace/coverage/default/10.sram_ctrl_multiple_keys.773796059
/workspace/coverage/default/10.sram_ctrl_partial_access.2407399761
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.3178532232
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2257661732
/workspace/coverage/default/10.sram_ctrl_regwen.846030807
/workspace/coverage/default/10.sram_ctrl_smoke.4048072943
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3883365675
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2447590737
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2852660723
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.271329062
/workspace/coverage/default/11.sram_ctrl_alert_test.3922578001
/workspace/coverage/default/11.sram_ctrl_bijection.4098845955
/workspace/coverage/default/11.sram_ctrl_executable.182797550
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2395738981
/workspace/coverage/default/11.sram_ctrl_max_throughput.692513539
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.4239415077
/workspace/coverage/default/11.sram_ctrl_mem_walk.532697929
/workspace/coverage/default/11.sram_ctrl_multiple_keys.1891183811
/workspace/coverage/default/11.sram_ctrl_partial_access.4079513875
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2686521032
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1825020561
/workspace/coverage/default/11.sram_ctrl_regwen.825271446
/workspace/coverage/default/11.sram_ctrl_smoke.1683740917
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1937654113
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3320640740
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.914668552
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.265025287
/workspace/coverage/default/12.sram_ctrl_alert_test.777813846
/workspace/coverage/default/12.sram_ctrl_bijection.375153462
/workspace/coverage/default/12.sram_ctrl_executable.1481263801
/workspace/coverage/default/12.sram_ctrl_lc_escalation.1489485284
/workspace/coverage/default/12.sram_ctrl_max_throughput.1264003048
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2552693179
/workspace/coverage/default/12.sram_ctrl_mem_walk.3970818147
/workspace/coverage/default/12.sram_ctrl_multiple_keys.740795424
/workspace/coverage/default/12.sram_ctrl_partial_access.1484385974
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1154615188
/workspace/coverage/default/12.sram_ctrl_ram_cfg.4033350515
/workspace/coverage/default/12.sram_ctrl_regwen.2062389032
/workspace/coverage/default/12.sram_ctrl_smoke.2681682583
/workspace/coverage/default/12.sram_ctrl_stress_all.1568392142
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1470705863
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.964039314
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3143822932
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/workspace/coverage/default/44.sram_ctrl_executable.2831016123
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1744439679
/workspace/coverage/default/44.sram_ctrl_max_throughput.1665345207
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.36251019
/workspace/coverage/default/44.sram_ctrl_mem_walk.2463836447
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3556779685
/workspace/coverage/default/44.sram_ctrl_partial_access.1022178318
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1655617018
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3211729696
/workspace/coverage/default/44.sram_ctrl_regwen.3328894652
/workspace/coverage/default/44.sram_ctrl_smoke.1064628519
/workspace/coverage/default/44.sram_ctrl_stress_all.4091897064
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.103420932
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1903857828
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1332461411
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1761397611
/workspace/coverage/default/45.sram_ctrl_alert_test.2629536009
/workspace/coverage/default/45.sram_ctrl_bijection.2197204295
/workspace/coverage/default/45.sram_ctrl_executable.3408018142
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1480812209
/workspace/coverage/default/45.sram_ctrl_max_throughput.2789036803
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3157782367
/workspace/coverage/default/45.sram_ctrl_mem_walk.3215739104
/workspace/coverage/default/45.sram_ctrl_multiple_keys.64365194
/workspace/coverage/default/45.sram_ctrl_partial_access.2239041378
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3357870441
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1355035446
/workspace/coverage/default/45.sram_ctrl_smoke.1654571557
/workspace/coverage/default/45.sram_ctrl_stress_all.2267346561
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1669369097
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3715960485
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.771858976
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3837713986
/workspace/coverage/default/46.sram_ctrl_alert_test.2059590359
/workspace/coverage/default/46.sram_ctrl_bijection.3542714303
/workspace/coverage/default/46.sram_ctrl_executable.1485997999
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1276944853
/workspace/coverage/default/46.sram_ctrl_max_throughput.2293940157
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1088572245
/workspace/coverage/default/46.sram_ctrl_mem_walk.1739856841
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2294798182
/workspace/coverage/default/46.sram_ctrl_partial_access.2259788431
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.2306017964
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1164026873
/workspace/coverage/default/46.sram_ctrl_regwen.2041856135
/workspace/coverage/default/46.sram_ctrl_smoke.3929225069
/workspace/coverage/default/46.sram_ctrl_stress_all.2120115404
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1286143027
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.1797890890
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3086366627
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1045325313
/workspace/coverage/default/47.sram_ctrl_alert_test.3213970956
/workspace/coverage/default/47.sram_ctrl_bijection.3756078489
/workspace/coverage/default/47.sram_ctrl_executable.17809562
/workspace/coverage/default/47.sram_ctrl_lc_escalation.3124944277
/workspace/coverage/default/47.sram_ctrl_max_throughput.3284977822
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.661892443
/workspace/coverage/default/47.sram_ctrl_mem_walk.2681945480
/workspace/coverage/default/47.sram_ctrl_multiple_keys.3276798087
/workspace/coverage/default/47.sram_ctrl_partial_access.234334244
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.612105621
/workspace/coverage/default/47.sram_ctrl_ram_cfg.4284567447
/workspace/coverage/default/47.sram_ctrl_regwen.2163405952
/workspace/coverage/default/47.sram_ctrl_smoke.973547679
/workspace/coverage/default/47.sram_ctrl_stress_all.3001584851
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.236075470
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.41190302
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3181541530
/workspace/coverage/default/48.sram_ctrl_alert_test.722779459
/workspace/coverage/default/48.sram_ctrl_bijection.1254553750
/workspace/coverage/default/48.sram_ctrl_executable.980347905
/workspace/coverage/default/48.sram_ctrl_lc_escalation.2086132452
/workspace/coverage/default/48.sram_ctrl_max_throughput.2049851513
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3523513024
/workspace/coverage/default/48.sram_ctrl_mem_walk.184788714
/workspace/coverage/default/48.sram_ctrl_multiple_keys.521163934
/workspace/coverage/default/48.sram_ctrl_partial_access.2412990718
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3916692999
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1542088109
/workspace/coverage/default/48.sram_ctrl_regwen.1799182562
/workspace/coverage/default/48.sram_ctrl_smoke.408845866
/workspace/coverage/default/48.sram_ctrl_stress_all.2851613566
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.844212676
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.621613125
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3549491533
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.1117212287
/workspace/coverage/default/49.sram_ctrl_alert_test.2195254192
/workspace/coverage/default/49.sram_ctrl_bijection.1229935900
/workspace/coverage/default/49.sram_ctrl_executable.2909800077
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1298645897
/workspace/coverage/default/49.sram_ctrl_max_throughput.3066054510
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2201670335
/workspace/coverage/default/49.sram_ctrl_mem_walk.1404636247
/workspace/coverage/default/49.sram_ctrl_multiple_keys.846593139
/workspace/coverage/default/49.sram_ctrl_partial_access.2816487527
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.2761967065
/workspace/coverage/default/49.sram_ctrl_ram_cfg.2979541563
/workspace/coverage/default/49.sram_ctrl_regwen.3138166040
/workspace/coverage/default/49.sram_ctrl_smoke.63413719
/workspace/coverage/default/49.sram_ctrl_stress_all.3117488950
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.1054194893
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2472650907
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3079125940
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.3601503711
/workspace/coverage/default/5.sram_ctrl_alert_test.3425258881
/workspace/coverage/default/5.sram_ctrl_bijection.1822234545
/workspace/coverage/default/5.sram_ctrl_executable.1539629667
/workspace/coverage/default/5.sram_ctrl_lc_escalation.192026915
/workspace/coverage/default/5.sram_ctrl_max_throughput.58897848
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.3701687466
/workspace/coverage/default/5.sram_ctrl_mem_walk.1550546400
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1434734123
/workspace/coverage/default/5.sram_ctrl_partial_access.84767190
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2657129068
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2311742590
/workspace/coverage/default/5.sram_ctrl_regwen.1465803892
/workspace/coverage/default/5.sram_ctrl_smoke.3628892432
/workspace/coverage/default/5.sram_ctrl_stress_all.1449868608
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4292177433
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1190217856
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3157767176
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2597645728
/workspace/coverage/default/6.sram_ctrl_alert_test.1673773282
/workspace/coverage/default/6.sram_ctrl_bijection.134427037
/workspace/coverage/default/6.sram_ctrl_executable.3920838959
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1839826592
/workspace/coverage/default/6.sram_ctrl_max_throughput.2048959816
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.1521159178
/workspace/coverage/default/6.sram_ctrl_mem_walk.1498387650
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3372396734
/workspace/coverage/default/6.sram_ctrl_partial_access.3208073703
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1491790093
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3198939686
/workspace/coverage/default/6.sram_ctrl_regwen.35858464
/workspace/coverage/default/6.sram_ctrl_smoke.293774118
/workspace/coverage/default/6.sram_ctrl_stress_all.2576385981
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.2221017735
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.4161849359
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2407717317
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.221084178
/workspace/coverage/default/7.sram_ctrl_alert_test.2641152588
/workspace/coverage/default/7.sram_ctrl_bijection.2794907260
/workspace/coverage/default/7.sram_ctrl_executable.2239031741
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2174348129
/workspace/coverage/default/7.sram_ctrl_max_throughput.3830407754
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3752516357
/workspace/coverage/default/7.sram_ctrl_mem_walk.2189993094
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3421120298
/workspace/coverage/default/7.sram_ctrl_partial_access.434527745
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.3307506029
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1086980951
/workspace/coverage/default/7.sram_ctrl_regwen.199881114
/workspace/coverage/default/7.sram_ctrl_smoke.397723786
/workspace/coverage/default/7.sram_ctrl_stress_all.4206702817
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3424810474
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.531307395
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1226379484
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.672894578
/workspace/coverage/default/8.sram_ctrl_alert_test.3070742508
/workspace/coverage/default/8.sram_ctrl_bijection.1769827839
/workspace/coverage/default/8.sram_ctrl_executable.2149022274
/workspace/coverage/default/8.sram_ctrl_lc_escalation.1378509214
/workspace/coverage/default/8.sram_ctrl_max_throughput.4111168186
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.308101141
/workspace/coverage/default/8.sram_ctrl_mem_walk.2892784802
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3386392937
/workspace/coverage/default/8.sram_ctrl_partial_access.701535762
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1853136455
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1763995809
/workspace/coverage/default/8.sram_ctrl_regwen.1983296720
/workspace/coverage/default/8.sram_ctrl_smoke.4263188411
/workspace/coverage/default/8.sram_ctrl_stress_all.1654518074
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.1936306362
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.800820657
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.272372567
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1065493930
/workspace/coverage/default/9.sram_ctrl_alert_test.3393919179
/workspace/coverage/default/9.sram_ctrl_bijection.174640920
/workspace/coverage/default/9.sram_ctrl_executable.2544509433
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1748351876
/workspace/coverage/default/9.sram_ctrl_max_throughput.358974409
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.2506728686
/workspace/coverage/default/9.sram_ctrl_mem_walk.4036488075
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3209733365
/workspace/coverage/default/9.sram_ctrl_partial_access.1613051087
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2367325401
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3913158355
/workspace/coverage/default/9.sram_ctrl_regwen.2848117065
/workspace/coverage/default/9.sram_ctrl_smoke.696503788
/workspace/coverage/default/9.sram_ctrl_stress_all.1587038905
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2523475211
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.833941545
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.538699016



Total test records in report: 1020
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.2082227428 Mar 31 02:34:19 PM PDT 24 Mar 31 02:34:25 PM PDT 24 1019902490 ps
T2 /workspace/coverage/default/15.sram_ctrl_ram_cfg.1365519601 Mar 31 02:30:32 PM PDT 24 Mar 31 02:30:33 PM PDT 24 26296549 ps
T3 /workspace/coverage/default/27.sram_ctrl_regwen.2089850243 Mar 31 02:33:15 PM PDT 24 Mar 31 02:43:24 PM PDT 24 3877752201 ps
T4 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1521159178 Mar 31 02:29:31 PM PDT 24 Mar 31 02:29:35 PM PDT 24 173275927 ps
T9 /workspace/coverage/default/16.sram_ctrl_regwen.105333708 Mar 31 02:30:46 PM PDT 24 Mar 31 02:55:34 PM PDT 24 2581153509 ps
T10 /workspace/coverage/default/10.sram_ctrl_max_throughput.1725926182 Mar 31 02:29:41 PM PDT 24 Mar 31 02:32:11 PM PDT 24 145689572 ps
T5 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2551693433 Mar 31 02:36:26 PM PDT 24 Mar 31 02:44:44 PM PDT 24 6083957652 ps
T11 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.3510028654 Mar 31 02:31:06 PM PDT 24 Mar 31 02:40:51 PM PDT 24 1201142803 ps
T12 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.2836083219 Mar 31 02:31:58 PM PDT 24 Mar 31 02:32:28 PM PDT 24 102156988 ps
T13 /workspace/coverage/default/34.sram_ctrl_multiple_keys.3279817705 Mar 31 02:34:13 PM PDT 24 Mar 31 02:46:18 PM PDT 24 18158662299 ps
T14 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.1246687377 Mar 31 02:33:27 PM PDT 24 Mar 31 02:33:30 PM PDT 24 371538264 ps
T16 /workspace/coverage/default/6.sram_ctrl_smoke.293774118 Mar 31 02:29:21 PM PDT 24 Mar 31 02:29:30 PM PDT 24 1689796983 ps
T46 /workspace/coverage/default/25.sram_ctrl_max_throughput.3225857871 Mar 31 02:32:19 PM PDT 24 Mar 31 02:34:47 PM PDT 24 541618367 ps
T29 /workspace/coverage/default/42.sram_ctrl_partial_access.3146027201 Mar 31 02:36:05 PM PDT 24 Mar 31 02:36:46 PM PDT 24 1463611596 ps
T30 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2201670335 Mar 31 02:37:36 PM PDT 24 Mar 31 02:37:40 PM PDT 24 457386928 ps
T50 /workspace/coverage/default/7.sram_ctrl_max_throughput.3830407754 Mar 31 02:29:29 PM PDT 24 Mar 31 02:29:51 PM PDT 24 71922619 ps
T75 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.4043192699 Mar 31 02:31:50 PM PDT 24 Mar 31 02:35:46 PM PDT 24 10024186950 ps
T96 /workspace/coverage/default/33.sram_ctrl_max_throughput.2641833663 Mar 31 02:34:06 PM PDT 24 Mar 31 02:34:09 PM PDT 24 50940206 ps
T51 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.2657129068 Mar 31 02:29:16 PM PDT 24 Mar 31 02:36:10 PM PDT 24 67466217963 ps
T17 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1218212506 Mar 31 02:30:34 PM PDT 24 Mar 31 02:31:10 PM PDT 24 2252075205 ps
T57 /workspace/coverage/default/38.sram_ctrl_smoke.885383830 Mar 31 02:35:15 PM PDT 24 Mar 31 02:35:51 PM PDT 24 375032341 ps
T58 /workspace/coverage/default/28.sram_ctrl_stress_pipeline.2769053512 Mar 31 02:33:21 PM PDT 24 Mar 31 02:36:51 PM PDT 24 10553589997 ps
T59 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.650199279 Mar 31 02:29:03 PM PDT 24 Mar 31 02:29:06 PM PDT 24 43475769 ps
T33 /workspace/coverage/default/16.sram_ctrl_ram_cfg.3757733136 Mar 31 02:30:45 PM PDT 24 Mar 31 02:30:46 PM PDT 24 30669009 ps
T18 /workspace/coverage/default/41.sram_ctrl_access_during_key_req.3241179615 Mar 31 02:36:01 PM PDT 24 Mar 31 02:51:01 PM PDT 24 7622102001 ps
T60 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.3768712399 Mar 31 02:36:07 PM PDT 24 Mar 31 02:41:56 PM PDT 24 10145271021 ps
T15 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1538230958 Mar 31 02:32:03 PM PDT 24 Mar 31 02:38:22 PM PDT 24 87594525039 ps
T61 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.2851956688 Mar 31 02:35:06 PM PDT 24 Mar 31 02:35:11 PM PDT 24 794429843 ps
T26 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3876665250 Mar 31 02:33:44 PM PDT 24 Mar 31 02:35:48 PM PDT 24 744899553 ps
T133 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1281956418 Mar 31 02:32:36 PM PDT 24 Mar 31 02:34:03 PM PDT 24 307976445 ps
T19 /workspace/coverage/default/23.sram_ctrl_alert_test.4239238063 Mar 31 02:32:04 PM PDT 24 Mar 31 02:32:05 PM PDT 24 72883264 ps
T130 /workspace/coverage/default/20.sram_ctrl_bijection.664446693 Mar 31 02:31:17 PM PDT 24 Mar 31 02:32:16 PM PDT 24 2018199478 ps
T6 /workspace/coverage/default/22.sram_ctrl_lc_escalation.140664224 Mar 31 02:31:48 PM PDT 24 Mar 31 02:31:54 PM PDT 24 769489783 ps
T78 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.3800021584 Mar 31 02:31:16 PM PDT 24 Mar 31 02:50:05 PM PDT 24 8189469321 ps
T32 /workspace/coverage/default/43.sram_ctrl_stress_all.785449884 Mar 31 02:36:33 PM PDT 24 Mar 31 03:29:16 PM PDT 24 13112185123 ps
T62 /workspace/coverage/default/30.sram_ctrl_regwen.517230430 Mar 31 02:33:28 PM PDT 24 Mar 31 02:44:38 PM PDT 24 13472064939 ps
T135 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2763582587 Mar 31 02:30:17 PM PDT 24 Mar 31 02:31:18 PM PDT 24 116844907 ps
T7 /workspace/coverage/default/48.sram_ctrl_lc_escalation.2086132452 Mar 31 02:37:18 PM PDT 24 Mar 31 02:37:22 PM PDT 24 391130843 ps
T8 /workspace/coverage/default/41.sram_ctrl_lc_escalation.821910916 Mar 31 02:36:01 PM PDT 24 Mar 31 02:36:06 PM PDT 24 840365753 ps
T63 /workspace/coverage/default/32.sram_ctrl_stress_all.1971356877 Mar 31 02:33:58 PM PDT 24 Mar 31 03:00:35 PM PDT 24 20272742764 ps
T136 /workspace/coverage/default/35.sram_ctrl_smoke.3096623260 Mar 31 02:34:28 PM PDT 24 Mar 31 02:36:31 PM PDT 24 549287136 ps
T134 /workspace/coverage/default/49.sram_ctrl_smoke.63413719 Mar 31 02:37:27 PM PDT 24 Mar 31 02:37:43 PM PDT 24 3153525102 ps
T20 /workspace/coverage/default/35.sram_ctrl_alert_test.1025850489 Mar 31 02:34:48 PM PDT 24 Mar 31 02:34:49 PM PDT 24 25745610 ps
T129 /workspace/coverage/default/15.sram_ctrl_executable.1186839532 Mar 31 02:30:29 PM PDT 24 Mar 31 02:35:23 PM PDT 24 1962589825 ps
T131 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.3601503711 Mar 31 02:29:24 PM PDT 24 Mar 31 02:42:53 PM PDT 24 2477277000 ps
T93 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.2711714088 Mar 31 02:34:12 PM PDT 24 Mar 31 02:37:52 PM PDT 24 12656528856 ps
T137 /workspace/coverage/default/3.sram_ctrl_mem_walk.25176805 Mar 31 02:29:04 PM PDT 24 Mar 31 02:29:15 PM PDT 24 578643921 ps
T34 /workspace/coverage/default/41.sram_ctrl_ram_cfg.3247127371 Mar 31 02:35:59 PM PDT 24 Mar 31 02:36:00 PM PDT 24 95462022 ps
T21 /workspace/coverage/default/28.sram_ctrl_alert_test.2128443130 Mar 31 02:33:20 PM PDT 24 Mar 31 02:33:21 PM PDT 24 49475528 ps
T31 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4292177433 Mar 31 02:29:24 PM PDT 24 Mar 31 02:30:49 PM PDT 24 1607695606 ps
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T159 /workspace/coverage/default/48.sram_ctrl_multiple_keys.521163934 Mar 31 02:37:18 PM PDT 24 Mar 31 02:41:25 PM PDT 24 1568889420 ps
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T161 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2296810200 Mar 31 02:36:25 PM PDT 24 Mar 31 02:39:17 PM PDT 24 3545648769 ps
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T55 /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3424810474 Mar 31 02:29:31 PM PDT 24 Mar 31 02:33:59 PM PDT 24 5071432316 ps
T23 /workspace/coverage/default/4.sram_ctrl_sec_cm.3048598667 Mar 31 02:29:18 PM PDT 24 Mar 31 02:29:22 PM PDT 24 2178703060 ps
T37 /workspace/coverage/default/13.sram_ctrl_max_throughput.1227408411 Mar 31 02:30:11 PM PDT 24 Mar 31 02:30:45 PM PDT 24 118563432 ps
T38 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.1030895953 Mar 31 02:36:00 PM PDT 24 Mar 31 02:40:41 PM PDT 24 6014991509 ps
T39 /workspace/coverage/default/9.sram_ctrl_max_throughput.358974409 Mar 31 02:29:37 PM PDT 24 Mar 31 02:29:43 PM PDT 24 68802245 ps
T40 /workspace/coverage/default/19.sram_ctrl_partial_access_b2b.1975126476 Mar 31 02:31:10 PM PDT 24 Mar 31 02:37:39 PM PDT 24 15727645378 ps
T41 /workspace/coverage/default/11.sram_ctrl_executable.182797550 Mar 31 02:29:54 PM PDT 24 Mar 31 02:47:06 PM PDT 24 17679813286 ps
T42 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.217099798 Mar 31 02:29:09 PM PDT 24 Mar 31 02:34:24 PM PDT 24 12441173697 ps
T43 /workspace/coverage/default/15.sram_ctrl_regwen.876541709 Mar 31 02:30:29 PM PDT 24 Mar 31 02:49:20 PM PDT 24 3245437826 ps
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T45 /workspace/coverage/default/8.sram_ctrl_ram_cfg.1763995809 Mar 31 02:29:36 PM PDT 24 Mar 31 02:29:38 PM PDT 24 53175213 ps
T164 /workspace/coverage/default/7.sram_ctrl_executable.2239031741 Mar 31 02:29:29 PM PDT 24 Mar 31 02:42:52 PM PDT 24 9303638701 ps
T165 /workspace/coverage/default/10.sram_ctrl_multiple_keys.773796059 Mar 31 02:29:40 PM PDT 24 Mar 31 02:42:09 PM PDT 24 25488662820 ps
T166 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.797063986 Mar 31 02:33:17 PM PDT 24 Mar 31 02:35:04 PM PDT 24 581244279 ps
T167 /workspace/coverage/default/20.sram_ctrl_mem_walk.4064193857 Mar 31 02:31:27 PM PDT 24 Mar 31 02:31:32 PM PDT 24 272495165 ps
T168 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.4017289591 Mar 31 02:36:41 PM PDT 24 Mar 31 02:42:15 PM PDT 24 7296994382 ps
T169 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.4167150956 Mar 31 02:31:11 PM PDT 24 Mar 31 02:31:13 PM PDT 24 138613353 ps
T109 /workspace/coverage/default/18.sram_ctrl_lc_escalation.3610634886 Mar 31 02:31:06 PM PDT 24 Mar 31 02:31:09 PM PDT 24 311019492 ps
T170 /workspace/coverage/default/32.sram_ctrl_max_throughput.1131163176 Mar 31 02:33:56 PM PDT 24 Mar 31 02:34:03 PM PDT 24 55241779 ps
T171 /workspace/coverage/default/27.sram_ctrl_max_throughput.664111247 Mar 31 02:32:38 PM PDT 24 Mar 31 02:32:49 PM PDT 24 95254294 ps
T172 /workspace/coverage/default/44.sram_ctrl_regwen.3328894652 Mar 31 02:36:41 PM PDT 24 Mar 31 03:03:19 PM PDT 24 12321961178 ps
T173 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.3426652224 Mar 31 02:29:47 PM PDT 24 Mar 31 02:29:52 PM PDT 24 232539157 ps
T174 /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1226379484 Mar 31 02:29:29 PM PDT 24 Mar 31 02:30:25 PM PDT 24 114267113 ps
T175 /workspace/coverage/default/36.sram_ctrl_mem_partial_access.2408909133 Mar 31 02:34:57 PM PDT 24 Mar 31 02:35:00 PM PDT 24 347637000 ps
T123 /workspace/coverage/default/13.sram_ctrl_regwen.2940391361 Mar 31 02:30:11 PM PDT 24 Mar 31 02:44:31 PM PDT 24 2443578009 ps
T176 /workspace/coverage/default/31.sram_ctrl_stress_pipeline.2547138167 Mar 31 02:33:30 PM PDT 24 Mar 31 02:38:45 PM PDT 24 12448709251 ps
T177 /workspace/coverage/default/17.sram_ctrl_alert_test.1464136293 Mar 31 02:30:58 PM PDT 24 Mar 31 02:30:59 PM PDT 24 16489948 ps
T178 /workspace/coverage/default/27.sram_ctrl_mem_walk.1359238188 Mar 31 02:33:14 PM PDT 24 Mar 31 02:33:20 PM PDT 24 692355979 ps
T179 /workspace/coverage/default/29.sram_ctrl_max_throughput.3118299439 Mar 31 02:33:21 PM PDT 24 Mar 31 02:33:22 PM PDT 24 57230897 ps
T180 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.820300161 Mar 31 02:33:08 PM PDT 24 Mar 31 02:38:20 PM PDT 24 3152696911 ps
T181 /workspace/coverage/default/24.sram_ctrl_alert_test.4279106083 Mar 31 02:32:19 PM PDT 24 Mar 31 02:32:20 PM PDT 24 19440906 ps
T182 /workspace/coverage/default/34.sram_ctrl_ram_cfg.1621098493 Mar 31 02:34:21 PM PDT 24 Mar 31 02:34:22 PM PDT 24 78283742 ps
T183 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1118722340 Mar 31 02:33:57 PM PDT 24 Mar 31 02:38:59 PM PDT 24 6446386474 ps
T184 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.378396495 Mar 31 02:35:36 PM PDT 24 Mar 31 02:46:24 PM PDT 24 1798817831 ps
T185 /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2076065532 Mar 31 02:30:11 PM PDT 24 Mar 31 02:30:15 PM PDT 24 67250258 ps
T186 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.393041139 Mar 31 02:29:02 PM PDT 24 Mar 31 02:31:56 PM PDT 24 36259875163 ps
T187 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.363364269 Mar 31 02:34:20 PM PDT 24 Mar 31 02:46:19 PM PDT 24 10565228543 ps
T188 /workspace/coverage/default/23.sram_ctrl_mem_walk.431765790 Mar 31 02:31:56 PM PDT 24 Mar 31 02:32:06 PM PDT 24 1307185594 ps
T189 /workspace/coverage/default/39.sram_ctrl_smoke.3852209879 Mar 31 02:35:27 PM PDT 24 Mar 31 02:35:34 PM PDT 24 993767628 ps
T190 /workspace/coverage/default/41.sram_ctrl_stress_all.3154767050 Mar 31 02:36:06 PM PDT 24 Mar 31 03:03:17 PM PDT 24 6949053287 ps
T191 /workspace/coverage/default/47.sram_ctrl_ram_cfg.4284567447 Mar 31 02:37:13 PM PDT 24 Mar 31 02:37:14 PM PDT 24 74358502 ps
T192 /workspace/coverage/default/25.sram_ctrl_regwen.3537825280 Mar 31 02:32:27 PM PDT 24 Mar 31 02:35:54 PM PDT 24 791915447 ps
T48 /workspace/coverage/default/10.sram_ctrl_stress_all.659426816 Mar 31 02:29:46 PM PDT 24 Mar 31 03:26:18 PM PDT 24 50932631478 ps
T193 /workspace/coverage/default/32.sram_ctrl_mem_walk.1632045600 Mar 31 02:33:58 PM PDT 24 Mar 31 02:34:08 PM PDT 24 576171072 ps
T194 /workspace/coverage/default/32.sram_ctrl_bijection.4195436794 Mar 31 02:33:45 PM PDT 24 Mar 31 02:34:16 PM PDT 24 8486859766 ps
T195 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.661823049 Mar 31 02:28:51 PM PDT 24 Mar 31 02:46:27 PM PDT 24 6880198074 ps
T196 /workspace/coverage/default/22.sram_ctrl_mem_walk.3449330014 Mar 31 02:31:48 PM PDT 24 Mar 31 02:31:52 PM PDT 24 78710179 ps
T197 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.3518615544 Mar 31 02:35:48 PM PDT 24 Mar 31 02:35:51 PM PDT 24 91126718 ps
T56 /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1470705863 Mar 31 02:30:06 PM PDT 24 Mar 31 02:47:22 PM PDT 24 2412382954 ps
T198 /workspace/coverage/default/36.sram_ctrl_partial_access.4120442609 Mar 31 02:34:49 PM PDT 24 Mar 31 02:35:01 PM PDT 24 596046571 ps
T199 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.102582595 Mar 31 02:35:36 PM PDT 24 Mar 31 02:40:59 PM PDT 24 77771401298 ps
T49 /workspace/coverage/default/19.sram_ctrl_executable.353209591 Mar 31 02:31:16 PM PDT 24 Mar 31 02:49:31 PM PDT 24 88464175462 ps
T200 /workspace/coverage/default/30.sram_ctrl_partial_access.2666508154 Mar 31 02:33:28 PM PDT 24 Mar 31 02:35:25 PM PDT 24 2443681622 ps
T201 /workspace/coverage/default/1.sram_ctrl_ram_cfg.3295413314 Mar 31 02:28:59 PM PDT 24 Mar 31 02:28:59 PM PDT 24 28722846 ps
T202 /workspace/coverage/default/9.sram_ctrl_alert_test.3393919179 Mar 31 02:29:41 PM PDT 24 Mar 31 02:29:42 PM PDT 24 23083957 ps
T203 /workspace/coverage/default/9.sram_ctrl_ram_cfg.3913158355 Mar 31 02:29:43 PM PDT 24 Mar 31 02:29:44 PM PDT 24 83043398 ps
T204 /workspace/coverage/default/3.sram_ctrl_stress_all.3961480288 Mar 31 02:29:09 PM PDT 24 Mar 31 03:02:51 PM PDT 24 24833390538 ps
T205 /workspace/coverage/default/48.sram_ctrl_mem_partial_access.3523513024 Mar 31 02:37:25 PM PDT 24 Mar 31 02:37:29 PM PDT 24 77973274 ps
T206 /workspace/coverage/default/4.sram_ctrl_partial_access.3705926654 Mar 31 02:29:10 PM PDT 24 Mar 31 02:30:42 PM PDT 24 1342965847 ps
T207 /workspace/coverage/default/12.sram_ctrl_max_throughput.1264003048 Mar 31 02:29:58 PM PDT 24 Mar 31 02:30:20 PM PDT 24 82227394 ps
T208 /workspace/coverage/default/43.sram_ctrl_alert_test.1539694058 Mar 31 02:36:33 PM PDT 24 Mar 31 02:36:35 PM PDT 24 199168800 ps
T209 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.180592554 Mar 31 02:30:11 PM PDT 24 Mar 31 02:35:49 PM PDT 24 24484580532 ps
T210 /workspace/coverage/default/43.sram_ctrl_max_throughput.4262417246 Mar 31 02:36:25 PM PDT 24 Mar 31 02:36:48 PM PDT 24 420695967 ps
T211 /workspace/coverage/default/42.sram_ctrl_multiple_keys.4134659701 Mar 31 02:36:06 PM PDT 24 Mar 31 03:05:36 PM PDT 24 15966410533 ps
T212 /workspace/coverage/default/5.sram_ctrl_mem_walk.1550546400 Mar 31 02:29:31 PM PDT 24 Mar 31 02:29:37 PM PDT 24 336466129 ps
T213 /workspace/coverage/default/38.sram_ctrl_mem_walk.4217764969 Mar 31 02:35:21 PM PDT 24 Mar 31 02:35:28 PM PDT 24 3184577946 ps
T214 /workspace/coverage/default/17.sram_ctrl_bijection.3140810623 Mar 31 02:30:52 PM PDT 24 Mar 31 02:31:20 PM PDT 24 6450993331 ps
T215 /workspace/coverage/default/31.sram_ctrl_regwen.3909534409 Mar 31 02:33:42 PM PDT 24 Mar 31 02:44:31 PM PDT 24 9702252050 ps
T216 /workspace/coverage/default/35.sram_ctrl_mem_walk.2499465844 Mar 31 02:34:41 PM PDT 24 Mar 31 02:34:46 PM PDT 24 143757966 ps
T217 /workspace/coverage/default/44.sram_ctrl_partial_access.1022178318 Mar 31 02:36:33 PM PDT 24 Mar 31 02:36:51 PM PDT 24 358457285 ps
T218 /workspace/coverage/default/35.sram_ctrl_multiple_keys.2495722682 Mar 31 02:34:29 PM PDT 24 Mar 31 02:40:40 PM PDT 24 6154018094 ps
T219 /workspace/coverage/default/7.sram_ctrl_regwen.199881114 Mar 31 02:29:34 PM PDT 24 Mar 31 02:52:42 PM PDT 24 15109795266 ps
T220 /workspace/coverage/default/17.sram_ctrl_stress_all.148913532 Mar 31 02:30:58 PM PDT 24 Mar 31 02:57:01 PM PDT 24 7285477402 ps
T221 /workspace/coverage/default/31.sram_ctrl_multiple_keys.784935629 Mar 31 02:33:27 PM PDT 24 Mar 31 02:44:07 PM PDT 24 42323337307 ps
T222 /workspace/coverage/default/7.sram_ctrl_alert_test.2641152588 Mar 31 02:29:28 PM PDT 24 Mar 31 02:29:29 PM PDT 24 38796532 ps
T223 /workspace/coverage/default/19.sram_ctrl_ram_cfg.2028423391 Mar 31 02:31:14 PM PDT 24 Mar 31 02:31:15 PM PDT 24 32350335 ps
T224 /workspace/coverage/default/8.sram_ctrl_bijection.1769827839 Mar 31 02:29:29 PM PDT 24 Mar 31 02:30:44 PM PDT 24 9961427361 ps
T225 /workspace/coverage/default/18.sram_ctrl_ram_cfg.1146341536 Mar 31 02:31:05 PM PDT 24 Mar 31 02:31:06 PM PDT 24 86087858 ps
T226 /workspace/coverage/default/30.sram_ctrl_max_throughput.2879843965 Mar 31 02:33:28 PM PDT 24 Mar 31 02:35:45 PM PDT 24 532926803 ps
T227 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.4193979249 Mar 31 02:36:01 PM PDT 24 Mar 31 02:36:06 PM PDT 24 355080036 ps
T228 /workspace/coverage/default/30.sram_ctrl_mem_walk.2999317179 Mar 31 02:33:24 PM PDT 24 Mar 31 02:33:33 PM PDT 24 915365673 ps
T229 /workspace/coverage/default/30.sram_ctrl_ram_cfg.1962540609 Mar 31 02:33:26 PM PDT 24 Mar 31 02:33:27 PM PDT 24 38504112 ps
T230 /workspace/coverage/default/16.sram_ctrl_bijection.2042100593 Mar 31 02:30:38 PM PDT 24 Mar 31 02:30:59 PM PDT 24 1338004656 ps
T231 /workspace/coverage/default/23.sram_ctrl_max_throughput.3012679998 Mar 31 02:31:57 PM PDT 24 Mar 31 02:31:59 PM PDT 24 43036910 ps
T232 /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2472650907 Mar 31 02:37:25 PM PDT 24 Mar 31 02:41:33 PM PDT 24 5292854035 ps
T233 /workspace/coverage/default/28.sram_ctrl_mem_walk.1818930195 Mar 31 02:33:19 PM PDT 24 Mar 31 02:33:25 PM PDT 24 571888233 ps
T234 /workspace/coverage/default/46.sram_ctrl_mem_walk.1739856841 Mar 31 02:37:04 PM PDT 24 Mar 31 02:37:14 PM PDT 24 2113499005 ps
T235 /workspace/coverage/default/28.sram_ctrl_stress_all.1840796640 Mar 31 02:33:17 PM PDT 24 Mar 31 03:07:50 PM PDT 24 6094760247 ps
T236 /workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2714465744 Mar 31 02:34:09 PM PDT 24 Mar 31 02:39:56 PM PDT 24 5050975833 ps
T237 /workspace/coverage/default/47.sram_ctrl_partial_access.234334244 Mar 31 02:37:04 PM PDT 24 Mar 31 02:37:22 PM PDT 24 885611839 ps
T238 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.661892443 Mar 31 02:37:13 PM PDT 24 Mar 31 02:37:16 PM PDT 24 50207161 ps
T239 /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1332461411 Mar 31 02:36:34 PM PDT 24 Mar 31 02:37:55 PM PDT 24 125093632 ps
T240 /workspace/coverage/default/45.sram_ctrl_smoke.1654571557 Mar 31 02:36:42 PM PDT 24 Mar 31 02:38:38 PM PDT 24 822696117 ps
T241 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3549491533 Mar 31 02:37:18 PM PDT 24 Mar 31 02:37:46 PM PDT 24 164334988 ps
T242 /workspace/coverage/default/4.sram_ctrl_multiple_keys.1210743505 Mar 31 02:29:13 PM PDT 24 Mar 31 02:36:40 PM PDT 24 29728480532 ps
T243 /workspace/coverage/default/8.sram_ctrl_multiple_keys.3386392937 Mar 31 02:29:31 PM PDT 24 Mar 31 02:51:12 PM PDT 24 39201117323 ps
T244 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.2493879777 Mar 31 02:34:56 PM PDT 24 Mar 31 02:50:56 PM PDT 24 14235135997 ps
T245 /workspace/coverage/default/29.sram_ctrl_mem_walk.1209808460 Mar 31 02:33:23 PM PDT 24 Mar 31 02:33:33 PM PDT 24 678989515 ps
T246 /workspace/coverage/default/11.sram_ctrl_regwen.825271446 Mar 31 02:29:53 PM PDT 24 Mar 31 02:44:30 PM PDT 24 32269649698 ps
T247 /workspace/coverage/default/15.sram_ctrl_partial_access_b2b.2018219828 Mar 31 02:30:25 PM PDT 24 Mar 31 02:36:08 PM PDT 24 11538600422 ps
T248 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.914668552 Mar 31 02:29:54 PM PDT 24 Mar 31 02:30:38 PM PDT 24 424287663 ps
T249 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.2115192276 Mar 31 02:31:36 PM PDT 24 Mar 31 02:32:07 PM PDT 24 1879797357 ps
T250 /workspace/coverage/default/4.sram_ctrl_regwen.198390066 Mar 31 02:29:12 PM PDT 24 Mar 31 02:39:20 PM PDT 24 8104907093 ps
T251 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1876224920 Mar 31 02:36:01 PM PDT 24 Mar 31 02:36:09 PM PDT 24 78908292 ps
T252 /workspace/coverage/default/34.sram_ctrl_mem_walk.3986617060 Mar 31 02:34:20 PM PDT 24 Mar 31 02:34:25 PM PDT 24 245686562 ps
T253 /workspace/coverage/default/26.sram_ctrl_partial_access_b2b.4247152395 Mar 31 02:32:32 PM PDT 24 Mar 31 02:35:57 PM PDT 24 6262868972 ps
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T124 /workspace/coverage/default/5.sram_ctrl_executable.1539629667 Mar 31 02:29:23 PM PDT 24 Mar 31 02:34:30 PM PDT 24 12417857831 ps
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T264 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.272372567 Mar 31 02:29:39 PM PDT 24 Mar 31 02:31:52 PM PDT 24 151725847 ps
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T304 /workspace/coverage/default/33.sram_ctrl_mem_walk.2630043372 Mar 31 02:34:05 PM PDT 24 Mar 31 02:34:14 PM PDT 24 168483925 ps
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