Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	152562648	1			T1	110374		T2	309956		T3	179770
instr_valid_dis	118522240	1			T1	110374		T2	309956		T3	179770
instr_en	24240362	1			T9	221810		T12	6044		T5	140576

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10912492	1			T9	26934		T11	79706		T5	90132
sram_ifetch_valid_disable	117561452	1			T1	110374		T2	309956		T3	179770
sram_ifetch_enable	24088704	1			T9	303324		T11	49824		T5	405604

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	152562648	1			T1	110374		T2	309956		T3	179770
hw_debug_en_valid_off	115017585	1			T1	110374		T2	309956		T3	179770
hw_debug_en_on	25786800	1			T9	146800		T11	103218		T12	14804

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	117561452	1			T1	110374		T2	309956		T3	179770
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	102168008	1			T1	110374		T2	309956		T3	179770
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	10452230	1			T9	68424		T12	6044		T5	41996
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4417512	1			T9	26934		T47	14868		T6	54644
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1997298	1			T9	26934		T6	22744		T125	81168
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1518418	1			T6	31900		T39	35826		T128	33546
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4337274	1			T11	79706		T5	85086		T47	44620
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1820932	1			T11	79706		T5	85086		T6	17916
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	2057640	1			T6	54812		T91	7258		T129	15642
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10339314	1			T9	44220		T12	14804		T5	193460
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3850408	1			T12	8760		T5	56038		T47	48782
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	4735512	1			T9	44120		T12	6044		T5	27188

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9222416	1			T9	153386		T5	93534		T47	20000
lc_exec_en	11110212	1			T9	102580		T11	23512		T5	311884
valid_exec_dis	114155473	1			T1	110374		T2	309956		T3	179770
invalid_exec_dis	35001196	1			T9	330258		T11	129530		T5	495736