| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1901314615 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2501976528 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2903709219 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.944814886 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4120810010 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1883195671 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3606293139 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4014851967 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2195313821 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3717592467 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2135485598 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3556490278 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1036667832 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2030695960 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3194291906 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2159232911 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.529675538 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.432015666 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2282376368 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.687306289 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2837098615 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2928570831 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3673780141 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2806079839 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3137742497 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2853311375 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.17411444 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.412213301 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3984508062 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3219114145 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.940184671 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.919772288 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4048098977 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.352421973 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3576614632 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1979691488 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.4081405181 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3250362991 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.682019137 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3948661542 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.20997325 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.945716914 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2786696831 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4145376841 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3707358923 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2107328746 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3493815746 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3247995522 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2399379374 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2249193792 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1846006046 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.893380976 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3771491361 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.552065115 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1181178684 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.961101017 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.861764823 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.995494075 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.865837485 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.482572537 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3915117116 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.728615732 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2553456142 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2573288685 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3066700020 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2772246059 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.644708302 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2611965322 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.308701173 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1986542214 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2200112852 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2250270182 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3566309678 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1089181618 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.267625264 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2090828110 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.106082548 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3285392770 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1897844025 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.4012265085 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.236061751 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2283195800 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.245596947 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2436193886 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2687463320 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3725682360 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3995653877 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1062939482 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2768727669 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2861316001 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.832786478 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3824537260 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1982641733 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3042031717 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2554646898 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3749718228 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1794672288 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3922248112 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3969534819 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2661283186 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.623753817 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.797557877 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.268725175 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1356470230 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.788579644 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3555741016 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3649346989 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3168953971 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.208485494 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1092520841 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3193977720 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2760178098 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3986660916 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2689127778 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2380996785 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3744842644 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3478931682 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.158644612 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2747007378 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3301294358 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2849931797 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.831857347 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1067819172 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.944144386 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2373745653 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1556377121 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1402620996 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3373990224 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.1230123801 |
| /workspace/coverage/default/0.sram_ctrl_bijection.1870781071 |
| /workspace/coverage/default/0.sram_ctrl_executable.1312803468 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.3414316025 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.2307806400 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.3244050170 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.3758031738 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.1257813689 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1706099750 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.1448039896 |
| /workspace/coverage/default/0.sram_ctrl_regwen.3747911733 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.3456973554 |
| /workspace/coverage/default/0.sram_ctrl_smoke.487975188 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.2087372578 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1722100718 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.3826764271 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2580705002 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.2385650114 |
| /workspace/coverage/default/1.sram_ctrl_alert_test.3334340589 |
| /workspace/coverage/default/1.sram_ctrl_bijection.3461659940 |
| /workspace/coverage/default/1.sram_ctrl_executable.4173552149 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.3698440675 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.4057062527 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1060527289 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.3948075379 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.711988815 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.3553953676 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3470970809 |
| /workspace/coverage/default/1.sram_ctrl_regwen.1635336452 |
| /workspace/coverage/default/1.sram_ctrl_sec_cm.3894326948 |
| /workspace/coverage/default/1.sram_ctrl_smoke.3697846355 |
| /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.3506326658 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.3681549933 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.1701614760 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.522290256 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.1988361365 |
| /workspace/coverage/default/10.sram_ctrl_bijection.2875413161 |
| /workspace/coverage/default/10.sram_ctrl_executable.1768746898 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.289201702 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.2385412218 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.472776116 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.581598617 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.3175980083 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.2331843841 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2529434150 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.917916638 |
| /workspace/coverage/default/10.sram_ctrl_regwen.1289765358 |
| /workspace/coverage/default/10.sram_ctrl_smoke.1597445507 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.3714525205 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.608054632 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3159757462 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.1944257871 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.1891472504 |
| /workspace/coverage/default/11.sram_ctrl_executable.357358768 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.931040400 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.495137540 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3269967870 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.2548027820 |
| /workspace/coverage/default/11.sram_ctrl_multiple_keys.3425623571 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.2400718660 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1026712322 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.4126452465 |
| /workspace/coverage/default/11.sram_ctrl_regwen.1306605551 |
| /workspace/coverage/default/11.sram_ctrl_smoke.326847112 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.3026799366 |
| /workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.43901575 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.555515878 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2474724315 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.513742743 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.3138858063 |
| /workspace/coverage/default/12.sram_ctrl_bijection.3366039516 |
| /workspace/coverage/default/12.sram_ctrl_executable.2714760641 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.3860056062 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.2174584186 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.1620159846 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.2405012929 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.792023335 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.3515128316 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.1030529694 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.3938969426 |
| /workspace/coverage/default/12.sram_ctrl_regwen.806686377 |
| /workspace/coverage/default/12.sram_ctrl_smoke.1712154781 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.1000726396 |
| /workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1714029355 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.629504420 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.2983759689 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.3480566437 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.1755108599 |
| /workspace/coverage/default/13.sram_ctrl_bijection.2628733730 |
| /workspace/coverage/default/13.sram_ctrl_executable.2243062157 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.581951354 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.550518993 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2785320595 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.3745028118 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.1247397893 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.572004597 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.1873630298 |
| /workspace/coverage/default/13.sram_ctrl_ram_cfg.1888202136 |
| /workspace/coverage/default/13.sram_ctrl_regwen.2480042084 |
| /workspace/coverage/default/13.sram_ctrl_smoke.31364330 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.156337072 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.3568083874 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3099283602 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.1673435533 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.309085451 |
| /workspace/coverage/default/14.sram_ctrl_bijection.4016051542 |
| /workspace/coverage/default/14.sram_ctrl_executable.1734900332 |
| /workspace/coverage/default/14.sram_ctrl_lc_escalation.902880661 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.2949538255 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.743123310 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.3281376751 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.3567056009 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.2983665675 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2492068562 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.744318870 |
| /workspace/coverage/default/14.sram_ctrl_regwen.1575044292 |
| /workspace/coverage/default/14.sram_ctrl_smoke.4013348978 |
| /workspace/coverage/default/14.sram_ctrl_stress_all.914856300 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2071990417 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.2360693084 |
| /workspace/coverage/default/15.sram_ctrl_access_during_key_req.237630479 |
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| /workspace/coverage/default/43.sram_ctrl_multiple_keys.269649630 |
| /workspace/coverage/default/43.sram_ctrl_partial_access.2311977478 |
| /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1589997886 |
| /workspace/coverage/default/43.sram_ctrl_ram_cfg.2965846924 |
| /workspace/coverage/default/43.sram_ctrl_regwen.1936353543 |
| /workspace/coverage/default/43.sram_ctrl_smoke.3809365361 |
| /workspace/coverage/default/43.sram_ctrl_stress_all.743728571 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.1721782249 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2668453427 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1006616439 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.936459176 |
| /workspace/coverage/default/44.sram_ctrl_bijection.3576644552 |
| /workspace/coverage/default/44.sram_ctrl_executable.923495054 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.3948755873 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.2900827683 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.2388362707 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.2947265531 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.2479652093 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.2447098028 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.4268607709 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.2211579864 |
| /workspace/coverage/default/44.sram_ctrl_regwen.2878560679 |
| /workspace/coverage/default/44.sram_ctrl_smoke.109352734 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.1870621797 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.372934739 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.1104691148 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.174971629 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.134200480 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.4173353024 |
| /workspace/coverage/default/45.sram_ctrl_bijection.2838938383 |
| /workspace/coverage/default/45.sram_ctrl_executable.1906622523 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.1030120149 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.3911345011 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.1051456111 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.3468279790 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.303567980 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.1918204492 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.958262805 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.207636694 |
| /workspace/coverage/default/45.sram_ctrl_regwen.4203943495 |
| /workspace/coverage/default/45.sram_ctrl_smoke.1567003885 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.4126857377 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.4067394208 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.621744546 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.508527464 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.3783055094 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.1998211376 |
| /workspace/coverage/default/46.sram_ctrl_bijection.1898340885 |
| /workspace/coverage/default/46.sram_ctrl_executable.4035660114 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.4082998696 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.2100805533 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3394824092 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.3059785461 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.2051887182 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.1566831823 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.1348241462 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.2764481768 |
| /workspace/coverage/default/46.sram_ctrl_regwen.3752862114 |
| /workspace/coverage/default/46.sram_ctrl_smoke.3547379723 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.3451468512 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.634749611 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.768133937 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1416765260 |
| /workspace/coverage/default/47.sram_ctrl_access_during_key_req.3104117356 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.635344209 |
| /workspace/coverage/default/47.sram_ctrl_bijection.423896365 |
| /workspace/coverage/default/47.sram_ctrl_executable.4164987045 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.3153229964 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.1514965967 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3491242384 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.2099264284 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.2746213968 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.3031386299 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3495615629 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.1198625717 |
| /workspace/coverage/default/47.sram_ctrl_regwen.617370231 |
| /workspace/coverage/default/47.sram_ctrl_smoke.4221035374 |
| /workspace/coverage/default/47.sram_ctrl_stress_all.4209469763 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1180279807 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1000853075 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.1653921102 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.4180294748 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.1722297331 |
| /workspace/coverage/default/48.sram_ctrl_bijection.3031933022 |
| /workspace/coverage/default/48.sram_ctrl_executable.932857181 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.1167334086 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.2380292228 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.4279250041 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.2108274444 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.2835338093 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.2280995906 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1769734334 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.885386105 |
| /workspace/coverage/default/48.sram_ctrl_regwen.954213143 |
| /workspace/coverage/default/48.sram_ctrl_smoke.3308895390 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.1583703935 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1503862364 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.858028786 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.2746183578 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.799739233 |
| /workspace/coverage/default/49.sram_ctrl_bijection.1243839560 |
| /workspace/coverage/default/49.sram_ctrl_executable.3540716178 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.2744739109 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.966851279 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.2335457212 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.2489950859 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.3964201266 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.4136491266 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.3010337419 |
| /workspace/coverage/default/49.sram_ctrl_regwen.4247254360 |
| /workspace/coverage/default/49.sram_ctrl_smoke.3253913056 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.3089913362 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3028746511 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.2215574079 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2533837833 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.21007977 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.212039944 |
| /workspace/coverage/default/5.sram_ctrl_bijection.2917953475 |
| /workspace/coverage/default/5.sram_ctrl_executable.2761998888 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.4118798478 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.2948111254 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.1889708793 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.296082289 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.2085289865 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.1906971567 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3778743951 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.3822486345 |
| /workspace/coverage/default/5.sram_ctrl_regwen.3448173647 |
| /workspace/coverage/default/5.sram_ctrl_smoke.2756699950 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.2401995937 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.1380112932 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.2268108453 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.1245188834 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.345748034 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.2680612515 |
| /workspace/coverage/default/6.sram_ctrl_bijection.1888909776 |
| /workspace/coverage/default/6.sram_ctrl_executable.3817889063 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.1715006179 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.2992498677 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2106797118 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.1898100225 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.3808096738 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.2860273051 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3343655542 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.3480668809 |
| /workspace/coverage/default/6.sram_ctrl_regwen.3799702416 |
| /workspace/coverage/default/6.sram_ctrl_smoke.1969645928 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.181385144 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.2686033124 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1872140250 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.513584073 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.218821000 |
| /workspace/coverage/default/7.sram_ctrl_bijection.917076639 |
| /workspace/coverage/default/7.sram_ctrl_executable.3356983424 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.2259257979 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.3801534018 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.2872150385 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.3345617829 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.2687420569 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.874151825 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2448741313 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.2402636659 |
| /workspace/coverage/default/7.sram_ctrl_regwen.1856303077 |
| /workspace/coverage/default/7.sram_ctrl_smoke.3075067899 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.482196021 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1366600309 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.4079105420 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.2251264117 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.1966049320 |
| /workspace/coverage/default/8.sram_ctrl_bijection.3019163517 |
| /workspace/coverage/default/8.sram_ctrl_executable.1424333348 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.601766059 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.2109559473 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.3696532717 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.1583956956 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.3994774231 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.1896459496 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.1774841298 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.1053840169 |
| /workspace/coverage/default/8.sram_ctrl_regwen.2165482672 |
| /workspace/coverage/default/8.sram_ctrl_smoke.1088226955 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.2999323153 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3112714989 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1826372346 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.136766882 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2550641239 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1618706221 |
| /workspace/coverage/default/9.sram_ctrl_bijection.3248069073 |
| /workspace/coverage/default/9.sram_ctrl_executable.622074572 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.3486033027 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.2747504118 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.888399112 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.1373860558 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.809546288 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.1098590028 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2600756721 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.1177085806 |
| /workspace/coverage/default/9.sram_ctrl_regwen.3708197605 |
| /workspace/coverage/default/9.sram_ctrl_smoke.2839784375 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.1444767139 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1428923355 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3941446788 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.80150856 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.3567056009 |
|
|
Apr 02 01:24:39 PM PDT 24 |
Apr 02 01:29:13 PM PDT 24 |
10423105226 ps |
| T2 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.3801522159 |
|
|
Apr 02 01:32:09 PM PDT 24 |
Apr 02 01:48:47 PM PDT 24 |
7259019230 ps |
| T3 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1826372346 |
|
|
Apr 02 01:23:00 PM PDT 24 |
Apr 02 01:24:49 PM PDT 24 |
2359190761 ps |
| T4 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.21007977 |
|
|
Apr 02 01:22:11 PM PDT 24 |
Apr 02 01:39:56 PM PDT 24 |
11488477007 ps |
| T8 |
/workspace/coverage/default/49.sram_ctrl_alert_test.799739233 |
|
|
Apr 02 01:34:18 PM PDT 24 |
Apr 02 01:34:18 PM PDT 24 |
124164864 ps |
| T9 |
/workspace/coverage/default/35.sram_ctrl_executable.1266885813 |
|
|
Apr 02 01:30:43 PM PDT 24 |
Apr 02 01:52:15 PM PDT 24 |
31246295162 ps |
| T10 |
/workspace/coverage/default/16.sram_ctrl_bijection.620600231 |
|
|
Apr 02 01:25:20 PM PDT 24 |
Apr 02 01:26:52 PM PDT 24 |
30015785644 ps |
| T11 |
/workspace/coverage/default/43.sram_ctrl_regwen.1936353543 |
|
|
Apr 02 01:32:54 PM PDT 24 |
Apr 02 01:39:16 PM PDT 24 |
15048099657 ps |
| T12 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1370387557 |
|
|
Apr 02 01:34:06 PM PDT 24 |
Apr 02 01:34:55 PM PDT 24 |
1010988175 ps |
| T13 |
/workspace/coverage/default/26.sram_ctrl_mem_partial_access.4130925045 |
|
|
Apr 02 01:28:25 PM PDT 24 |
Apr 02 01:28:28 PM PDT 24 |
82128718 ps |
| T14 |
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.4067394208 |
|
|
Apr 02 01:33:31 PM PDT 24 |
Apr 02 01:34:15 PM PDT 24 |
5364066311 ps |
| T16 |
/workspace/coverage/default/27.sram_ctrl_alert_test.3847196701 |
|
|
Apr 02 01:28:45 PM PDT 24 |
Apr 02 01:28:45 PM PDT 24 |
15904595 ps |
| T46 |
/workspace/coverage/default/8.sram_ctrl_bijection.3019163517 |
|
|
Apr 02 01:22:57 PM PDT 24 |
Apr 02 01:23:39 PM PDT 24 |
2885958627 ps |
| T5 |
/workspace/coverage/default/1.sram_ctrl_stress_all.2904245269 |
|
|
Apr 02 01:20:48 PM PDT 24 |
Apr 02 02:13:42 PM PDT 24 |
81603989462 ps |
| T23 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2335457212 |
|
|
Apr 02 01:34:14 PM PDT 24 |
Apr 02 01:34:17 PM PDT 24 |
89001651 ps |
| T47 |
/workspace/coverage/default/40.sram_ctrl_executable.4141884755 |
|
|
Apr 02 01:32:10 PM PDT 24 |
Apr 02 01:37:34 PM PDT 24 |
1335320193 ps |
| T6 |
/workspace/coverage/default/22.sram_ctrl_stress_all.1337925287 |
|
|
Apr 02 01:27:24 PM PDT 24 |
Apr 02 02:25:20 PM PDT 24 |
363024749015 ps |
| T48 |
/workspace/coverage/default/23.sram_ctrl_executable.2994222749 |
|
|
Apr 02 01:27:34 PM PDT 24 |
Apr 02 01:52:01 PM PDT 24 |
13814856163 ps |
| T127 |
/workspace/coverage/default/11.sram_ctrl_partial_access.2400718660 |
|
|
Apr 02 01:23:52 PM PDT 24 |
Apr 02 01:26:10 PM PDT 24 |
858723023 ps |
| T83 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.4254906538 |
|
|
Apr 02 01:30:09 PM PDT 24 |
Apr 02 01:32:04 PM PDT 24 |
4717035151 ps |
| T15 |
/workspace/coverage/default/31.sram_ctrl_access_during_key_req.3890409043 |
|
|
Apr 02 01:29:44 PM PDT 24 |
Apr 02 01:35:53 PM PDT 24 |
1437714876 ps |
| T91 |
/workspace/coverage/default/32.sram_ctrl_executable.1475307997 |
|
|
Apr 02 01:29:58 PM PDT 24 |
Apr 02 01:32:09 PM PDT 24 |
660673461 ps |
| T39 |
/workspace/coverage/default/31.sram_ctrl_stress_all.2295426995 |
|
|
Apr 02 01:29:52 PM PDT 24 |
Apr 02 02:19:43 PM PDT 24 |
287697119197 ps |
| T148 |
/workspace/coverage/default/7.sram_ctrl_smoke.3075067899 |
|
|
Apr 02 01:22:36 PM PDT 24 |
Apr 02 01:22:39 PM PDT 24 |
98948112 ps |
| T69 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.108155885 |
|
|
Apr 02 01:26:47 PM PDT 24 |
Apr 02 01:26:49 PM PDT 24 |
167999231 ps |
| T92 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.2100805533 |
|
|
Apr 02 01:33:32 PM PDT 24 |
Apr 02 01:33:52 PM PDT 24 |
76492566 ps |
| T7 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1030120149 |
|
|
Apr 02 01:33:23 PM PDT 24 |
Apr 02 01:33:28 PM PDT 24 |
2157486130 ps |
| T25 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.3714639124 |
|
|
Apr 02 01:31:32 PM PDT 24 |
Apr 02 01:31:33 PM PDT 24 |
64816151 ps |
| T126 |
/workspace/coverage/default/27.sram_ctrl_partial_access.4166158085 |
|
|
Apr 02 01:28:31 PM PDT 24 |
Apr 02 01:29:59 PM PDT 24 |
1240488031 ps |
| T125 |
/workspace/coverage/default/2.sram_ctrl_executable.2707412359 |
|
|
Apr 02 01:21:07 PM PDT 24 |
Apr 02 01:58:36 PM PDT 24 |
22890335085 ps |
| T149 |
/workspace/coverage/default/23.sram_ctrl_bijection.1902414009 |
|
|
Apr 02 01:27:29 PM PDT 24 |
Apr 02 01:27:53 PM PDT 24 |
1545620353 ps |
| T132 |
/workspace/coverage/default/45.sram_ctrl_bijection.2838938383 |
|
|
Apr 02 01:33:17 PM PDT 24 |
Apr 02 01:34:23 PM PDT 24 |
4021407700 ps |
| T17 |
/workspace/coverage/default/42.sram_ctrl_alert_test.4281417021 |
|
|
Apr 02 01:32:49 PM PDT 24 |
Apr 02 01:32:50 PM PDT 24 |
18728085 ps |
| T26 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1053840169 |
|
|
Apr 02 01:23:10 PM PDT 24 |
Apr 02 01:23:11 PM PDT 24 |
136107364 ps |
| T49 |
/workspace/coverage/default/31.sram_ctrl_lc_escalation.721893089 |
|
|
Apr 02 01:29:39 PM PDT 24 |
Apr 02 01:29:47 PM PDT 24 |
2757230327 ps |
| T150 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.3089858501 |
|
|
Apr 02 01:26:56 PM PDT 24 |
Apr 02 01:27:01 PM PDT 24 |
74799298 ps |
| T84 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2215574079 |
|
|
Apr 02 01:34:06 PM PDT 24 |
Apr 02 01:37:04 PM PDT 24 |
7614437287 ps |
| T70 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.898002724 |
|
|
Apr 02 01:32:11 PM PDT 24 |
Apr 02 01:32:15 PM PDT 24 |
246722973 ps |
| T147 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.864322737 |
|
|
Apr 02 01:25:23 PM PDT 24 |
Apr 02 01:26:19 PM PDT 24 |
120448747 ps |
| T27 |
/workspace/coverage/default/1.sram_ctrl_ram_cfg.1674503477 |
|
|
Apr 02 01:20:37 PM PDT 24 |
Apr 02 01:20:38 PM PDT 24 |
31469312 ps |
| T151 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2085289865 |
|
|
Apr 02 01:22:03 PM PDT 24 |
Apr 02 01:28:15 PM PDT 24 |
2815811051 ps |
| T85 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.608054632 |
|
|
Apr 02 01:23:33 PM PDT 24 |
Apr 02 01:28:19 PM PDT 24 |
2950011150 ps |
| T128 |
/workspace/coverage/default/31.sram_ctrl_executable.922946393 |
|
|
Apr 02 01:29:44 PM PDT 24 |
Apr 02 01:39:47 PM PDT 24 |
1369886966 ps |
| T141 |
/workspace/coverage/default/49.sram_ctrl_bijection.1243839560 |
|
|
Apr 02 01:34:07 PM PDT 24 |
Apr 02 01:34:46 PM PDT 24 |
1826740653 ps |
| T129 |
/workspace/coverage/default/36.sram_ctrl_executable.2541644999 |
|
|
Apr 02 01:30:52 PM PDT 24 |
Apr 02 01:47:11 PM PDT 24 |
15449907716 ps |
| T86 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3992053000 |
|
|
Apr 02 01:30:51 PM PDT 24 |
Apr 02 01:37:34 PM PDT 24 |
16159938175 ps |
| T152 |
/workspace/coverage/default/28.sram_ctrl_partial_access.1918901515 |
|
|
Apr 02 01:28:53 PM PDT 24 |
Apr 02 01:29:07 PM PDT 24 |
1157526584 ps |
| T144 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.495137540 |
|
|
Apr 02 01:23:56 PM PDT 24 |
Apr 02 01:25:44 PM PDT 24 |
130556998 ps |
| T142 |
/workspace/coverage/default/33.sram_ctrl_executable.189907580 |
|
|
Apr 02 01:30:16 PM PDT 24 |
Apr 02 01:34:04 PM PDT 24 |
1173706813 ps |
| T71 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.995260999 |
|
|
Apr 02 01:30:54 PM PDT 24 |
Apr 02 01:33:00 PM PDT 24 |
205373069 ps |
| T153 |
/workspace/coverage/default/49.sram_ctrl_smoke.3253913056 |
|
|
Apr 02 01:34:06 PM PDT 24 |
Apr 02 01:34:18 PM PDT 24 |
780006161 ps |
| T154 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.964319563 |
|
|
Apr 02 01:31:27 PM PDT 24 |
Apr 02 01:32:59 PM PDT 24 |
1067173556 ps |
| T50 |
/workspace/coverage/default/5.sram_ctrl_regwen.3448173647 |
|
|
Apr 02 01:22:11 PM PDT 24 |
Apr 02 01:32:47 PM PDT 24 |
10489324120 ps |
| T155 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.2761827346 |
|
|
Apr 02 01:27:07 PM PDT 24 |
Apr 02 01:27:49 PM PDT 24 |
379945225 ps |
| T72 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.1046013672 |
|
|
Apr 02 01:29:14 PM PDT 24 |
Apr 02 01:42:33 PM PDT 24 |
2977400318 ps |
| T140 |
/workspace/coverage/default/11.sram_ctrl_bijection.3346293282 |
|
|
Apr 02 01:23:48 PM PDT 24 |
Apr 02 01:24:39 PM PDT 24 |
11295914066 ps |
| T136 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.4107461531 |
|
|
Apr 02 01:26:50 PM PDT 24 |
Apr 02 01:43:02 PM PDT 24 |
2508760896 ps |
| T73 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.2100135304 |
|
|
Apr 02 01:29:16 PM PDT 24 |
Apr 02 01:29:21 PM PDT 24 |
356979623 ps |
| T51 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.801084595 |
|
|
Apr 02 01:25:45 PM PDT 24 |
Apr 02 01:25:49 PM PDT 24 |
538089563 ps |
| T52 |
/workspace/coverage/default/0.sram_ctrl_stress_all.2087372578 |
|
|
Apr 02 01:20:16 PM PDT 24 |
Apr 02 01:23:02 PM PDT 24 |
3444705906 ps |
| T156 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.475216697 |
|
|
Apr 02 01:28:18 PM PDT 24 |
Apr 02 01:29:08 PM PDT 24 |
1522590110 ps |
| T53 |
/workspace/coverage/default/8.sram_ctrl_stress_all.2999323153 |
|
|
Apr 02 01:23:11 PM PDT 24 |
Apr 02 02:16:50 PM PDT 24 |
174667311799 ps |
| T157 |
/workspace/coverage/default/36.sram_ctrl_bijection.2128710795 |
|
|
Apr 02 01:30:47 PM PDT 24 |
Apr 02 01:31:30 PM PDT 24 |
3085417641 ps |
| T158 |
/workspace/coverage/default/42.sram_ctrl_access_during_key_req.4097929668 |
|
|
Apr 02 01:32:38 PM PDT 24 |
Apr 02 01:46:40 PM PDT 24 |
10955044473 ps |
| T87 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.1257203166 |
|
|
Apr 02 01:31:20 PM PDT 24 |
Apr 02 01:34:10 PM PDT 24 |
14956821114 ps |
| T88 |
/workspace/coverage/default/13.sram_ctrl_mem_partial_access.2785320595 |
|
|
Apr 02 01:24:36 PM PDT 24 |
Apr 02 01:24:40 PM PDT 24 |
234900728 ps |
| T159 |
/workspace/coverage/default/48.sram_ctrl_partial_access.2280995906 |
|
|
Apr 02 01:33:57 PM PDT 24 |
Apr 02 01:36:00 PM PDT 24 |
4669974896 ps |
| T160 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.372218282 |
|
|
Apr 02 01:30:07 PM PDT 24 |
Apr 02 01:34:19 PM PDT 24 |
12278857015 ps |
| T135 |
/workspace/coverage/default/44.sram_ctrl_bijection.3576644552 |
|
|
Apr 02 01:33:04 PM PDT 24 |
Apr 02 01:33:45 PM PDT 24 |
3402004802 ps |
| T161 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.2251509410 |
|
|
Apr 02 01:25:29 PM PDT 24 |
Apr 02 01:25:34 PM PDT 24 |
79222733 ps |
| T162 |
/workspace/coverage/default/44.sram_ctrl_partial_access.2447098028 |
|
|
Apr 02 01:33:04 PM PDT 24 |
Apr 02 01:33:58 PM PDT 24 |
4058180834 ps |
| T133 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.1721782249 |
|
|
Apr 02 01:32:55 PM PDT 24 |
Apr 02 01:38:00 PM PDT 24 |
27233529592 ps |
| T163 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.1515341962 |
|
|
Apr 02 01:31:24 PM PDT 24 |
Apr 02 01:33:11 PM PDT 24 |
176771831 ps |
| T18 |
/workspace/coverage/default/40.sram_ctrl_alert_test.761441703 |
|
|
Apr 02 01:32:10 PM PDT 24 |
Apr 02 01:32:11 PM PDT 24 |
25775059 ps |
| T131 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2482972894 |
|
|
Apr 02 01:30:10 PM PDT 24 |
Apr 02 01:30:14 PM PDT 24 |
101931282 ps |
| T164 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.450906555 |
|
|
Apr 02 01:26:05 PM PDT 24 |
Apr 02 01:26:11 PM PDT 24 |
1646225709 ps |
| T165 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.2289396333 |
|
|
Apr 02 01:25:34 PM PDT 24 |
Apr 02 01:25:40 PM PDT 24 |
292238082 ps |
| T137 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.1210243462 |
|
|
Apr 02 01:29:40 PM PDT 24 |
Apr 02 01:47:40 PM PDT 24 |
24241530529 ps |
| T145 |
/workspace/coverage/default/7.sram_ctrl_executable.3356983424 |
|
|
Apr 02 01:22:49 PM PDT 24 |
Apr 02 01:30:16 PM PDT 24 |
29086806742 ps |
| T166 |
/workspace/coverage/default/7.sram_ctrl_bijection.917076639 |
|
|
Apr 02 01:22:39 PM PDT 24 |
Apr 02 01:23:06 PM PDT 24 |
5071287593 ps |
| T167 |
/workspace/coverage/default/3.sram_ctrl_bijection.318244377 |
|
|
Apr 02 01:21:17 PM PDT 24 |
Apr 02 01:22:21 PM PDT 24 |
21579143180 ps |
| T139 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.996496312 |
|
|
Apr 02 01:30:28 PM PDT 24 |
Apr 02 01:30:29 PM PDT 24 |
27730457 ps |
| T24 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.634749611 |
|
|
Apr 02 01:33:38 PM PDT 24 |
Apr 02 01:33:55 PM PDT 24 |
5053621380 ps |
| T103 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2479652093 |
|
|
Apr 02 01:33:00 PM PDT 24 |
Apr 02 01:36:48 PM PDT 24 |
574963480 ps |
| T104 |
/workspace/coverage/default/42.sram_ctrl_regwen.3356478770 |
|
|
Apr 02 01:32:46 PM PDT 24 |
Apr 02 01:33:20 PM PDT 24 |
4014489118 ps |
| T105 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.3622354127 |
|
|
Apr 02 01:29:30 PM PDT 24 |
Apr 02 01:37:12 PM PDT 24 |
21139571375 ps |
| T106 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.3734163650 |
|
|
Apr 02 01:32:07 PM PDT 24 |
Apr 02 01:32:14 PM PDT 24 |
4211122878 ps |
| T107 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.1423288084 |
|
|
Apr 02 01:28:14 PM PDT 24 |
Apr 02 01:33:45 PM PDT 24 |
13014260861 ps |
| T108 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2746183578 |
|
|
Apr 02 01:34:11 PM PDT 24 |
Apr 02 01:47:29 PM PDT 24 |
4260968396 ps |
| T109 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3822486345 |
|
|
Apr 02 01:22:12 PM PDT 24 |
Apr 02 01:22:13 PM PDT 24 |
61394359 ps |
| T110 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2106797118 |
|
|
Apr 02 01:22:37 PM PDT 24 |
Apr 02 01:22:42 PM PDT 24 |
61907006 ps |
| T111 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.687441212 |
|
|
Apr 02 01:30:03 PM PDT 24 |
Apr 02 01:30:08 PM PDT 24 |
150434831 ps |
| T143 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.2792161530 |
|
|
Apr 02 01:21:33 PM PDT 24 |
Apr 02 01:21:38 PM PDT 24 |
153408489 ps |
| T168 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.2641885882 |
|
|
Apr 02 01:29:00 PM PDT 24 |
Apr 02 01:29:01 PM PDT 24 |
35846459 ps |
| T169 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.4082601031 |
|
|
Apr 02 01:26:16 PM PDT 24 |
Apr 02 01:30:58 PM PDT 24 |
6470738095 ps |
| T170 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3938969426 |
|
|
Apr 02 01:24:13 PM PDT 24 |
Apr 02 01:24:14 PM PDT 24 |
141783488 ps |
| T171 |
/workspace/coverage/default/34.sram_ctrl_partial_access.4116931803 |
|
|
Apr 02 01:30:20 PM PDT 24 |
Apr 02 01:30:38 PM PDT 24 |
6643139674 ps |
| T172 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.1898100225 |
|
|
Apr 02 01:22:32 PM PDT 24 |
Apr 02 01:22:37 PM PDT 24 |
269220118 ps |
| T173 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.601766059 |
|
|
Apr 02 01:23:04 PM PDT 24 |
Apr 02 01:23:08 PM PDT 24 |
345076324 ps |
| T174 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.508527464 |
|
|
Apr 02 01:33:21 PM PDT 24 |
Apr 02 01:34:10 PM PDT 24 |
450935331 ps |
| T175 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.966851279 |
|
|
Apr 02 01:34:12 PM PDT 24 |
Apr 02 01:36:12 PM PDT 24 |
134049329 ps |
| T176 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2668453427 |
|
|
Apr 02 01:32:49 PM PDT 24 |
Apr 02 01:32:51 PM PDT 24 |
239745096 ps |
| T177 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.2900827683 |
|
|
Apr 02 01:33:03 PM PDT 24 |
Apr 02 01:33:53 PM PDT 24 |
339519721 ps |
| T22 |
/workspace/coverage/default/12.sram_ctrl_regwen.806686377 |
|
|
Apr 02 01:24:13 PM PDT 24 |
Apr 02 01:37:32 PM PDT 24 |
6234379492 ps |
| T178 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.679443306 |
|
|
Apr 02 01:29:08 PM PDT 24 |
Apr 02 01:30:31 PM PDT 24 |
432342605 ps |
| T179 |
/workspace/coverage/default/11.sram_ctrl_alert_test.1891472504 |
|
|
Apr 02 01:24:02 PM PDT 24 |
Apr 02 01:24:02 PM PDT 24 |
20769904 ps |
| T180 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.86209681 |
|
|
Apr 02 01:27:35 PM PDT 24 |
Apr 02 01:27:45 PM PDT 24 |
687925896 ps |
| T181 |
/workspace/coverage/default/26.sram_ctrl_partial_access.1838524252 |
|
|
Apr 02 01:28:16 PM PDT 24 |
Apr 02 01:28:32 PM PDT 24 |
412602816 ps |
| T182 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.2548027820 |
|
|
Apr 02 01:24:01 PM PDT 24 |
Apr 02 01:24:13 PM PDT 24 |
4063216949 ps |
| T146 |
/workspace/coverage/default/10.sram_ctrl_regwen.1289765358 |
|
|
Apr 02 01:23:41 PM PDT 24 |
Apr 02 01:47:40 PM PDT 24 |
88008269041 ps |
| T183 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1582965212 |
|
|
Apr 02 01:29:51 PM PDT 24 |
Apr 02 01:29:54 PM PDT 24 |
43063477 ps |
| T184 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.1812867177 |
|
|
Apr 02 01:28:39 PM PDT 24 |
Apr 02 01:28:40 PM PDT 24 |
27088626 ps |
| T185 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.251065701 |
|
|
Apr 02 01:26:28 PM PDT 24 |
Apr 02 01:26:32 PM PDT 24 |
139115880 ps |
| T186 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.1102684361 |
|
|
Apr 02 01:30:36 PM PDT 24 |
Apr 02 01:37:58 PM PDT 24 |
11038292239 ps |
| T187 |
/workspace/coverage/default/8.sram_ctrl_smoke.1088226955 |
|
|
Apr 02 01:22:56 PM PDT 24 |
Apr 02 01:23:06 PM PDT 24 |
211206239 ps |
| T188 |
/workspace/coverage/default/36.sram_ctrl_smoke.3941043473 |
|
|
Apr 02 01:30:46 PM PDT 24 |
Apr 02 01:31:07 PM PDT 24 |
1284855078 ps |
| T189 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.958262805 |
|
|
Apr 02 01:33:21 PM PDT 24 |
Apr 02 01:40:17 PM PDT 24 |
126118216533 ps |
| T190 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3497374756 |
|
|
Apr 02 01:29:40 PM PDT 24 |
Apr 02 01:30:20 PM PDT 24 |
203552675 ps |
| T191 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2687420569 |
|
|
Apr 02 01:22:35 PM PDT 24 |
Apr 02 01:36:51 PM PDT 24 |
5788903454 ps |
| T192 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.628093213 |
|
|
Apr 02 01:27:44 PM PDT 24 |
Apr 02 01:29:49 PM PDT 24 |
262524892 ps |
| T124 |
/workspace/coverage/default/48.sram_ctrl_regwen.954213143 |
|
|
Apr 02 01:34:04 PM PDT 24 |
Apr 02 01:38:55 PM PDT 24 |
8443988035 ps |
| T134 |
/workspace/coverage/default/6.sram_ctrl_executable.3817889063 |
|
|
Apr 02 01:22:28 PM PDT 24 |
Apr 02 01:26:24 PM PDT 24 |
16302602749 ps |
| T138 |
/workspace/coverage/default/14.sram_ctrl_bijection.4016051542 |
|
|
Apr 02 01:24:38 PM PDT 24 |
Apr 02 01:25:53 PM PDT 24 |
18172046612 ps |
| T193 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3480668809 |
|
|
Apr 02 01:22:28 PM PDT 24 |
Apr 02 01:22:29 PM PDT 24 |
84187418 ps |
| T130 |
/workspace/coverage/default/4.sram_ctrl_stress_all.720084177 |
|
|
Apr 02 01:22:01 PM PDT 24 |
Apr 02 02:28:59 PM PDT 24 |
195633206297 ps |
| T194 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3826764271 |
|
|
Apr 02 01:19:57 PM PDT 24 |
Apr 02 01:23:55 PM PDT 24 |
2564899741 ps |
| T195 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.3706133142 |
|
|
Apr 02 01:20:58 PM PDT 24 |
Apr 02 01:22:35 PM PDT 24 |
131247520 ps |
| T40 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.1635459918 |
|
|
Apr 02 01:29:00 PM PDT 24 |
Apr 02 01:32:43 PM PDT 24 |
1659568217 ps |
| T196 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.3549139433 |
|
|
Apr 02 01:30:14 PM PDT 24 |
Apr 02 01:30:15 PM PDT 24 |
144901949 ps |
| T197 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1051456111 |
|
|
Apr 02 01:33:27 PM PDT 24 |
Apr 02 01:33:31 PM PDT 24 |
822697420 ps |
| T198 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2448741313 |
|
|
Apr 02 01:22:40 PM PDT 24 |
Apr 02 01:25:50 PM PDT 24 |
2626280694 ps |
| T199 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.3724362646 |
|
|
Apr 02 01:27:32 PM PDT 24 |
Apr 02 01:33:52 PM PDT 24 |
15577576477 ps |
| T200 |
/workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.3883845142 |
|
|
Apr 02 01:29:10 PM PDT 24 |
Apr 02 01:29:49 PM PDT 24 |
139798356 ps |
| T201 |
/workspace/coverage/default/16.sram_ctrl_regwen.1928178926 |
|
|
Apr 02 01:25:31 PM PDT 24 |
Apr 02 01:39:16 PM PDT 24 |
1660890878 ps |
| T41 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.255422397 |
|
|
Apr 02 01:26:57 PM PDT 24 |
Apr 02 01:27:12 PM PDT 24 |
1836153045 ps |
| T202 |
/workspace/coverage/default/14.sram_ctrl_executable.1734900332 |
|
|
Apr 02 01:24:48 PM PDT 24 |
Apr 02 01:30:01 PM PDT 24 |
5464690550 ps |
| T203 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.1362558354 |
|
|
Apr 02 01:32:45 PM PDT 24 |
Apr 02 01:32:51 PM PDT 24 |
627235155 ps |
| T204 |
/workspace/coverage/default/5.sram_ctrl_smoke.2756699950 |
|
|
Apr 02 01:22:02 PM PDT 24 |
Apr 02 01:22:10 PM PDT 24 |
272992240 ps |
| T205 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.743404399 |
|
|
Apr 02 01:27:50 PM PDT 24 |
Apr 02 01:27:55 PM PDT 24 |
420129405 ps |
| T206 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.1368526526 |
|
|
Apr 02 01:27:24 PM PDT 24 |
Apr 02 01:27:28 PM PDT 24 |
565431647 ps |
| T207 |
/workspace/coverage/default/2.sram_ctrl_regwen.1445835389 |
|
|
Apr 02 01:21:10 PM PDT 24 |
Apr 02 01:40:05 PM PDT 24 |
68928521219 ps |
| T208 |
/workspace/coverage/default/31.sram_ctrl_regwen.978424476 |
|
|
Apr 02 01:29:43 PM PDT 24 |
Apr 02 01:47:07 PM PDT 24 |
59321266138 ps |
| T209 |
/workspace/coverage/default/30.sram_ctrl_bijection.1968207177 |
|
|
Apr 02 01:29:28 PM PDT 24 |
Apr 02 01:29:52 PM PDT 24 |
418047066 ps |
| T210 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2747504118 |
|
|
Apr 02 01:23:17 PM PDT 24 |
Apr 02 01:24:13 PM PDT 24 |
258345523 ps |
| T211 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.3666164077 |
|
|
Apr 02 01:26:52 PM PDT 24 |
Apr 02 01:29:29 PM PDT 24 |
1608751648 ps |
| T212 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.3281376751 |
|
|
Apr 02 01:24:54 PM PDT 24 |
Apr 02 01:25:04 PM PDT 24 |
659391664 ps |
| T213 |
/workspace/coverage/default/27.sram_ctrl_smoke.990515759 |
|
|
Apr 02 01:28:29 PM PDT 24 |
Apr 02 01:29:45 PM PDT 24 |
217722096 ps |
| T214 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.1718077156 |
|
|
Apr 02 01:30:11 PM PDT 24 |
Apr 02 01:31:13 PM PDT 24 |
112821483 ps |
| T215 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.3499887132 |
|
|
Apr 02 01:25:11 PM PDT 24 |
Apr 02 01:25:12 PM PDT 24 |
29998502 ps |
| T216 |
/workspace/coverage/default/20.sram_ctrl_smoke.1614065480 |
|
|
Apr 02 01:26:30 PM PDT 24 |
Apr 02 01:28:48 PM PDT 24 |
1425156067 ps |
| T217 |
/workspace/coverage/default/31.sram_ctrl_alert_test.1925013679 |
|
|
Apr 02 01:29:53 PM PDT 24 |
Apr 02 01:29:54 PM PDT 24 |
12617440 ps |
| T218 |
/workspace/coverage/default/18.sram_ctrl_alert_test.3796462051 |
|
|
Apr 02 01:26:13 PM PDT 24 |
Apr 02 01:26:14 PM PDT 24 |
13863577 ps |
| T219 |
/workspace/coverage/default/13.sram_ctrl_smoke.31364330 |
|
|
Apr 02 01:24:19 PM PDT 24 |
Apr 02 01:24:27 PM PDT 24 |
419724792 ps |
| T220 |
/workspace/coverage/default/4.sram_ctrl_regwen.234571906 |
|
|
Apr 02 01:21:56 PM PDT 24 |
Apr 02 01:28:57 PM PDT 24 |
17572685524 ps |
| T221 |
/workspace/coverage/default/19.sram_ctrl_partial_access.2116615053 |
|
|
Apr 02 01:26:19 PM PDT 24 |
Apr 02 01:26:25 PM PDT 24 |
133033244 ps |
| T222 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.441663702 |
|
|
Apr 02 01:32:20 PM PDT 24 |
Apr 02 01:40:09 PM PDT 24 |
11808860647 ps |
| T223 |
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3778743951 |
|
|
Apr 02 01:22:16 PM PDT 24 |
Apr 02 01:29:05 PM PDT 24 |
10896340807 ps |
| T224 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.3093633608 |
|
|
Apr 02 01:28:33 PM PDT 24 |
Apr 02 01:29:40 PM PDT 24 |
394016864 ps |
| T225 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.2385412218 |
|
|
Apr 02 01:23:38 PM PDT 24 |
Apr 02 01:26:06 PM PDT 24 |
1411610008 ps |
| T226 |
/workspace/coverage/default/29.sram_ctrl_smoke.2990326339 |
|
|
Apr 02 01:29:04 PM PDT 24 |
Apr 02 01:29:20 PM PDT 24 |
7660904240 ps |
| T19 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.2381403286 |
|
|
Apr 02 01:21:11 PM PDT 24 |
Apr 02 01:21:13 PM PDT 24 |
114624928 ps |
| T30 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.3414316025 |
|
|
Apr 02 01:19:59 PM PDT 24 |
Apr 02 01:20:04 PM PDT 24 |
215193945 ps |
| T31 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2112659849 |
|
|
Apr 02 01:20:05 PM PDT 24 |
Apr 02 01:20:14 PM PDT 24 |
3305031318 ps |
| T32 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.761004499 |
|
|
Apr 02 01:29:55 PM PDT 24 |
Apr 02 01:31:04 PM PDT 24 |
248221022 ps |
| T33 |
/workspace/coverage/default/3.sram_ctrl_smoke.3807487794 |
|
|
Apr 02 01:21:12 PM PDT 24 |
Apr 02 01:23:21 PM PDT 24 |
1341399914 ps |
| T34 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.799195656 |
|
|
Apr 02 01:24:53 PM PDT 24 |
Apr 02 01:25:02 PM PDT 24 |
280461804 ps |
| T35 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.1468169726 |
|
|
Apr 02 01:31:37 PM PDT 24 |
Apr 02 01:54:11 PM PDT 24 |
12482993164 ps |
| T36 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2492068562 |
|
|
Apr 02 01:24:42 PM PDT 24 |
Apr 02 01:35:01 PM PDT 24 |
83974541715 ps |
| T37 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.121420835 |
|
|
Apr 02 01:26:53 PM PDT 24 |
Apr 02 01:26:56 PM PDT 24 |
1102347234 ps |
| T38 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.269649630 |
|
|
Apr 02 01:32:50 PM PDT 24 |
Apr 02 01:47:45 PM PDT 24 |
11473723017 ps |
| T227 |
/workspace/coverage/default/45.sram_ctrl_executable.1906622523 |
|
|
Apr 02 01:33:24 PM PDT 24 |
Apr 02 01:40:40 PM PDT 24 |
39084766312 ps |
| T42 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1428923355 |
|
|
Apr 02 01:23:24 PM PDT 24 |
Apr 02 01:33:57 PM PDT 24 |
2307694473 ps |
| T228 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1889708793 |
|
|
Apr 02 01:22:19 PM PDT 24 |
Apr 02 01:22:24 PM PDT 24 |
694079614 ps |
| T229 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2529434150 |
|
|
Apr 02 01:23:33 PM PDT 24 |
Apr 02 01:27:32 PM PDT 24 |
10753898409 ps |
| T230 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1167577307 |
|
|
Apr 02 01:32:57 PM PDT 24 |
Apr 02 01:33:03 PM PDT 24 |
881092013 ps |
| T231 |
/workspace/coverage/default/40.sram_ctrl_partial_access.1687283856 |
|
|
Apr 02 01:32:01 PM PDT 24 |
Apr 02 01:32:18 PM PDT 24 |
996756284 ps |
| T232 |
/workspace/coverage/default/14.sram_ctrl_alert_test.309085451 |
|
|
Apr 02 01:25:00 PM PDT 24 |
Apr 02 01:25:00 PM PDT 24 |
47042107 ps |
| T233 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.1155074233 |
|
|
Apr 02 01:32:55 PM PDT 24 |
Apr 02 01:33:02 PM PDT 24 |
588824081 ps |
| T234 |
/workspace/coverage/default/23.sram_ctrl_regwen.429775885 |
|
|
Apr 02 01:27:33 PM PDT 24 |
Apr 02 01:31:00 PM PDT 24 |
1453903983 ps |
| T235 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.1448789891 |
|
|
Apr 02 01:27:31 PM PDT 24 |
Apr 02 01:32:18 PM PDT 24 |
22452036382 ps |
| T236 |
/workspace/coverage/default/36.sram_ctrl_partial_access.2988349114 |
|
|
Apr 02 01:30:49 PM PDT 24 |
Apr 02 01:31:44 PM PDT 24 |
447857797 ps |
| T237 |
/workspace/coverage/default/25.sram_ctrl_alert_test.466589605 |
|
|
Apr 02 01:28:12 PM PDT 24 |
Apr 02 01:28:13 PM PDT 24 |
66461052 ps |
| T238 |
/workspace/coverage/default/17.sram_ctrl_mem_partial_access.3994366038 |
|
|
Apr 02 01:25:52 PM PDT 24 |
Apr 02 01:25:57 PM PDT 24 |
1592312033 ps |
| T43 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3028746511 |
|
|
Apr 02 01:34:14 PM PDT 24 |
Apr 02 01:34:43 PM PDT 24 |
2432771003 ps |
| T239 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1292282513 |
|
|
Apr 02 01:32:37 PM PDT 24 |
Apr 02 01:32:43 PM PDT 24 |
887913470 ps |
| T240 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.2444610725 |
|
|
Apr 02 01:32:31 PM PDT 24 |
Apr 02 01:32:40 PM PDT 24 |
268135634 ps |
| T241 |
/workspace/coverage/default/47.sram_ctrl_bijection.423896365 |
|
|
Apr 02 01:33:42 PM PDT 24 |
Apr 02 01:34:53 PM PDT 24 |
19088937740 ps |
| T242 |
/workspace/coverage/default/44.sram_ctrl_regwen.2878560679 |
|
|
Apr 02 01:33:09 PM PDT 24 |
Apr 02 01:41:03 PM PDT 24 |
3657660357 ps |
| T243 |
/workspace/coverage/default/22.sram_ctrl_bijection.3902298504 |
|
|
Apr 02 01:27:05 PM PDT 24 |
Apr 02 01:27:22 PM PDT 24 |
1128456076 ps |
| T244 |
/workspace/coverage/default/39.sram_ctrl_stress_all.722652818 |
|
|
Apr 02 01:31:56 PM PDT 24 |
Apr 02 02:09:32 PM PDT 24 |
45563059961 ps |
| T245 |
/workspace/coverage/default/10.sram_ctrl_partial_access.2331843841 |
|
|
Apr 02 01:23:31 PM PDT 24 |
Apr 02 01:23:36 PM PDT 24 |
432379309 ps |
| T246 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.1606215962 |
|
|
Apr 02 01:26:58 PM PDT 24 |
Apr 02 01:26:59 PM PDT 24 |
82694002 ps |
| T247 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2838489469 |
|
|
Apr 02 01:28:43 PM PDT 24 |
Apr 02 01:28:46 PM PDT 24 |
149850793 ps |
| T248 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.3041885538 |
|
|
Apr 02 01:27:51 PM PDT 24 |
Apr 02 01:28:01 PM PDT 24 |
664592900 ps |
| T249 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.2947265531 |
|
|
Apr 02 01:33:12 PM PDT 24 |
Apr 02 01:33:16 PM PDT 24 |
74203661 ps |
| T250 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.2546391242 |
|
|
Apr 02 01:31:56 PM PDT 24 |
Apr 02 01:31:57 PM PDT 24 |
31130974 ps |
| T251 |
/workspace/coverage/default/27.sram_ctrl_stress_all.1825479432 |
|
|
Apr 02 01:28:43 PM PDT 24 |
Apr 02 02:01:33 PM PDT 24 |
19874275890 ps |
| T252 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1769734334 |
|
|
Apr 02 01:33:56 PM PDT 24 |
Apr 02 01:41:25 PM PDT 24 |
29070811845 ps |
| T253 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3577700876 |
|
|
Apr 02 01:31:42 PM PDT 24 |
Apr 02 01:32:01 PM PDT 24 |
295867275 ps |
| T254 |
/workspace/coverage/default/10.sram_ctrl_stress_all.3714525205 |
|
|
Apr 02 01:23:44 PM PDT 24 |
Apr 02 02:50:42 PM PDT 24 |
18401957444 ps |
| T255 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.2109559473 |
|
|
Apr 02 01:23:05 PM PDT 24 |
Apr 02 01:23:26 PM PDT 24 |
86363628 ps |
| T256 |
/workspace/coverage/default/15.sram_ctrl_executable.3819899928 |
|
|
Apr 02 01:25:13 PM PDT 24 |
Apr 02 01:45:08 PM PDT 24 |
43915135068 ps |
| T257 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.2572530174 |
|
|
Apr 02 01:31:58 PM PDT 24 |
Apr 02 01:32:01 PM PDT 24 |
64236682 ps |
| T258 |
/workspace/coverage/default/20.sram_ctrl_ram_cfg.3499710638 |
|
|
Apr 02 01:26:46 PM PDT 24 |
Apr 02 01:26:47 PM PDT 24 |
29709345 ps |
| T259 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.324438056 |
|
|
Apr 02 01:28:56 PM PDT 24 |
Apr 02 01:44:56 PM PDT 24 |
27682046827 ps |
| T260 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3159757462 |
|
|
Apr 02 01:23:37 PM PDT 24 |
Apr 02 01:23:47 PM PDT 24 |
69763355 ps |
| T261 |
/workspace/coverage/default/22.sram_ctrl_regwen.3401599279 |
|
|
Apr 02 01:27:19 PM PDT 24 |
Apr 02 01:47:57 PM PDT 24 |
87102379466 ps |
| T262 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.2226220635 |
|
|
Apr 02 01:21:05 PM PDT 24 |
Apr 02 01:32:41 PM PDT 24 |
3682784377 ps |
| T263 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1126492437 |
|
|
Apr 02 01:30:49 PM PDT 24 |
Apr 02 01:33:16 PM PDT 24 |
306705384 ps |
| T264 |
/workspace/coverage/default/29.sram_ctrl_partial_access.1470845392 |
|
|
Apr 02 01:29:06 PM PDT 24 |
Apr 02 01:29:19 PM PDT 24 |
102906214 ps |
| T265 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.743123310 |
|
|
Apr 02 01:24:53 PM PDT 24 |
Apr 02 01:24:56 PM PDT 24 |
94910939 ps |
| T266 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.114733301 |
|
|
Apr 02 01:26:50 PM PDT 24 |
Apr 02 01:31:00 PM PDT 24 |
9124089472 ps |
| T267 |
/workspace/coverage/default/18.sram_ctrl_regwen.460346747 |
|
|
Apr 02 01:26:06 PM PDT 24 |
Apr 02 01:30:49 PM PDT 24 |
5999861319 ps |
| T268 |
/workspace/coverage/default/18.sram_ctrl_executable.362599689 |
|
|
Apr 02 01:26:11 PM PDT 24 |
Apr 02 01:44:15 PM PDT 24 |
22835345652 ps |
| T269 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.3751616665 |
|
|
Apr 02 01:21:49 PM PDT 24 |
Apr 02 01:22:29 PM PDT 24 |
404189947 ps |
| T270 |
/workspace/coverage/default/14.sram_ctrl_partial_access.2983665675 |
|
|
Apr 02 01:24:42 PM PDT 24 |
Apr 02 01:24:49 PM PDT 24 |
476846296 ps |
| T271 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.2519015071 |
|
|
Apr 02 01:30:14 PM PDT 24 |
Apr 02 01:46:14 PM PDT 24 |
3911838538 ps |
| T272 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.631476957 |
|
|
Apr 02 01:27:58 PM PDT 24 |
Apr 02 01:43:53 PM PDT 24 |
46452975357 ps |
| T273 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.202788884 |
|
|
Apr 02 01:27:08 PM PDT 24 |
Apr 02 01:28:12 PM PDT 24 |
214515205 ps |
| T274 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3098005638 |
|
|
Apr 02 01:31:07 PM PDT 24 |
Apr 02 01:32:20 PM PDT 24 |
115891396 ps |
| T44 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.607890396 |
|
|
Apr 02 01:31:31 PM PDT 24 |
Apr 02 01:32:29 PM PDT 24 |
876054700 ps |
| T275 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1177085806 |
|
|
Apr 02 01:23:24 PM PDT 24 |
Apr 02 01:23:26 PM PDT 24 |
47001054 ps |
| T45 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.2554667256 |
|
|
Apr 02 01:29:35 PM PDT 24 |
Apr 02 01:33:03 PM PDT 24 |
1093065619 ps |
| T276 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.3010792614 |
|
|
Apr 02 01:21:45 PM PDT 24 |
Apr 02 01:40:24 PM PDT 24 |
31464066284 ps |
| T277 |
/workspace/coverage/default/13.sram_ctrl_executable.2243062157 |
|
|
Apr 02 01:24:32 PM PDT 24 |
Apr 02 01:27:34 PM PDT 24 |
450332015 ps |
| T278 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.3117792001 |
|
|
Apr 02 01:31:57 PM PDT 24 |
Apr 02 01:37:33 PM PDT 24 |
23437343792 ps |
| T279 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1503862364 |
|
|
Apr 02 01:33:57 PM PDT 24 |
Apr 02 01:39:04 PM PDT 24 |
6495063279 ps |
| T280 |
/workspace/coverage/default/27.sram_ctrl_bijection.3040443114 |
|
|
Apr 02 01:28:28 PM PDT 24 |
Apr 02 01:29:19 PM PDT 24 |
2231759451 ps |
| T281 |
/workspace/coverage/default/17.sram_ctrl_executable.55907339 |
|
|
Apr 02 01:25:54 PM PDT 24 |
Apr 02 01:29:20 PM PDT 24 |
1770480662 ps |
| T282 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1982154211 |
|
|
Apr 02 01:25:42 PM PDT 24 |
Apr 02 01:31:19 PM PDT 24 |
18355984270 ps |
| T283 |
/workspace/coverage/default/49.sram_ctrl_partial_access.3964201266 |
|
|
Apr 02 01:34:07 PM PDT 24 |
Apr 02 01:34:24 PM PDT 24 |
3730057065 ps |
| T284 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.603304929 |
|
|
Apr 02 01:26:27 PM PDT 24 |
Apr 02 01:26:28 PM PDT 24 |
32122708 ps |
| T285 |
/workspace/coverage/default/24.sram_ctrl_alert_test.1313887358 |
|
|
Apr 02 01:27:54 PM PDT 24 |
Apr 02 01:27:55 PM PDT 24 |
21855979 ps |
| T286 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.2548232180 |
|
|
Apr 02 01:30:22 PM PDT 24 |
Apr 02 01:35:46 PM PDT 24 |
6711749679 ps |
| T287 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.2311330505 |
|
|
Apr 02 01:32:01 PM PDT 24 |
Apr 02 01:33:40 PM PDT 24 |
144551649 ps |
| T288 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.629504420 |
|
|
Apr 02 01:24:03 PM PDT 24 |
Apr 02 01:26:12 PM PDT 24 |
2558463312 ps |
| T123 |
/workspace/coverage/default/45.sram_ctrl_stress_all.4126857377 |
|
|
Apr 02 01:33:32 PM PDT 24 |
Apr 02 02:10:54 PM PDT 24 |
22635424656 ps |
| T289 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.903777044 |
|
|
Apr 02 01:30:57 PM PDT 24 |
Apr 02 01:30:58 PM PDT 24 |
76402216 ps |
| T290 |
/workspace/coverage/default/33.sram_ctrl_partial_access.1235382777 |
|
|
Apr 02 01:30:12 PM PDT 24 |
Apr 02 01:30:14 PM PDT 24 |
71944421 ps |
| T291 |
/workspace/coverage/default/17.sram_ctrl_alert_test.1239251136 |
|
|
Apr 02 01:25:54 PM PDT 24 |
Apr 02 01:25:55 PM PDT 24 |
86355033 ps |
| T292 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.3961098993 |
|
|
Apr 02 01:21:49 PM PDT 24 |
Apr 02 01:22:11 PM PDT 24 |
292002642 ps |
| T293 |
/workspace/coverage/default/32.sram_ctrl_alert_test.1810713633 |
|
|
Apr 02 01:30:07 PM PDT 24 |
Apr 02 01:30:08 PM PDT 24 |
31576516 ps |
| T294 |
/workspace/coverage/default/29.sram_ctrl_alert_test.1369594667 |
|
|
Apr 02 01:29:21 PM PDT 24 |
Apr 02 01:29:21 PM PDT 24 |
17137679 ps |
| T295 |
/workspace/coverage/default/21.sram_ctrl_executable.1061062745 |
|
|
Apr 02 01:26:57 PM PDT 24 |
Apr 02 01:54:05 PM PDT 24 |
12781215643 ps |
| T296 |
/workspace/coverage/default/3.sram_ctrl_partial_access.3557659891 |
|
|
Apr 02 01:21:19 PM PDT 24 |
Apr 02 01:21:41 PM PDT 24 |
4664113372 ps |
| T297 |
/workspace/coverage/default/5.sram_ctrl_partial_access.1906971567 |
|
|
Apr 02 01:22:05 PM PDT 24 |
Apr 02 01:22:13 PM PDT 24 |
1798862841 ps |
| T298 |
/workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.3893526822 |
|
|
Apr 02 01:27:29 PM PDT 24 |
Apr 02 01:30:09 PM PDT 24 |
971268501 ps |
| T299 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.522290256 |
|
|
Apr 02 01:23:40 PM PDT 24 |
Apr 02 01:51:22 PM PDT 24 |
4221630990 ps |
| T300 |
/workspace/coverage/default/28.sram_ctrl_executable.3786086180 |
|
|
Apr 02 01:29:00 PM PDT 24 |
Apr 02 01:46:07 PM PDT 24 |
4525068823 ps |
| T301 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.2509959142 |
|
|
Apr 02 01:30:32 PM PDT 24 |
Apr 02 01:41:24 PM PDT 24 |
4211824778 ps |