Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	44756879	1			T1	50126		T2	140944		T3	81643
triple_byte_access	2746377	1			T1	1046		T2	2832		T3	1667
halfword_access	4123889	1			T1	1469		T2	4208		T3	2466
byte_access	5499089	1			T1	2077		T2	5630		T3	3294
zero_access	1385617	1			T1	469		T2	1364		T3	815

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29199862

1

T1

27820

T2

77267

T3

45233

auto[1]

29311989

1

T1

27367

T2

77711

T3

44652

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22329232	1			T1	25252		T2	70240		T3	41114
auto[0]	triple_byte_access	1369237	1			T1	527		T2	1417		T3	819
auto[0]	halfword_access	2057531	1			T1	720		T2	2117		T3	1242
auto[0]	byte_access	2747108	1			T1	1056		T2	2765		T3	1655
auto[0]	zero_access	696754	1			T1	265		T2	728		T3	403
auto[1]	word_access	22427647	1			T1	24874		T2	70704		T3	40529
auto[1]	triple_byte_access	1377140	1			T1	519		T2	1415		T3	848
auto[1]	halfword_access	2066358	1			T1	749		T2	2091		T3	1224
auto[1]	byte_access	2751981	1			T1	1021		T2	2865		T3	1639
auto[1]	zero_access	688863	1			T1	204		T2	636		T3	412