| T794 |
/workspace/coverage/default/38.sram_ctrl_bijection.1211341964 |
|
|
Apr 02 01:31:20 PM PDT 24 |
Apr 02 01:31:59 PM PDT 24 |
2411725846 ps |
| T795 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.129657863 |
|
|
Apr 02 01:28:24 PM PDT 24 |
Apr 02 01:28:29 PM PDT 24 |
163681559 ps |
| T796 |
/workspace/coverage/default/9.sram_ctrl_mem_walk.1373860558 |
|
|
Apr 02 01:23:25 PM PDT 24 |
Apr 02 01:23:34 PM PDT 24 |
137297623 ps |
| T797 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.1865478636 |
|
|
Apr 02 01:30:12 PM PDT 24 |
Apr 02 01:30:16 PM PDT 24 |
358168579 ps |
| T798 |
/workspace/coverage/default/38.sram_ctrl_alert_test.304076372 |
|
|
Apr 02 01:31:34 PM PDT 24 |
Apr 02 01:31:35 PM PDT 24 |
59285784 ps |
| T799 |
/workspace/coverage/default/34.sram_ctrl_stress_all.1452857527 |
|
|
Apr 02 01:30:32 PM PDT 24 |
Apr 02 02:24:57 PM PDT 24 |
87402326021 ps |
| T800 |
/workspace/coverage/default/47.sram_ctrl_alert_test.635344209 |
|
|
Apr 02 01:33:51 PM PDT 24 |
Apr 02 01:33:52 PM PDT 24 |
13735514 ps |
| T801 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.3495615629 |
|
|
Apr 02 01:33:43 PM PDT 24 |
Apr 02 01:38:42 PM PDT 24 |
13166463148 ps |
| T101 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.4256642248 |
|
|
Apr 02 01:29:53 PM PDT 24 |
Apr 02 01:29:58 PM PDT 24 |
1304517809 ps |
| T802 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.2466666849 |
|
|
Apr 02 01:28:52 PM PDT 24 |
Apr 02 01:28:56 PM PDT 24 |
50352915 ps |
| T803 |
/workspace/coverage/default/44.sram_ctrl_smoke.109352734 |
|
|
Apr 02 01:33:01 PM PDT 24 |
Apr 02 01:34:30 PM PDT 24 |
386640598 ps |
| T804 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.3727283175 |
|
|
Apr 02 01:25:40 PM PDT 24 |
Apr 02 01:30:03 PM PDT 24 |
11985902555 ps |
| T805 |
/workspace/coverage/default/12.sram_ctrl_smoke.1712154781 |
|
|
Apr 02 01:24:01 PM PDT 24 |
Apr 02 01:24:42 PM PDT 24 |
375874662 ps |
| T806 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1660148928 |
|
|
Apr 02 01:29:38 PM PDT 24 |
Apr 02 01:32:23 PM PDT 24 |
7108761404 ps |
| T807 |
/workspace/coverage/default/9.sram_ctrl_alert_test.1618706221 |
|
|
Apr 02 01:23:27 PM PDT 24 |
Apr 02 01:23:29 PM PDT 24 |
43484519 ps |
| T808 |
/workspace/coverage/default/46.sram_ctrl_partial_access.1566831823 |
|
|
Apr 02 01:33:33 PM PDT 24 |
Apr 02 01:33:40 PM PDT 24 |
658211290 ps |
| T809 |
/workspace/coverage/default/34.sram_ctrl_alert_test.3401646021 |
|
|
Apr 02 01:30:31 PM PDT 24 |
Apr 02 01:30:32 PM PDT 24 |
29149465 ps |
| T810 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.2388620652 |
|
|
Apr 02 01:28:35 PM PDT 24 |
Apr 02 01:28:42 PM PDT 24 |
1992889185 ps |
| T811 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.3758031738 |
|
|
Apr 02 01:19:52 PM PDT 24 |
Apr 02 01:32:33 PM PDT 24 |
9828069067 ps |
| T812 |
/workspace/coverage/default/6.sram_ctrl_partial_access.2860273051 |
|
|
Apr 02 01:22:18 PM PDT 24 |
Apr 02 01:22:34 PM PDT 24 |
871848930 ps |
| T813 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3345117089 |
|
|
Apr 02 01:32:31 PM PDT 24 |
Apr 02 01:32:31 PM PDT 24 |
14983346 ps |
| T814 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.2444030857 |
|
|
Apr 02 01:21:20 PM PDT 24 |
Apr 02 01:21:23 PM PDT 24 |
161454879 ps |
| T815 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.1602404099 |
|
|
Apr 02 01:26:43 PM PDT 24 |
Apr 02 01:26:46 PM PDT 24 |
276041451 ps |
| T816 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1448039896 |
|
|
Apr 02 01:20:04 PM PDT 24 |
Apr 02 01:20:04 PM PDT 24 |
184129132 ps |
| T817 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.3939597530 |
|
|
Apr 02 01:26:38 PM PDT 24 |
Apr 02 01:28:13 PM PDT 24 |
447189932 ps |
| T818 |
/workspace/coverage/default/49.sram_ctrl_executable.3540716178 |
|
|
Apr 02 01:34:11 PM PDT 24 |
Apr 02 01:55:41 PM PDT 24 |
4318869357 ps |
| T819 |
/workspace/coverage/default/39.sram_ctrl_partial_access.2925947824 |
|
|
Apr 02 01:31:41 PM PDT 24 |
Apr 02 01:31:57 PM PDT 24 |
848993351 ps |
| T820 |
/workspace/coverage/default/31.sram_ctrl_bijection.2182488206 |
|
|
Apr 02 01:29:42 PM PDT 24 |
Apr 02 01:30:09 PM PDT 24 |
6099313146 ps |
| T821 |
/workspace/coverage/default/46.sram_ctrl_executable.4035660114 |
|
|
Apr 02 01:33:35 PM PDT 24 |
Apr 02 01:42:50 PM PDT 24 |
6201238678 ps |
| T822 |
/workspace/coverage/default/24.sram_ctrl_smoke.1301235621 |
|
|
Apr 02 01:27:37 PM PDT 24 |
Apr 02 01:27:50 PM PDT 24 |
205771848 ps |
| T823 |
/workspace/coverage/default/28.sram_ctrl_bijection.400950374 |
|
|
Apr 02 01:28:47 PM PDT 24 |
Apr 02 01:29:02 PM PDT 24 |
231397166 ps |
| T824 |
/workspace/coverage/default/24.sram_ctrl_lc_escalation.1315496113 |
|
|
Apr 02 01:27:48 PM PDT 24 |
Apr 02 01:27:55 PM PDT 24 |
2399599602 ps |
| T825 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.4268607709 |
|
|
Apr 02 01:33:05 PM PDT 24 |
Apr 02 01:40:28 PM PDT 24 |
81619183498 ps |
| T826 |
/workspace/coverage/default/31.sram_ctrl_smoke.2455529334 |
|
|
Apr 02 01:29:35 PM PDT 24 |
Apr 02 01:29:47 PM PDT 24 |
132687697 ps |
| T827 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.384312320 |
|
|
Apr 02 01:30:29 PM PDT 24 |
Apr 02 01:30:34 PM PDT 24 |
643776412 ps |
| T828 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3895932496 |
|
|
Apr 02 01:26:00 PM PDT 24 |
Apr 02 01:28:34 PM PDT 24 |
5436977986 ps |
| T829 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.133081009 |
|
|
Apr 02 01:32:11 PM PDT 24 |
Apr 02 01:32:20 PM PDT 24 |
98450775 ps |
| T830 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.3244050170 |
|
|
Apr 02 01:20:09 PM PDT 24 |
Apr 02 01:20:14 PM PDT 24 |
263590865 ps |
| T831 |
/workspace/coverage/default/25.sram_ctrl_partial_access_b2b.1472022717 |
|
|
Apr 02 01:28:05 PM PDT 24 |
Apr 02 01:34:30 PM PDT 24 |
5139976638 ps |
| T832 |
/workspace/coverage/default/44.sram_ctrl_alert_test.936459176 |
|
|
Apr 02 01:33:17 PM PDT 24 |
Apr 02 01:33:17 PM PDT 24 |
12648261 ps |
| T833 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.3345617829 |
|
|
Apr 02 01:22:51 PM PDT 24 |
Apr 02 01:22:57 PM PDT 24 |
340010466 ps |
| T834 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.2380292228 |
|
|
Apr 02 01:33:57 PM PDT 24 |
Apr 02 01:34:00 PM PDT 24 |
70745814 ps |
| T835 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.2490912886 |
|
|
Apr 02 01:21:35 PM PDT 24 |
Apr 02 01:21:46 PM PDT 24 |
3816467496 ps |
| T836 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.4118798478 |
|
|
Apr 02 01:22:19 PM PDT 24 |
Apr 02 01:22:26 PM PDT 24 |
1407958453 ps |
| T837 |
/workspace/coverage/default/12.sram_ctrl_bijection.3366039516 |
|
|
Apr 02 01:24:03 PM PDT 24 |
Apr 02 01:25:06 PM PDT 24 |
11423453554 ps |
| T838 |
/workspace/coverage/default/6.sram_ctrl_regwen.3799702416 |
|
|
Apr 02 01:22:27 PM PDT 24 |
Apr 02 01:22:44 PM PDT 24 |
5168767810 ps |
| T839 |
/workspace/coverage/default/18.sram_ctrl_partial_access.2848356022 |
|
|
Apr 02 01:25:58 PM PDT 24 |
Apr 02 01:26:15 PM PDT 24 |
3894965385 ps |
| T840 |
/workspace/coverage/default/37.sram_ctrl_partial_access.1339278925 |
|
|
Apr 02 01:31:07 PM PDT 24 |
Apr 02 01:33:09 PM PDT 24 |
192818480 ps |
| T841 |
/workspace/coverage/default/46.sram_ctrl_smoke.3547379723 |
|
|
Apr 02 01:33:31 PM PDT 24 |
Apr 02 01:33:38 PM PDT 24 |
126852429 ps |
| T842 |
/workspace/coverage/default/27.sram_ctrl_regwen.239524483 |
|
|
Apr 02 01:28:39 PM PDT 24 |
Apr 02 01:40:12 PM PDT 24 |
36044991226 ps |
| T843 |
/workspace/coverage/default/43.sram_ctrl_alert_test.3557929343 |
|
|
Apr 02 01:33:00 PM PDT 24 |
Apr 02 01:33:01 PM PDT 24 |
16539386 ps |
| T844 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.331809206 |
|
|
Apr 02 01:31:21 PM PDT 24 |
Apr 02 01:35:02 PM PDT 24 |
3082771228 ps |
| T845 |
/workspace/coverage/default/38.sram_ctrl_smoke.514511317 |
|
|
Apr 02 01:31:18 PM PDT 24 |
Apr 02 01:32:00 PM PDT 24 |
1179022609 ps |
| T846 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.1711862986 |
|
|
Apr 02 01:32:11 PM PDT 24 |
Apr 02 01:37:58 PM PDT 24 |
4902856417 ps |
| T847 |
/workspace/coverage/default/18.sram_ctrl_bijection.3005769137 |
|
|
Apr 02 01:25:59 PM PDT 24 |
Apr 02 01:27:05 PM PDT 24 |
3869330456 ps |
| T848 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.2377620308 |
|
|
Apr 02 01:25:09 PM PDT 24 |
Apr 02 01:29:03 PM PDT 24 |
4505066434 ps |
| T849 |
/workspace/coverage/default/5.sram_ctrl_stress_all.2401995937 |
|
|
Apr 02 01:22:14 PM PDT 24 |
Apr 02 01:41:39 PM PDT 24 |
14354782539 ps |
| T850 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.136766882 |
|
|
Apr 02 01:23:05 PM PDT 24 |
Apr 02 01:23:10 PM PDT 24 |
65681456 ps |
| T851 |
/workspace/coverage/default/2.sram_ctrl_partial_access.689443793 |
|
|
Apr 02 01:20:57 PM PDT 24 |
Apr 02 01:21:12 PM PDT 24 |
293125863 ps |
| T852 |
/workspace/coverage/default/39.sram_ctrl_regwen.4234870712 |
|
|
Apr 02 01:31:42 PM PDT 24 |
Apr 02 01:54:44 PM PDT 24 |
18984847813 ps |
| T853 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.768133937 |
|
|
Apr 02 01:33:33 PM PDT 24 |
Apr 02 01:38:50 PM PDT 24 |
6675642263 ps |
| T854 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.2475346820 |
|
|
Apr 02 01:30:44 PM PDT 24 |
Apr 02 01:30:52 PM PDT 24 |
601494263 ps |
| T855 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.805735784 |
|
|
Apr 02 01:26:18 PM PDT 24 |
Apr 02 01:26:25 PM PDT 24 |
87135163 ps |
| T856 |
/workspace/coverage/default/13.sram_ctrl_bijection.2628733730 |
|
|
Apr 02 01:24:24 PM PDT 24 |
Apr 02 01:25:23 PM PDT 24 |
1962208288 ps |
| T857 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2001440348 |
|
|
Apr 02 01:31:00 PM PDT 24 |
Apr 02 01:31:06 PM PDT 24 |
299808579 ps |
| T858 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.3599066692 |
|
|
Apr 02 01:30:22 PM PDT 24 |
Apr 02 01:43:41 PM PDT 24 |
6582959133 ps |
| T859 |
/workspace/coverage/default/42.sram_ctrl_stress_all.4018826452 |
|
|
Apr 02 01:32:48 PM PDT 24 |
Apr 02 02:08:37 PM PDT 24 |
51477018176 ps |
| T860 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.44262547 |
|
|
Apr 02 01:32:40 PM PDT 24 |
Apr 02 01:33:11 PM PDT 24 |
83530192 ps |
| T861 |
/workspace/coverage/default/32.sram_ctrl_regwen.4145374800 |
|
|
Apr 02 01:29:58 PM PDT 24 |
Apr 02 01:43:13 PM PDT 24 |
10252356243 ps |
| T862 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.856598425 |
|
|
Apr 02 01:28:51 PM PDT 24 |
Apr 02 01:32:46 PM PDT 24 |
13467885336 ps |
| T863 |
/workspace/coverage/default/46.sram_ctrl_multiple_keys.2051887182 |
|
|
Apr 02 01:33:29 PM PDT 24 |
Apr 02 01:52:03 PM PDT 24 |
6327389515 ps |
| T864 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1799676079 |
|
|
Apr 02 01:26:45 PM PDT 24 |
Apr 02 01:26:49 PM PDT 24 |
95919485 ps |
| T865 |
/workspace/coverage/default/0.sram_ctrl_bijection.1870781071 |
|
|
Apr 02 01:19:57 PM PDT 24 |
Apr 02 01:20:55 PM PDT 24 |
896560850 ps |
| T866 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.41218733 |
|
|
Apr 02 01:30:03 PM PDT 24 |
Apr 02 01:30:04 PM PDT 24 |
91967499 ps |
| T867 |
/workspace/coverage/default/41.sram_ctrl_bijection.2724559630 |
|
|
Apr 02 01:32:14 PM PDT 24 |
Apr 02 01:32:36 PM PDT 24 |
1443785010 ps |
| T868 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.4262077091 |
|
|
Apr 02 01:29:55 PM PDT 24 |
Apr 02 01:29:57 PM PDT 24 |
133355185 ps |
| T869 |
/workspace/coverage/default/41.sram_ctrl_regwen.1872617828 |
|
|
Apr 02 01:32:28 PM PDT 24 |
Apr 02 01:34:47 PM PDT 24 |
1315736278 ps |
| T870 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.2533837833 |
|
|
Apr 02 01:34:11 PM PDT 24 |
Apr 02 01:36:27 PM PDT 24 |
782192504 ps |
| T871 |
/workspace/coverage/default/45.sram_ctrl_alert_test.4173353024 |
|
|
Apr 02 01:33:31 PM PDT 24 |
Apr 02 01:33:31 PM PDT 24 |
14642590 ps |
| T872 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2268108453 |
|
|
Apr 02 01:22:05 PM PDT 24 |
Apr 02 01:24:13 PM PDT 24 |
11707258734 ps |
| T873 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.2488582553 |
|
|
Apr 02 01:30:28 PM PDT 24 |
Apr 02 01:30:34 PM PDT 24 |
514231114 ps |
| T874 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.4012201311 |
|
|
Apr 02 01:32:57 PM PDT 24 |
Apr 02 01:49:26 PM PDT 24 |
4054979140 ps |
| T875 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.4146595245 |
|
|
Apr 02 01:30:24 PM PDT 24 |
Apr 02 01:36:08 PM PDT 24 |
13770210009 ps |
| T876 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.4011931259 |
|
|
Apr 02 01:29:32 PM PDT 24 |
Apr 02 01:41:03 PM PDT 24 |
2960417323 ps |
| T877 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.225099818 |
|
|
Apr 02 01:21:09 PM PDT 24 |
Apr 02 01:21:46 PM PDT 24 |
1227538500 ps |
| T878 |
/workspace/coverage/default/45.sram_ctrl_partial_access.1918204492 |
|
|
Apr 02 01:33:21 PM PDT 24 |
Apr 02 01:33:31 PM PDT 24 |
390918021 ps |
| T879 |
/workspace/coverage/default/46.sram_ctrl_bijection.1898340885 |
|
|
Apr 02 01:33:31 PM PDT 24 |
Apr 02 01:33:47 PM PDT 24 |
276150253 ps |
| T880 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.3948755873 |
|
|
Apr 02 01:33:08 PM PDT 24 |
Apr 02 01:33:15 PM PDT 24 |
6955146458 ps |
| T881 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.222910008 |
|
|
Apr 02 01:29:32 PM PDT 24 |
Apr 02 01:29:38 PM PDT 24 |
598421272 ps |
| T882 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2259257979 |
|
|
Apr 02 01:22:45 PM PDT 24 |
Apr 02 01:22:48 PM PDT 24 |
211983307 ps |
| T883 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.189654767 |
|
|
Apr 02 01:32:01 PM PDT 24 |
Apr 02 01:33:08 PM PDT 24 |
431516218 ps |
| T884 |
/workspace/coverage/default/11.sram_ctrl_stress_all.3026799366 |
|
|
Apr 02 01:24:00 PM PDT 24 |
Apr 02 01:52:39 PM PDT 24 |
19017961380 ps |
| T885 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.550518993 |
|
|
Apr 02 01:24:27 PM PDT 24 |
Apr 02 01:25:39 PM PDT 24 |
223924019 ps |
| T886 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.1583956956 |
|
|
Apr 02 01:23:08 PM PDT 24 |
Apr 02 01:23:16 PM PDT 24 |
1858925690 ps |
| T887 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.1561738844 |
|
|
Apr 02 01:30:40 PM PDT 24 |
Apr 02 01:41:50 PM PDT 24 |
2621847357 ps |
| T888 |
/workspace/coverage/default/9.sram_ctrl_bijection.3248069073 |
|
|
Apr 02 01:23:12 PM PDT 24 |
Apr 02 01:23:30 PM PDT 24 |
2395458175 ps |
| T889 |
/workspace/coverage/default/16.sram_ctrl_smoke.130250208 |
|
|
Apr 02 01:25:17 PM PDT 24 |
Apr 02 01:26:10 PM PDT 24 |
435397689 ps |
| T890 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1613633492 |
|
|
Apr 02 01:27:44 PM PDT 24 |
Apr 02 01:35:36 PM PDT 24 |
41182759347 ps |
| T891 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.156337072 |
|
|
Apr 02 01:24:34 PM PDT 24 |
Apr 02 01:26:15 PM PDT 24 |
1031865355 ps |
| T892 |
/workspace/coverage/default/30.sram_ctrl_regwen.1921884576 |
|
|
Apr 02 01:29:35 PM PDT 24 |
Apr 02 01:32:42 PM PDT 24 |
642284905 ps |
| T893 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.3783055094 |
|
|
Apr 02 01:33:34 PM PDT 24 |
Apr 02 01:38:00 PM PDT 24 |
8630112632 ps |
| T894 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1104691148 |
|
|
Apr 02 01:33:05 PM PDT 24 |
Apr 02 01:37:21 PM PDT 24 |
5431054229 ps |
| T895 |
/workspace/coverage/default/4.sram_ctrl_smoke.2302351504 |
|
|
Apr 02 01:21:46 PM PDT 24 |
Apr 02 01:21:49 PM PDT 24 |
98774345 ps |
| T896 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.2761121590 |
|
|
Apr 02 01:21:18 PM PDT 24 |
Apr 02 01:24:09 PM PDT 24 |
1814187905 ps |
| T102 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.1714029355 |
|
|
Apr 02 01:24:13 PM PDT 24 |
Apr 02 01:25:25 PM PDT 24 |
4327292643 ps |
| T897 |
/workspace/coverage/default/22.sram_ctrl_smoke.1652346548 |
|
|
Apr 02 01:27:02 PM PDT 24 |
Apr 02 01:27:58 PM PDT 24 |
1580943135 ps |
| T898 |
/workspace/coverage/default/18.sram_ctrl_smoke.3203745678 |
|
|
Apr 02 01:25:55 PM PDT 24 |
Apr 02 01:26:40 PM PDT 24 |
867793113 ps |
| T899 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.2793998459 |
|
|
Apr 02 01:28:04 PM PDT 24 |
Apr 02 01:47:20 PM PDT 24 |
50567129294 ps |
| T900 |
/workspace/coverage/default/8.sram_ctrl_executable.1424333348 |
|
|
Apr 02 01:23:07 PM PDT 24 |
Apr 02 01:52:16 PM PDT 24 |
4281792045 ps |
| T901 |
/workspace/coverage/default/16.sram_ctrl_ram_cfg.612704632 |
|
|
Apr 02 01:25:30 PM PDT 24 |
Apr 02 01:25:31 PM PDT 24 |
45062087 ps |
| T902 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.771856014 |
|
|
Apr 02 01:26:24 PM PDT 24 |
Apr 02 01:27:38 PM PDT 24 |
916630105 ps |
| T29 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.2715486346 |
|
|
Apr 02 01:22:00 PM PDT 24 |
Apr 02 01:22:03 PM PDT 24 |
789905329 ps |
| T903 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.1819154306 |
|
|
Apr 02 01:30:41 PM PDT 24 |
Apr 02 01:30:48 PM PDT 24 |
245024048 ps |
| T904 |
/workspace/coverage/default/42.sram_ctrl_smoke.2714076699 |
|
|
Apr 02 01:32:33 PM PDT 24 |
Apr 02 01:35:12 PM PDT 24 |
265710168 ps |
| T905 |
/workspace/coverage/default/32.sram_ctrl_smoke.3817418759 |
|
|
Apr 02 01:29:52 PM PDT 24 |
Apr 02 01:29:57 PM PDT 24 |
154998363 ps |
| T906 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3698440675 |
|
|
Apr 02 01:20:35 PM PDT 24 |
Apr 02 01:20:42 PM PDT 24 |
1830380430 ps |
| T907 |
/workspace/coverage/default/19.sram_ctrl_regwen.2375667691 |
|
|
Apr 02 01:26:27 PM PDT 24 |
Apr 02 01:50:54 PM PDT 24 |
133938303583 ps |
| T908 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.1341502090 |
|
|
Apr 02 01:32:56 PM PDT 24 |
Apr 02 01:35:30 PM PDT 24 |
811295911 ps |
| T909 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.3745028118 |
|
|
Apr 02 01:24:35 PM PDT 24 |
Apr 02 01:24:40 PM PDT 24 |
413288914 ps |
| T910 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.315541640 |
|
|
Apr 02 01:31:31 PM PDT 24 |
Apr 02 01:31:36 PM PDT 24 |
149086229 ps |
| T911 |
/workspace/coverage/default/24.sram_ctrl_regwen.2560941457 |
|
|
Apr 02 01:27:53 PM PDT 24 |
Apr 02 01:45:07 PM PDT 24 |
46164324648 ps |
| T912 |
/workspace/coverage/default/2.sram_ctrl_smoke.3267331313 |
|
|
Apr 02 01:20:49 PM PDT 24 |
Apr 02 01:21:34 PM PDT 24 |
375943652 ps |
| T913 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3486033027 |
|
|
Apr 02 01:23:20 PM PDT 24 |
Apr 02 01:23:23 PM PDT 24 |
318676182 ps |
| T914 |
/workspace/coverage/default/37.sram_ctrl_bijection.2898168211 |
|
|
Apr 02 01:31:05 PM PDT 24 |
Apr 02 01:31:32 PM PDT 24 |
1277439933 ps |
| T915 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.2649446996 |
|
|
Apr 02 01:30:24 PM PDT 24 |
Apr 02 01:30:37 PM PDT 24 |
64113902 ps |
| T916 |
/workspace/coverage/default/30.sram_ctrl_smoke.1670659272 |
|
|
Apr 02 01:29:22 PM PDT 24 |
Apr 02 01:29:25 PM PDT 24 |
450448468 ps |
| T917 |
/workspace/coverage/default/25.sram_ctrl_smoke.1179941207 |
|
|
Apr 02 01:27:59 PM PDT 24 |
Apr 02 01:29:21 PM PDT 24 |
1122392049 ps |
| T918 |
/workspace/coverage/default/23.sram_ctrl_partial_access.2980118758 |
|
|
Apr 02 01:27:28 PM PDT 24 |
Apr 02 01:27:43 PM PDT 24 |
10666125844 ps |
| T919 |
/workspace/coverage/default/30.sram_ctrl_partial_access.456016889 |
|
|
Apr 02 01:29:29 PM PDT 24 |
Apr 02 01:29:41 PM PDT 24 |
190257585 ps |
| T920 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.2706412913 |
|
|
Apr 02 01:21:48 PM PDT 24 |
Apr 02 01:28:46 PM PDT 24 |
19630502584 ps |
| T921 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.186221359 |
|
|
Apr 02 01:30:37 PM PDT 24 |
Apr 02 01:34:25 PM PDT 24 |
9183227574 ps |
| T922 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.214031359 |
|
|
Apr 02 01:26:14 PM PDT 24 |
Apr 02 01:26:56 PM PDT 24 |
228850608 ps |
| T923 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.1455534184 |
|
|
Apr 02 01:32:18 PM PDT 24 |
Apr 02 01:33:32 PM PDT 24 |
110299551 ps |
| T924 |
/workspace/coverage/default/15.sram_ctrl_alert_test.99040223 |
|
|
Apr 02 01:25:17 PM PDT 24 |
Apr 02 01:25:18 PM PDT 24 |
21834033 ps |
| T925 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.4227772843 |
|
|
Apr 02 01:26:38 PM PDT 24 |
Apr 02 01:31:35 PM PDT 24 |
33104357078 ps |
| T926 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.3896349917 |
|
|
Apr 02 01:30:28 PM PDT 24 |
Apr 02 01:30:34 PM PDT 24 |
341505075 ps |
| T927 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3470970809 |
|
|
Apr 02 01:20:30 PM PDT 24 |
Apr 02 01:26:15 PM PDT 24 |
11489285265 ps |
| T928 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1366600309 |
|
|
Apr 02 01:22:38 PM PDT 24 |
Apr 02 01:25:32 PM PDT 24 |
9636842716 ps |
| T929 |
/workspace/coverage/default/40.sram_ctrl_smoke.3610649942 |
|
|
Apr 02 01:31:55 PM PDT 24 |
Apr 02 01:32:08 PM PDT 24 |
1191606976 ps |
| T930 |
/workspace/coverage/default/11.sram_ctrl_executable.357358768 |
|
|
Apr 02 01:23:57 PM PDT 24 |
Apr 02 01:41:02 PM PDT 24 |
43237687173 ps |
| T931 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3137742497 |
|
|
Apr 02 12:26:31 PM PDT 24 |
Apr 02 12:26:32 PM PDT 24 |
40992604 ps |
| T54 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.20997325 |
|
|
Apr 02 12:26:37 PM PDT 24 |
Apr 02 12:26:42 PM PDT 24 |
1374441094 ps |
| T932 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.861764823 |
|
|
Apr 02 12:26:57 PM PDT 24 |
Apr 02 12:26:59 PM PDT 24 |
100805662 ps |
| T55 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2346166102 |
|
|
Apr 02 12:26:44 PM PDT 24 |
Apr 02 12:26:45 PM PDT 24 |
406424700 ps |
| T93 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2711795439 |
|
|
Apr 02 12:26:36 PM PDT 24 |
Apr 02 12:26:41 PM PDT 24 |
143221705 ps |
| T89 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3824537260 |
|
|
Apr 02 12:26:26 PM PDT 24 |
Apr 02 12:26:26 PM PDT 24 |
16942098 ps |
| T56 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2861316001 |
|
|
Apr 02 12:26:53 PM PDT 24 |
Apr 02 12:26:54 PM PDT 24 |
68710876 ps |
| T933 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2380996785 |
|
|
Apr 02 12:26:37 PM PDT 24 |
Apr 02 12:26:41 PM PDT 24 |
82199203 ps |
| T57 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3194291906 |
|
|
Apr 02 12:26:52 PM PDT 24 |
Apr 02 12:26:55 PM PDT 24 |
424287897 ps |
| T58 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3948661542 |
|
|
Apr 02 12:26:48 PM PDT 24 |
Apr 02 12:26:49 PM PDT 24 |
19417203 ps |
| T934 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4014851967 |
|
|
Apr 02 12:26:11 PM PDT 24 |
Apr 02 12:26:14 PM PDT 24 |
764350516 ps |
| T81 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.482572537 |
|
|
Apr 02 12:26:58 PM PDT 24 |
Apr 02 12:26:59 PM PDT 24 |
33859547 ps |
| T59 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.865837485 |
|
|
Apr 02 12:26:57 PM PDT 24 |
Apr 02 12:27:00 PM PDT 24 |
1734617415 ps |
| T935 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3478931682 |
|
|
Apr 02 12:26:26 PM PDT 24 |
Apr 02 12:26:28 PM PDT 24 |
46631684 ps |
| T60 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2501976528 |
|
|
Apr 02 12:26:09 PM PDT 24 |
Apr 02 12:26:11 PM PDT 24 |
404656997 ps |
| T936 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2553456142 |
|
|
Apr 02 12:26:55 PM PDT 24 |
Apr 02 12:26:56 PM PDT 24 |
30078512 ps |
| T90 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.995494075 |
|
|
Apr 02 12:26:57 PM PDT 24 |
Apr 02 12:26:58 PM PDT 24 |
32806625 ps |
| T82 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.17411444 |
|
|
Apr 02 12:26:52 PM PDT 24 |
Apr 02 12:26:54 PM PDT 24 |
26477495 ps |
| T937 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.644708302 |
|
|
Apr 02 12:26:53 PM PDT 24 |
Apr 02 12:26:57 PM PDT 24 |
115499342 ps |
| T61 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.944144386 |
|
|
Apr 02 12:26:14 PM PDT 24 |
Apr 02 12:26:15 PM PDT 24 |
13370107 ps |
| T938 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.529675538 |
|
|
Apr 02 12:26:40 PM PDT 24 |
Apr 02 12:26:43 PM PDT 24 |
24898798 ps |
| T939 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1897844025 |
|
|
Apr 02 12:26:03 PM PDT 24 |
Apr 02 12:26:04 PM PDT 24 |
11156569 ps |
| T62 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1062939482 |
|
|
Apr 02 12:26:09 PM PDT 24 |
Apr 02 12:26:14 PM PDT 24 |
38915437 ps |
| T63 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.267625264 |
|
|
Apr 02 12:26:55 PM PDT 24 |
Apr 02 12:26:56 PM PDT 24 |
15576788 ps |
| T64 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2903709219 |
|
|
Apr 02 12:26:10 PM PDT 24 |
Apr 02 12:26:11 PM PDT 24 |
20720301 ps |
| T940 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4120810010 |
|
|
Apr 02 12:26:54 PM PDT 24 |
Apr 02 12:26:56 PM PDT 24 |
82056592 ps |
| T941 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1036667832 |
|
|
Apr 02 12:26:12 PM PDT 24 |
Apr 02 12:26:14 PM PDT 24 |
100503584 ps |
| T65 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2554646898 |
|
|
Apr 02 12:26:48 PM PDT 24 |
Apr 02 12:26:49 PM PDT 24 |
37365963 ps |
| T94 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3984508062 |
|
|
Apr 02 12:26:48 PM PDT 24 |
Apr 02 12:26:49 PM PDT 24 |
174341117 ps |
| T942 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1979691488 |
|
|
Apr 02 12:26:35 PM PDT 24 |
Apr 02 12:26:36 PM PDT 24 |
226277633 ps |
| T943 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2837098615 |
|
|
Apr 02 12:26:16 PM PDT 24 |
Apr 02 12:26:19 PM PDT 24 |
2153897603 ps |
| T944 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.308701173 |
|
|
Apr 02 12:26:47 PM PDT 24 |
Apr 02 12:26:49 PM PDT 24 |
124918031 ps |
| T945 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.832786478 |
|
|
Apr 02 12:26:04 PM PDT 24 |
Apr 02 12:26:09 PM PDT 24 |
146279186 ps |
| T946 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2135485598 |
|
|
Apr 02 12:26:16 PM PDT 24 |
Apr 02 12:26:27 PM PDT 24 |
198524018 ps |
| T66 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2747007378 |
|
|
Apr 02 12:26:10 PM PDT 24 |
Apr 02 12:26:13 PM PDT 24 |
396398901 ps |
| T947 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3219114145 |
|
|
Apr 02 12:26:44 PM PDT 24 |
Apr 02 12:26:45 PM PDT 24 |
151964980 ps |
| T948 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.940184671 |
|
|
Apr 02 12:26:31 PM PDT 24 |
Apr 02 12:26:31 PM PDT 24 |
16131047 ps |
| T949 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2772246059 |
|
|
Apr 02 12:26:56 PM PDT 24 |
Apr 02 12:26:57 PM PDT 24 |
15578586 ps |
| T950 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3673780141 |
|
|
Apr 02 12:26:14 PM PDT 24 |
Apr 02 12:26:17 PM PDT 24 |
70204741 ps |
| T95 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3343342980 |
|
|
Apr 02 12:26:55 PM PDT 24 |
Apr 02 12:26:58 PM PDT 24 |
530130353 ps |
| T67 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3749718228 |
|
|
Apr 02 12:26:28 PM PDT 24 |
Apr 02 12:26:30 PM PDT 24 |
802397731 ps |
| T951 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3717592467 |
|
|
Apr 02 12:26:50 PM PDT 24 |
Apr 02 12:26:51 PM PDT 24 |
11658625 ps |
| T952 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1067819172 |
|
|
Apr 02 12:26:28 PM PDT 24 |
Apr 02 12:26:35 PM PDT 24 |
49271046 ps |
| T68 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2373745653 |
|
|
Apr 02 12:26:11 PM PDT 24 |
Apr 02 12:26:13 PM PDT 24 |
412099186 ps |
| T75 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3168953971 |
|
|
Apr 02 12:26:10 PM PDT 24 |
Apr 02 12:26:15 PM PDT 24 |
227006464 ps |
| T953 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2760178098 |
|
|
Apr 02 12:26:31 PM PDT 24 |
Apr 02 12:26:32 PM PDT 24 |
34805275 ps |
| T954 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3247995522 |
|
|
Apr 02 12:26:55 PM PDT 24 |
Apr 02 12:26:56 PM PDT 24 |
50260449 ps |
| T955 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3301294358 |
|
|
Apr 02 12:26:50 PM PDT 24 |
Apr 02 12:26:51 PM PDT 24 |
98684977 ps |
| T115 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.831857347 |
|
|
Apr 02 12:26:10 PM PDT 24 |
Apr 02 12:26:13 PM PDT 24 |
603705423 ps |
| T956 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3566309678 |
|
|
Apr 02 12:26:47 PM PDT 24 |
Apr 02 12:26:49 PM PDT 24 |
250952613 ps |
| T957 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.2928570831 |
|
|
Apr 02 12:26:47 PM PDT 24 |
Apr 02 12:26:47 PM PDT 24 |
30679269 ps |
| T76 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3771491361 |
|
|
Apr 02 12:26:38 PM PDT 24 |
Apr 02 12:26:41 PM PDT 24 |
1509624349 ps |
| T958 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3986660916 |
|
|
Apr 02 12:26:17 PM PDT 24 |
Apr 02 12:26:21 PM PDT 24 |
440295502 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3725682360 |
|
|
Apr 02 12:26:47 PM PDT 24 |
Apr 02 12:26:48 PM PDT 24 |
46480466 ps |
| T116 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.961101017 |
|
|
Apr 02 12:26:36 PM PDT 24 |
Apr 02 12:26:41 PM PDT 24 |
1821979056 ps |
| T960 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2853311375 |
|
|
Apr 02 12:26:39 PM PDT 24 |
Apr 02 12:26:42 PM PDT 24 |
12507954 ps |
| T112 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2611965322 |
|
|
Apr 02 12:26:58 PM PDT 24 |
Apr 02 12:27:00 PM PDT 24 |
214506560 ps |
| T113 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.1040031182 |
|
|
Apr 02 12:26:27 PM PDT 24 |
Apr 02 12:26:29 PM PDT 24 |
199576637 ps |
| T961 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.4081405181 |
|
|
Apr 02 12:26:51 PM PDT 24 |
Apr 02 12:26:55 PM PDT 24 |
185865318 ps |
| T77 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3686526685 |
|
|
Apr 02 12:26:58 PM PDT 24 |
Apr 02 12:26:58 PM PDT 24 |
20080661 ps |
| T962 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1092520841 |
|
|
Apr 02 12:26:30 PM PDT 24 |
Apr 02 12:26:35 PM PDT 24 |
590204661 ps |
| T963 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.158644612 |
|
|
Apr 02 12:26:38 PM PDT 24 |
Apr 02 12:26:40 PM PDT 24 |
15598205 ps |
| T78 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3066700020 |
|
|
Apr 02 12:26:49 PM PDT 24 |
Apr 02 12:26:53 PM PDT 24 |
893074176 ps |
| T114 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.432015666 |
|
|
Apr 02 12:26:09 PM PDT 24 |
Apr 02 12:26:10 PM PDT 24 |
375683203 ps |
| T117 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2249193792 |
|
|
Apr 02 12:26:48 PM PDT 24 |
Apr 02 12:26:50 PM PDT 24 |
647391598 ps |
| T964 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1402620996 |
|
|
Apr 02 12:26:43 PM PDT 24 |
Apr 02 12:26:45 PM PDT 24 |
76338857 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3556490278 |
|
|
Apr 02 12:26:46 PM PDT 24 |
Apr 02 12:26:47 PM PDT 24 |
25407164 ps |
| T966 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2687463320 |
|
|
Apr 02 12:26:10 PM PDT 24 |
Apr 02 12:26:12 PM PDT 24 |
235820221 ps |
| T967 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.412213301 |
|
|
Apr 02 12:26:38 PM PDT 24 |
Apr 02 12:26:42 PM PDT 24 |
169048264 ps |
| T968 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2282376368 |
|
|
Apr 02 12:26:32 PM PDT 24 |
Apr 02 12:26:33 PM PDT 24 |
36247520 ps |
| T969 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2030695960 |
|
|
Apr 02 12:26:09 PM PDT 24 |
Apr 02 12:26:09 PM PDT 24 |
22782611 ps |
| T970 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3555741016 |
|
|
Apr 02 12:26:12 PM PDT 24 |
Apr 02 12:26:13 PM PDT 24 |
112264305 ps |
| T79 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.797557877 |
|
|
Apr 02 12:26:10 PM PDT 24 |
Apr 02 12:26:13 PM PDT 24 |
7874811044 ps |
| T971 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.944814886 |
|
|
Apr 02 12:26:11 PM PDT 24 |
Apr 02 12:26:15 PM PDT 24 |
38019835 ps |
| T972 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2399379374 |
|
|
Apr 02 12:26:46 PM PDT 24 |
Apr 02 12:26:48 PM PDT 24 |
112877226 ps |
| T973 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1556377121 |
|
|
Apr 02 12:26:44 PM PDT 24 |
Apr 02 12:26:45 PM PDT 24 |
56307640 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.2436193886 |
|
|
Apr 02 12:26:53 PM PDT 24 |
Apr 02 12:26:54 PM PDT 24 |
71275058 ps |
| T975 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2661283186 |
|
|
Apr 02 12:26:15 PM PDT 24 |
Apr 02 12:26:16 PM PDT 24 |
40488474 ps |
| T119 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1089181618 |
|
|
Apr 02 12:27:02 PM PDT 24 |
Apr 02 12:27:05 PM PDT 24 |
143879859 ps |
| T976 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.236061751 |
|
|
Apr 02 12:26:51 PM PDT 24 |
Apr 02 12:26:52 PM PDT 24 |
19450223 ps |
| T977 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.4145376841 |
|
|
Apr 02 12:26:46 PM PDT 24 |
Apr 02 12:26:48 PM PDT 24 |
418937492 ps |
| T978 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2159232911 |
|
|
Apr 02 12:26:08 PM PDT 24 |
Apr 02 12:26:09 PM PDT 24 |
115756954 ps |
| T979 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2849931797 |
|
|
Apr 02 12:26:33 PM PDT 24 |
Apr 02 12:26:37 PM PDT 24 |
110418671 ps |
| T980 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3606293139 |
|
|
Apr 02 12:26:18 PM PDT 24 |
Apr 02 12:26:19 PM PDT 24 |
19626133 ps |
| T981 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.4048098977 |
|
|
Apr 02 12:26:42 PM PDT 24 |
Apr 02 12:26:43 PM PDT 24 |
22287916 ps |
| T80 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2200112852 |
|
|
Apr 02 12:26:55 PM PDT 24 |
Apr 02 12:26:59 PM PDT 24 |
381105365 ps |
| T120 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2195313821 |
|
|
Apr 02 12:26:11 PM PDT 24 |
Apr 02 12:26:12 PM PDT 24 |
504245842 ps |
| T982 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2573288685 |
|
|
Apr 02 12:26:57 PM PDT 24 |
Apr 02 12:26:57 PM PDT 24 |
21427850 ps |
| T983 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3969534819 |
|
|
Apr 02 12:26:09 PM PDT 24 |
Apr 02 12:26:11 PM PDT 24 |
540144688 ps |
| T984 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3707358923 |
|
|
Apr 02 12:26:59 PM PDT 24 |
Apr 02 12:27:00 PM PDT 24 |
172035766 ps |
| T985 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.352421973 |
|
|
Apr 02 12:26:42 PM PDT 24 |
Apr 02 12:26:44 PM PDT 24 |
44185777 ps |
| T986 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2786696831 |
|
|
Apr 02 12:26:45 PM PDT 24 |
Apr 02 12:26:47 PM PDT 24 |
28016344 ps |
| T118 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2806079839 |
|
|
Apr 02 12:26:33 PM PDT 24 |
Apr 02 12:26:34 PM PDT 24 |
164968221 ps |
| T121 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.728615732 |
|
|
Apr 02 12:26:58 PM PDT 24 |
Apr 02 12:27:01 PM PDT 24 |
292476824 ps |
| T987 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.945716914 |
|
|
Apr 02 12:26:50 PM PDT 24 |
Apr 02 12:26:51 PM PDT 24 |
22372706 ps |
| T988 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2768727669 |
|
|
Apr 02 12:26:10 PM PDT 24 |
Apr 02 12:26:12 PM PDT 24 |
790093046 ps |
| T989 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1846006046 |
|
|
Apr 02 12:26:49 PM PDT 24 |
Apr 02 12:26:52 PM PDT 24 |
142613150 ps |
| T990 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2689127778 |
|
|
Apr 02 12:26:35 PM PDT 24 |
Apr 02 12:26:39 PM PDT 24 |
42605897 ps |
| T991 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3744842644 |
|
|
Apr 02 12:26:32 PM PDT 24 |
Apr 02 12:26:33 PM PDT 24 |
207280375 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1794672288 |
|
|
Apr 02 12:26:13 PM PDT 24 |
Apr 02 12:26:13 PM PDT 24 |
36151127 ps |
| T122 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3696300327 |
|
|
Apr 02 12:26:09 PM PDT 24 |
Apr 02 12:26:10 PM PDT 24 |
178695717 ps |
| T993 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3995653877 |
|
|
Apr 02 12:26:28 PM PDT 24 |
Apr 02 12:26:30 PM PDT 24 |
37871782 ps |
| T994 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1181178684 |
|
|
Apr 02 12:26:58 PM PDT 24 |
Apr 02 12:27:06 PM PDT 24 |
28113226 ps |
| T995 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.552065115 |
|
|
Apr 02 12:26:47 PM PDT 24 |
Apr 02 12:26:47 PM PDT 24 |
17926545 ps |
| T996 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.623753817 |
|
|
Apr 02 12:26:09 PM PDT 24 |
Apr 02 12:26:09 PM PDT 24 |
19388178 ps |
| T997 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.106082548 |
|
|
Apr 02 12:26:12 PM PDT 24 |
Apr 02 12:26:13 PM PDT 24 |
107896476 ps |
| T998 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.1986542214 |
|
|
Apr 02 12:27:01 PM PDT 24 |
Apr 02 12:27:02 PM PDT 24 |
11595132 ps |
| T999 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3250362991 |
|
|
Apr 02 12:26:46 PM PDT 24 |
Apr 02 12:26:47 PM PDT 24 |
330059363 ps |
| T1000 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2107328746 |
|
|
Apr 02 12:26:54 PM PDT 24 |
Apr 02 12:26:55 PM PDT 24 |
14944607 ps |
| T1001 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3285392770 |
|
|
Apr 02 12:26:07 PM PDT 24 |
Apr 02 12:26:08 PM PDT 24 |
84139331 ps |