Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	140772512	1			T1	309524		T2	1938		T3	412872
instr_valid_dis	114264676	1			T1	309524		T2	1938		T3	279236
instr_en	18338733	1			T3	97152		T10	65286		T4	176874

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	9168785	1			T3	172322		T10	39974		T4	59858
sram_ifetch_valid_disable	110476340	1			T1	309524		T2	1938		T3	163230
sram_ifetch_enable	21127387	1			T3	77320		T10	68040		T4	176458

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	140772512	1			T1	309524		T2	1938		T3	412872
hw_debug_en_valid_off	111926188	1			T1	309524		T2	1938		T3	165680
hw_debug_en_on	18666332	1			T3	230720		T10	108084		T4	142218

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	110476340	1			T1	309524		T2	1938		T3	163230
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	99831457	1			T1	309524		T2	1938		T3	126448
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	7188492	1			T3	36782		T10	61008		T4	68152
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4294720	1			T3	101698		T10	7824		T54	18012
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1971366	1			T3	51398		T10	7824		T24	42492
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1565096	1			T3	28980		T54	18012		T16	41340
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	2940799	1			T3	54152		T10	3776		T36	36452
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1304490	1			T3	54152		T36	36452		T16	14268
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1271459	1			T10	3776		T54	10992		T56	74106
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8447749	1			T3	126448		T10	84310		T4	61576
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	4326251	1			T3	126448		T10	23302		T36	20754
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2545048	1			T10	61008		T4	61576		T36	32096

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	7759386	1			T3	31390		T10	502		T4	48864
lc_exec_en	7277784	1			T3	50120		T10	19998		T4	80642
valid_exec_dis	107899558	1			T1	309524		T2	1938		T3	67548
invalid_exec_dis	30296172	1			T3	249642		T10	108014		T4	236316