| Name |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3814017306 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3643563335 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.179786217 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3089872172 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.348798083 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1492568581 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1655053699 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4084989549 |
| /workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.4128900583 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1847506721 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.583569651 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1922963595 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3587611851 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.11417434 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4035201297 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2355253803 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.146526730 |
| /workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1436146730 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.272877979 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1278013806 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.322218384 |
| /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.949171767 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.2416270664 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1427484515 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3425163147 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.2322476228 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2991042074 |
| /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2988605260 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2439853863 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.327050958 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1860476233 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3234020403 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4029160304 |
| /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3007761344 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.2944452267 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2394718332 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3989300570 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3563937414 |
| /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.4203708763 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1361384288 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3682881585 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.1124390119 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2356847808 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2258854791 |
| /workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3821000548 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.82903981 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2155760651 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3342041072 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.285002104 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1681711084 |
| /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2757891026 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.956528524 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3292781361 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3269028057 |
| /workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.802594902 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3886943175 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.559805122 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1890386628 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3831505106 |
| /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.340713950 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2729328135 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2373663542 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2941133830 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.511468890 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3243430025 |
| /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.724417509 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1254857862 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.176869156 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4246201021 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.336311911 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1725848880 |
| /workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.1782603566 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2495721323 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2348887414 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1381835265 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.634495173 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3240423578 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.789829771 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2876052338 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1418970179 |
| /workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.805193334 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.719296780 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3731214319 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3466029462 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3386822483 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.4253172545 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.984906250 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.379238762 |
| /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.258392499 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.4245478385 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.3468963681 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1098507353 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3433906044 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2075104599 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1541493787 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4197770104 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3363227457 |
| /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1462864388 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1954728367 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.382901203 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2718151976 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.684378270 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.223185099 |
| /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1368394964 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3126231790 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.956736726 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.595950068 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.3479385681 |
| /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.571755137 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2938644125 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2966546131 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1439752091 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3705917314 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1117201019 |
| /workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1725448267 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.3267301763 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.662212842 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1502002320 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.398599366 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.640438655 |
| /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2760619640 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.873446605 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3157858477 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3030915203 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1752152407 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1886661300 |
| /workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.699359650 |
| /workspace/coverage/default/0.sram_ctrl_access_during_key_req.3157033008 |
| /workspace/coverage/default/0.sram_ctrl_alert_test.2331520069 |
| /workspace/coverage/default/0.sram_ctrl_bijection.793991957 |
| /workspace/coverage/default/0.sram_ctrl_lc_escalation.2948268589 |
| /workspace/coverage/default/0.sram_ctrl_max_throughput.3376316865 |
| /workspace/coverage/default/0.sram_ctrl_mem_partial_access.892554669 |
| /workspace/coverage/default/0.sram_ctrl_mem_walk.2068660776 |
| /workspace/coverage/default/0.sram_ctrl_multiple_keys.4291465247 |
| /workspace/coverage/default/0.sram_ctrl_partial_access.2929754753 |
| /workspace/coverage/default/0.sram_ctrl_partial_access_b2b.307745816 |
| /workspace/coverage/default/0.sram_ctrl_ram_cfg.3044146128 |
| /workspace/coverage/default/0.sram_ctrl_regwen.4014631864 |
| /workspace/coverage/default/0.sram_ctrl_sec_cm.3987162567 |
| /workspace/coverage/default/0.sram_ctrl_smoke.3948550783 |
| /workspace/coverage/default/0.sram_ctrl_stress_all.3523723403 |
| /workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3064243424 |
| /workspace/coverage/default/0.sram_ctrl_stress_pipeline.2912411597 |
| /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2146414677 |
| /workspace/coverage/default/1.sram_ctrl_access_during_key_req.440632165 |
| /workspace/coverage/default/1.sram_ctrl_bijection.2991172565 |
| /workspace/coverage/default/1.sram_ctrl_executable.2660258991 |
| /workspace/coverage/default/1.sram_ctrl_lc_escalation.3945581458 |
| /workspace/coverage/default/1.sram_ctrl_max_throughput.2341970435 |
| /workspace/coverage/default/1.sram_ctrl_mem_partial_access.2539218521 |
| /workspace/coverage/default/1.sram_ctrl_mem_walk.485967147 |
| /workspace/coverage/default/1.sram_ctrl_multiple_keys.3895233826 |
| /workspace/coverage/default/1.sram_ctrl_partial_access.886876183 |
| /workspace/coverage/default/1.sram_ctrl_partial_access_b2b.289485869 |
| /workspace/coverage/default/1.sram_ctrl_ram_cfg.440071046 |
| /workspace/coverage/default/1.sram_ctrl_regwen.3775108576 |
| /workspace/coverage/default/1.sram_ctrl_smoke.212907601 |
| /workspace/coverage/default/1.sram_ctrl_stress_all.3907212805 |
| /workspace/coverage/default/1.sram_ctrl_stress_pipeline.1306727130 |
| /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.3394179172 |
| /workspace/coverage/default/10.sram_ctrl_access_during_key_req.4014662955 |
| /workspace/coverage/default/10.sram_ctrl_alert_test.2125761069 |
| /workspace/coverage/default/10.sram_ctrl_bijection.2119547583 |
| /workspace/coverage/default/10.sram_ctrl_executable.2040922700 |
| /workspace/coverage/default/10.sram_ctrl_lc_escalation.1615483695 |
| /workspace/coverage/default/10.sram_ctrl_max_throughput.3571500068 |
| /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2181029194 |
| /workspace/coverage/default/10.sram_ctrl_mem_walk.3297499037 |
| /workspace/coverage/default/10.sram_ctrl_multiple_keys.1189406063 |
| /workspace/coverage/default/10.sram_ctrl_partial_access.3809574421 |
| /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.462047101 |
| /workspace/coverage/default/10.sram_ctrl_ram_cfg.3803958397 |
| /workspace/coverage/default/10.sram_ctrl_regwen.2176152014 |
| /workspace/coverage/default/10.sram_ctrl_smoke.3746006239 |
| /workspace/coverage/default/10.sram_ctrl_stress_all.3935827239 |
| /workspace/coverage/default/10.sram_ctrl_stress_pipeline.3399406614 |
| /workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1924325355 |
| /workspace/coverage/default/11.sram_ctrl_access_during_key_req.205383138 |
| /workspace/coverage/default/11.sram_ctrl_alert_test.704477933 |
| /workspace/coverage/default/11.sram_ctrl_bijection.1221331156 |
| /workspace/coverage/default/11.sram_ctrl_executable.3598838113 |
| /workspace/coverage/default/11.sram_ctrl_lc_escalation.100235718 |
| /workspace/coverage/default/11.sram_ctrl_max_throughput.1152714081 |
| /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3513432328 |
| /workspace/coverage/default/11.sram_ctrl_mem_walk.1941262276 |
| /workspace/coverage/default/11.sram_ctrl_partial_access.2637647700 |
| /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1630805603 |
| /workspace/coverage/default/11.sram_ctrl_ram_cfg.2654632337 |
| /workspace/coverage/default/11.sram_ctrl_regwen.2961167706 |
| /workspace/coverage/default/11.sram_ctrl_smoke.3316569206 |
| /workspace/coverage/default/11.sram_ctrl_stress_all.4293676267 |
| /workspace/coverage/default/11.sram_ctrl_stress_pipeline.1327728576 |
| /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.2328340416 |
| /workspace/coverage/default/12.sram_ctrl_access_during_key_req.182521401 |
| /workspace/coverage/default/12.sram_ctrl_alert_test.1168014206 |
| /workspace/coverage/default/12.sram_ctrl_bijection.203318125 |
| /workspace/coverage/default/12.sram_ctrl_executable.38597114 |
| /workspace/coverage/default/12.sram_ctrl_lc_escalation.654149093 |
| /workspace/coverage/default/12.sram_ctrl_max_throughput.184746476 |
| /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2414802768 |
| /workspace/coverage/default/12.sram_ctrl_mem_walk.1099971761 |
| /workspace/coverage/default/12.sram_ctrl_multiple_keys.373788634 |
| /workspace/coverage/default/12.sram_ctrl_partial_access.714780846 |
| /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.63375511 |
| /workspace/coverage/default/12.sram_ctrl_ram_cfg.2848852389 |
| /workspace/coverage/default/12.sram_ctrl_regwen.1726352204 |
| /workspace/coverage/default/12.sram_ctrl_smoke.3699999881 |
| /workspace/coverage/default/12.sram_ctrl_stress_all.1708137708 |
| /workspace/coverage/default/12.sram_ctrl_stress_pipeline.288614622 |
| /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1146519540 |
| /workspace/coverage/default/13.sram_ctrl_access_during_key_req.244097806 |
| /workspace/coverage/default/13.sram_ctrl_alert_test.1582188003 |
| /workspace/coverage/default/13.sram_ctrl_bijection.873903955 |
| /workspace/coverage/default/13.sram_ctrl_executable.4198339726 |
| /workspace/coverage/default/13.sram_ctrl_lc_escalation.4084718417 |
| /workspace/coverage/default/13.sram_ctrl_max_throughput.121826739 |
| /workspace/coverage/default/13.sram_ctrl_mem_partial_access.2086673372 |
| /workspace/coverage/default/13.sram_ctrl_mem_walk.2547171397 |
| /workspace/coverage/default/13.sram_ctrl_multiple_keys.2885155761 |
| /workspace/coverage/default/13.sram_ctrl_partial_access.2243611934 |
| /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.477897561 |
| /workspace/coverage/default/13.sram_ctrl_regwen.1005071427 |
| /workspace/coverage/default/13.sram_ctrl_smoke.1801429995 |
| /workspace/coverage/default/13.sram_ctrl_stress_all.3784733683 |
| /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.912609625 |
| /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1749432693 |
| /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3822720653 |
| /workspace/coverage/default/14.sram_ctrl_access_during_key_req.4054379568 |
| /workspace/coverage/default/14.sram_ctrl_alert_test.2589366621 |
| /workspace/coverage/default/14.sram_ctrl_bijection.2259637033 |
| /workspace/coverage/default/14.sram_ctrl_executable.3683117794 |
| /workspace/coverage/default/14.sram_ctrl_max_throughput.2467614640 |
| /workspace/coverage/default/14.sram_ctrl_mem_partial_access.4080682806 |
| /workspace/coverage/default/14.sram_ctrl_mem_walk.2196347801 |
| /workspace/coverage/default/14.sram_ctrl_multiple_keys.2523520615 |
| /workspace/coverage/default/14.sram_ctrl_partial_access.3646544049 |
| /workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2379433624 |
| /workspace/coverage/default/14.sram_ctrl_ram_cfg.3817885790 |
| /workspace/coverage/default/14.sram_ctrl_regwen.1691283590 |
| /workspace/coverage/default/14.sram_ctrl_smoke.3101109787 |
| /workspace/coverage/default/14.sram_ctrl_stress_all.2461773226 |
| /workspace/coverage/default/14.sram_ctrl_stress_pipeline.1122722024 |
| /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.288278624 |
| /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2608871387 |
| /workspace/coverage/default/15.sram_ctrl_alert_test.3736431246 |
| /workspace/coverage/default/15.sram_ctrl_bijection.849115771 |
| /workspace/coverage/default/15.sram_ctrl_executable.2250935506 |
| /workspace/coverage/default/15.sram_ctrl_max_throughput.5109154 |
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| /workspace/coverage/default/43.sram_ctrl_smoke.226868763 |
| /workspace/coverage/default/43.sram_ctrl_stress_all.312448129 |
| /workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.728318374 |
| /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2766380083 |
| /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.749817748 |
| /workspace/coverage/default/44.sram_ctrl_access_during_key_req.825014384 |
| /workspace/coverage/default/44.sram_ctrl_alert_test.3728216486 |
| /workspace/coverage/default/44.sram_ctrl_bijection.1747101744 |
| /workspace/coverage/default/44.sram_ctrl_executable.3626071725 |
| /workspace/coverage/default/44.sram_ctrl_lc_escalation.907039369 |
| /workspace/coverage/default/44.sram_ctrl_max_throughput.1200819259 |
| /workspace/coverage/default/44.sram_ctrl_mem_partial_access.4123023459 |
| /workspace/coverage/default/44.sram_ctrl_mem_walk.893282792 |
| /workspace/coverage/default/44.sram_ctrl_multiple_keys.1681195962 |
| /workspace/coverage/default/44.sram_ctrl_partial_access.2718273168 |
| /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1640069974 |
| /workspace/coverage/default/44.sram_ctrl_ram_cfg.396279319 |
| /workspace/coverage/default/44.sram_ctrl_regwen.776717041 |
| /workspace/coverage/default/44.sram_ctrl_smoke.694374421 |
| /workspace/coverage/default/44.sram_ctrl_stress_all.3487885952 |
| /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.2972534779 |
| /workspace/coverage/default/44.sram_ctrl_stress_pipeline.177636655 |
| /workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1171296065 |
| /workspace/coverage/default/45.sram_ctrl_access_during_key_req.945319709 |
| /workspace/coverage/default/45.sram_ctrl_alert_test.1956339374 |
| /workspace/coverage/default/45.sram_ctrl_bijection.2350042696 |
| /workspace/coverage/default/45.sram_ctrl_executable.3643581794 |
| /workspace/coverage/default/45.sram_ctrl_lc_escalation.3610463065 |
| /workspace/coverage/default/45.sram_ctrl_max_throughput.1866629005 |
| /workspace/coverage/default/45.sram_ctrl_mem_partial_access.2286977076 |
| /workspace/coverage/default/45.sram_ctrl_mem_walk.3899967176 |
| /workspace/coverage/default/45.sram_ctrl_multiple_keys.491339824 |
| /workspace/coverage/default/45.sram_ctrl_partial_access.3481557209 |
| /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1198310482 |
| /workspace/coverage/default/45.sram_ctrl_ram_cfg.1259576974 |
| /workspace/coverage/default/45.sram_ctrl_regwen.4076510542 |
| /workspace/coverage/default/45.sram_ctrl_smoke.2339810299 |
| /workspace/coverage/default/45.sram_ctrl_stress_all.3107303212 |
| /workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.626677058 |
| /workspace/coverage/default/45.sram_ctrl_stress_pipeline.1874399726 |
| /workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.1888138452 |
| /workspace/coverage/default/46.sram_ctrl_access_during_key_req.2241894477 |
| /workspace/coverage/default/46.sram_ctrl_alert_test.561050750 |
| /workspace/coverage/default/46.sram_ctrl_bijection.807296528 |
| /workspace/coverage/default/46.sram_ctrl_executable.4264665700 |
| /workspace/coverage/default/46.sram_ctrl_lc_escalation.1562068517 |
| /workspace/coverage/default/46.sram_ctrl_max_throughput.3898720339 |
| /workspace/coverage/default/46.sram_ctrl_mem_partial_access.2764763987 |
| /workspace/coverage/default/46.sram_ctrl_mem_walk.927272136 |
| /workspace/coverage/default/46.sram_ctrl_multiple_keys.3705016811 |
| /workspace/coverage/default/46.sram_ctrl_partial_access.1745109380 |
| /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.816629668 |
| /workspace/coverage/default/46.sram_ctrl_ram_cfg.1437848583 |
| /workspace/coverage/default/46.sram_ctrl_regwen.1963972216 |
| /workspace/coverage/default/46.sram_ctrl_smoke.1040430907 |
| /workspace/coverage/default/46.sram_ctrl_stress_all.3609428642 |
| /workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1243453773 |
| /workspace/coverage/default/46.sram_ctrl_stress_pipeline.4032739899 |
| /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1718786911 |
| /workspace/coverage/default/47.sram_ctrl_alert_test.2249838176 |
| /workspace/coverage/default/47.sram_ctrl_bijection.2746002522 |
| /workspace/coverage/default/47.sram_ctrl_executable.386165794 |
| /workspace/coverage/default/47.sram_ctrl_lc_escalation.1512025106 |
| /workspace/coverage/default/47.sram_ctrl_max_throughput.4006173297 |
| /workspace/coverage/default/47.sram_ctrl_mem_partial_access.2105314013 |
| /workspace/coverage/default/47.sram_ctrl_mem_walk.2655674562 |
| /workspace/coverage/default/47.sram_ctrl_multiple_keys.532307511 |
| /workspace/coverage/default/47.sram_ctrl_partial_access.706951748 |
| /workspace/coverage/default/47.sram_ctrl_partial_access_b2b.229958808 |
| /workspace/coverage/default/47.sram_ctrl_ram_cfg.991021575 |
| /workspace/coverage/default/47.sram_ctrl_regwen.3848999169 |
| /workspace/coverage/default/47.sram_ctrl_smoke.3186202168 |
| /workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1907414727 |
| /workspace/coverage/default/47.sram_ctrl_stress_pipeline.2483553094 |
| /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.494545764 |
| /workspace/coverage/default/48.sram_ctrl_access_during_key_req.1928114027 |
| /workspace/coverage/default/48.sram_ctrl_alert_test.1594964174 |
| /workspace/coverage/default/48.sram_ctrl_bijection.613438581 |
| /workspace/coverage/default/48.sram_ctrl_executable.1216185183 |
| /workspace/coverage/default/48.sram_ctrl_lc_escalation.1416724887 |
| /workspace/coverage/default/48.sram_ctrl_max_throughput.4067515010 |
| /workspace/coverage/default/48.sram_ctrl_mem_partial_access.114179018 |
| /workspace/coverage/default/48.sram_ctrl_mem_walk.1249393811 |
| /workspace/coverage/default/48.sram_ctrl_multiple_keys.150370138 |
| /workspace/coverage/default/48.sram_ctrl_partial_access.1867157261 |
| /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4254443420 |
| /workspace/coverage/default/48.sram_ctrl_ram_cfg.1254474551 |
| /workspace/coverage/default/48.sram_ctrl_regwen.966322865 |
| /workspace/coverage/default/48.sram_ctrl_smoke.868458448 |
| /workspace/coverage/default/48.sram_ctrl_stress_all.3302374810 |
| /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1200106302 |
| /workspace/coverage/default/48.sram_ctrl_stress_pipeline.1931841374 |
| /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.1485701814 |
| /workspace/coverage/default/49.sram_ctrl_access_during_key_req.1796490234 |
| /workspace/coverage/default/49.sram_ctrl_alert_test.1178909963 |
| /workspace/coverage/default/49.sram_ctrl_bijection.1216444836 |
| /workspace/coverage/default/49.sram_ctrl_executable.3348596957 |
| /workspace/coverage/default/49.sram_ctrl_lc_escalation.4057759858 |
| /workspace/coverage/default/49.sram_ctrl_max_throughput.2993332278 |
| /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3973684219 |
| /workspace/coverage/default/49.sram_ctrl_mem_walk.678745685 |
| /workspace/coverage/default/49.sram_ctrl_multiple_keys.299669668 |
| /workspace/coverage/default/49.sram_ctrl_partial_access.3583076677 |
| /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.1279235612 |
| /workspace/coverage/default/49.sram_ctrl_ram_cfg.3869262567 |
| /workspace/coverage/default/49.sram_ctrl_regwen.2509964055 |
| /workspace/coverage/default/49.sram_ctrl_smoke.145438214 |
| /workspace/coverage/default/49.sram_ctrl_stress_all.1195663403 |
| /workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.429800526 |
| /workspace/coverage/default/49.sram_ctrl_stress_pipeline.3084194559 |
| /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3625097058 |
| /workspace/coverage/default/5.sram_ctrl_access_during_key_req.606898012 |
| /workspace/coverage/default/5.sram_ctrl_alert_test.516859533 |
| /workspace/coverage/default/5.sram_ctrl_bijection.602330935 |
| /workspace/coverage/default/5.sram_ctrl_executable.2189328334 |
| /workspace/coverage/default/5.sram_ctrl_lc_escalation.2525841207 |
| /workspace/coverage/default/5.sram_ctrl_max_throughput.2720380329 |
| /workspace/coverage/default/5.sram_ctrl_mem_partial_access.768787075 |
| /workspace/coverage/default/5.sram_ctrl_mem_walk.3806280102 |
| /workspace/coverage/default/5.sram_ctrl_multiple_keys.3345362982 |
| /workspace/coverage/default/5.sram_ctrl_partial_access.2383709387 |
| /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.3341740887 |
| /workspace/coverage/default/5.sram_ctrl_ram_cfg.1121634350 |
| /workspace/coverage/default/5.sram_ctrl_regwen.3497107634 |
| /workspace/coverage/default/5.sram_ctrl_smoke.156381192 |
| /workspace/coverage/default/5.sram_ctrl_stress_all.4201078113 |
| /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4162652881 |
| /workspace/coverage/default/5.sram_ctrl_stress_pipeline.3099771818 |
| /workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.793906689 |
| /workspace/coverage/default/6.sram_ctrl_access_during_key_req.3900033207 |
| /workspace/coverage/default/6.sram_ctrl_alert_test.3397703083 |
| /workspace/coverage/default/6.sram_ctrl_bijection.2504788353 |
| /workspace/coverage/default/6.sram_ctrl_executable.332460931 |
| /workspace/coverage/default/6.sram_ctrl_lc_escalation.2897112574 |
| /workspace/coverage/default/6.sram_ctrl_max_throughput.654743760 |
| /workspace/coverage/default/6.sram_ctrl_mem_partial_access.2849514823 |
| /workspace/coverage/default/6.sram_ctrl_mem_walk.791472587 |
| /workspace/coverage/default/6.sram_ctrl_multiple_keys.1284308780 |
| /workspace/coverage/default/6.sram_ctrl_partial_access.1774406820 |
| /workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3363680939 |
| /workspace/coverage/default/6.sram_ctrl_ram_cfg.2653460324 |
| /workspace/coverage/default/6.sram_ctrl_regwen.2290147711 |
| /workspace/coverage/default/6.sram_ctrl_smoke.2435107385 |
| /workspace/coverage/default/6.sram_ctrl_stress_all.519286672 |
| /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4070789862 |
| /workspace/coverage/default/6.sram_ctrl_stress_pipeline.397008594 |
| /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3271330218 |
| /workspace/coverage/default/7.sram_ctrl_access_during_key_req.465149705 |
| /workspace/coverage/default/7.sram_ctrl_alert_test.370049338 |
| /workspace/coverage/default/7.sram_ctrl_bijection.1344561538 |
| /workspace/coverage/default/7.sram_ctrl_lc_escalation.658463049 |
| /workspace/coverage/default/7.sram_ctrl_max_throughput.3274895607 |
| /workspace/coverage/default/7.sram_ctrl_mem_partial_access.131117634 |
| /workspace/coverage/default/7.sram_ctrl_mem_walk.2493005341 |
| /workspace/coverage/default/7.sram_ctrl_multiple_keys.1841446307 |
| /workspace/coverage/default/7.sram_ctrl_partial_access.3539266528 |
| /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1089997231 |
| /workspace/coverage/default/7.sram_ctrl_ram_cfg.1819160796 |
| /workspace/coverage/default/7.sram_ctrl_regwen.4087061407 |
| /workspace/coverage/default/7.sram_ctrl_smoke.1361383882 |
| /workspace/coverage/default/7.sram_ctrl_stress_all.3071766856 |
| /workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.4101376607 |
| /workspace/coverage/default/7.sram_ctrl_stress_pipeline.614188120 |
| /workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2078731676 |
| /workspace/coverage/default/8.sram_ctrl_access_during_key_req.456840722 |
| /workspace/coverage/default/8.sram_ctrl_alert_test.1778205319 |
| /workspace/coverage/default/8.sram_ctrl_bijection.204772653 |
| /workspace/coverage/default/8.sram_ctrl_executable.4237108957 |
| /workspace/coverage/default/8.sram_ctrl_lc_escalation.921821719 |
| /workspace/coverage/default/8.sram_ctrl_max_throughput.1497780401 |
| /workspace/coverage/default/8.sram_ctrl_mem_partial_access.1616456198 |
| /workspace/coverage/default/8.sram_ctrl_mem_walk.698546793 |
| /workspace/coverage/default/8.sram_ctrl_multiple_keys.1678208034 |
| /workspace/coverage/default/8.sram_ctrl_partial_access.315866603 |
| /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2564235513 |
| /workspace/coverage/default/8.sram_ctrl_ram_cfg.2052477851 |
| /workspace/coverage/default/8.sram_ctrl_regwen.2074504925 |
| /workspace/coverage/default/8.sram_ctrl_smoke.2286107671 |
| /workspace/coverage/default/8.sram_ctrl_stress_all.1698371897 |
| /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2699106031 |
| /workspace/coverage/default/8.sram_ctrl_stress_pipeline.1306805961 |
| /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.888617713 |
| /workspace/coverage/default/9.sram_ctrl_access_during_key_req.2961860712 |
| /workspace/coverage/default/9.sram_ctrl_alert_test.1146861844 |
| /workspace/coverage/default/9.sram_ctrl_bijection.1326216145 |
| /workspace/coverage/default/9.sram_ctrl_executable.2443253027 |
| /workspace/coverage/default/9.sram_ctrl_lc_escalation.50012588 |
| /workspace/coverage/default/9.sram_ctrl_max_throughput.3332328314 |
| /workspace/coverage/default/9.sram_ctrl_mem_partial_access.2894148927 |
| /workspace/coverage/default/9.sram_ctrl_mem_walk.143947638 |
| /workspace/coverage/default/9.sram_ctrl_multiple_keys.2465233381 |
| /workspace/coverage/default/9.sram_ctrl_partial_access.3199961618 |
| /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.656506641 |
| /workspace/coverage/default/9.sram_ctrl_ram_cfg.1414526071 |
| /workspace/coverage/default/9.sram_ctrl_regwen.760404466 |
| /workspace/coverage/default/9.sram_ctrl_smoke.191987693 |
| /workspace/coverage/default/9.sram_ctrl_stress_all.3656704951 |
| /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.544259481 |
| /workspace/coverage/default/9.sram_ctrl_stress_pipeline.3986367004 |
| /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1320236591 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.177636655 |
|
|
Apr 04 12:39:06 PM PDT 24 |
Apr 04 12:42:05 PM PDT 24 |
7717132021 ps |
| T2 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2849514823 |
|
|
Apr 04 12:36:08 PM PDT 24 |
Apr 04 12:36:11 PM PDT 24 |
48510858 ps |
| T3 |
/workspace/coverage/default/7.sram_ctrl_executable.1877213281 |
|
|
Apr 04 12:36:04 PM PDT 24 |
Apr 04 01:11:57 PM PDT 24 |
18150069671 ps |
| T9 |
/workspace/coverage/default/25.sram_ctrl_bijection.2681778037 |
|
|
Apr 04 12:37:14 PM PDT 24 |
Apr 04 12:38:21 PM PDT 24 |
6383745320 ps |
| T10 |
/workspace/coverage/default/18.sram_ctrl_executable.1871957291 |
|
|
Apr 04 12:36:42 PM PDT 24 |
Apr 04 12:50:18 PM PDT 24 |
1818041222 ps |
| T11 |
/workspace/coverage/default/32.sram_ctrl_alert_test.114500021 |
|
|
Apr 04 12:37:58 PM PDT 24 |
Apr 04 12:37:59 PM PDT 24 |
16254574 ps |
| T4 |
/workspace/coverage/default/1.sram_ctrl_stress_all.3907212805 |
|
|
Apr 04 12:35:54 PM PDT 24 |
Apr 04 01:03:39 PM PDT 24 |
80695753815 ps |
| T12 |
/workspace/coverage/default/40.sram_ctrl_alert_test.3949035946 |
|
|
Apr 04 12:38:45 PM PDT 24 |
Apr 04 12:38:46 PM PDT 24 |
14813553 ps |
| T5 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.571645667 |
|
|
Apr 04 12:36:30 PM PDT 24 |
Apr 04 12:36:37 PM PDT 24 |
405238133 ps |
| T13 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.600595745 |
|
|
Apr 04 12:36:34 PM PDT 24 |
Apr 04 12:37:10 PM PDT 24 |
191467468 ps |
| T15 |
/workspace/coverage/default/28.sram_ctrl_partial_access.2467354387 |
|
|
Apr 04 12:37:25 PM PDT 24 |
Apr 04 12:38:15 PM PDT 24 |
434761547 ps |
| T18 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.1241749510 |
|
|
Apr 04 12:36:42 PM PDT 24 |
Apr 04 12:48:12 PM PDT 24 |
5211503216 ps |
| T8 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.1645684417 |
|
|
Apr 04 12:35:55 PM PDT 24 |
Apr 04 12:35:58 PM PDT 24 |
171731854 ps |
| T34 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.181820404 |
|
|
Apr 04 12:38:48 PM PDT 24 |
Apr 04 12:39:30 PM PDT 24 |
111427852 ps |
| T29 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3869262567 |
|
|
Apr 04 12:39:35 PM PDT 24 |
Apr 04 12:39:36 PM PDT 24 |
81998115 ps |
| T6 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.310241037 |
|
|
Apr 04 12:38:02 PM PDT 24 |
Apr 04 12:38:07 PM PDT 24 |
1115034996 ps |
| T19 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.3681642741 |
|
|
Apr 04 12:39:21 PM PDT 24 |
Apr 04 01:08:09 PM PDT 24 |
14708644341 ps |
| T20 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.3123106323 |
|
|
Apr 04 12:38:22 PM PDT 24 |
Apr 04 12:41:39 PM PDT 24 |
1155919351 ps |
| T7 |
/workspace/coverage/default/36.sram_ctrl_lc_escalation.4019373266 |
|
|
Apr 04 12:38:10 PM PDT 24 |
Apr 04 12:38:19 PM PDT 24 |
926746821 ps |
| T35 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.1722367549 |
|
|
Apr 04 12:37:36 PM PDT 24 |
Apr 04 12:37:46 PM PDT 24 |
1821780289 ps |
| T36 |
/workspace/coverage/default/32.sram_ctrl_executable.1248874228 |
|
|
Apr 04 12:38:09 PM PDT 24 |
Apr 04 01:05:16 PM PDT 24 |
18218709591 ps |
| T37 |
/workspace/coverage/default/22.sram_ctrl_multiple_keys.3474178269 |
|
|
Apr 04 12:36:57 PM PDT 24 |
Apr 04 12:42:35 PM PDT 24 |
3714650202 ps |
| T54 |
/workspace/coverage/default/0.sram_ctrl_regwen.4014631864 |
|
|
Apr 04 12:35:53 PM PDT 24 |
Apr 04 12:42:36 PM PDT 24 |
7733492468 ps |
| T24 |
/workspace/coverage/default/24.sram_ctrl_regwen.25981584 |
|
|
Apr 04 12:37:10 PM PDT 24 |
Apr 04 12:41:35 PM PDT 24 |
4381025292 ps |
| T67 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.3250073338 |
|
|
Apr 04 12:38:10 PM PDT 24 |
Apr 04 12:38:14 PM PDT 24 |
341324165 ps |
| T133 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.654743760 |
|
|
Apr 04 12:36:41 PM PDT 24 |
Apr 04 12:36:43 PM PDT 24 |
239885953 ps |
| T17 |
/workspace/coverage/default/9.sram_ctrl_smoke.191987693 |
|
|
Apr 04 12:36:12 PM PDT 24 |
Apr 04 12:36:29 PM PDT 24 |
3367272970 ps |
| T134 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.494545764 |
|
|
Apr 04 12:39:22 PM PDT 24 |
Apr 04 12:40:49 PM PDT 24 |
1706403164 ps |
| T68 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.21744109 |
|
|
Apr 04 12:37:34 PM PDT 24 |
Apr 04 12:45:50 PM PDT 24 |
144617701183 ps |
| T128 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3625097058 |
|
|
Apr 04 12:39:27 PM PDT 24 |
Apr 04 12:40:06 PM PDT 24 |
108596557 ps |
| T92 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.769069495 |
|
|
Apr 04 12:38:28 PM PDT 24 |
Apr 04 12:45:30 PM PDT 24 |
290734229982 ps |
| T14 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3654617802 |
|
|
Apr 04 12:37:19 PM PDT 24 |
Apr 04 12:40:46 PM PDT 24 |
6358036377 ps |
| T45 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.1678208034 |
|
|
Apr 04 12:36:18 PM PDT 24 |
Apr 04 01:02:22 PM PDT 24 |
19856113606 ps |
| T46 |
/workspace/coverage/default/32.sram_ctrl_stress_all.1240085822 |
|
|
Apr 04 12:37:56 PM PDT 24 |
Apr 04 12:43:54 PM PDT 24 |
897229259 ps |
| T47 |
/workspace/coverage/default/46.sram_ctrl_smoke.1040430907 |
|
|
Apr 04 12:39:12 PM PDT 24 |
Apr 04 12:39:25 PM PDT 24 |
212041000 ps |
| T48 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.2304833032 |
|
|
Apr 04 12:38:09 PM PDT 24 |
Apr 04 12:40:23 PM PDT 24 |
1160569476 ps |
| T49 |
/workspace/coverage/default/33.sram_ctrl_smoke.570892736 |
|
|
Apr 04 12:37:54 PM PDT 24 |
Apr 04 12:38:06 PM PDT 24 |
557372921 ps |
| T50 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.763623714 |
|
|
Apr 04 12:38:29 PM PDT 24 |
Apr 04 12:46:33 PM PDT 24 |
19837749600 ps |
| T51 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.4092158812 |
|
|
Apr 04 12:38:44 PM PDT 24 |
Apr 04 12:42:25 PM PDT 24 |
3168034284 ps |
| T52 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.3986367004 |
|
|
Apr 04 12:36:04 PM PDT 24 |
Apr 04 12:39:41 PM PDT 24 |
2324895324 ps |
| T53 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.1865948819 |
|
|
Apr 04 12:38:11 PM PDT 24 |
Apr 04 12:43:27 PM PDT 24 |
32421100122 ps |
| T135 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2078731676 |
|
|
Apr 04 12:36:06 PM PDT 24 |
Apr 04 12:36:44 PM PDT 24 |
390560280 ps |
| T93 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.2483553094 |
|
|
Apr 04 12:39:21 PM PDT 24 |
Apr 04 12:43:42 PM PDT 24 |
5537518888 ps |
| T136 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.1162651449 |
|
|
Apr 04 12:38:08 PM PDT 24 |
Apr 04 12:38:14 PM PDT 24 |
339081389 ps |
| T21 |
/workspace/coverage/default/1.sram_ctrl_alert_test.178832001 |
|
|
Apr 04 12:35:54 PM PDT 24 |
Apr 04 12:35:55 PM PDT 24 |
67135394 ps |
| T74 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2289848368 |
|
|
Apr 04 12:37:09 PM PDT 24 |
Apr 04 12:37:14 PM PDT 24 |
153223728 ps |
| T16 |
/workspace/coverage/default/23.sram_ctrl_stress_all.798306708 |
|
|
Apr 04 12:37:18 PM PDT 24 |
Apr 04 01:41:53 PM PDT 24 |
213151677266 ps |
| T75 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.882904690 |
|
|
Apr 04 12:38:17 PM PDT 24 |
Apr 04 12:52:04 PM PDT 24 |
3593337048 ps |
| T132 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2214262961 |
|
|
Apr 04 12:35:58 PM PDT 24 |
Apr 04 12:36:58 PM PDT 24 |
156667798 ps |
| T25 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1621888840 |
|
|
Apr 04 12:38:13 PM PDT 24 |
Apr 04 12:53:51 PM PDT 24 |
2042394601 ps |
| T30 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.3001729163 |
|
|
Apr 04 12:37:11 PM PDT 24 |
Apr 04 12:37:12 PM PDT 24 |
86026398 ps |
| T119 |
/workspace/coverage/default/8.sram_ctrl_executable.4237108957 |
|
|
Apr 04 12:36:04 PM PDT 24 |
Apr 04 12:45:54 PM PDT 24 |
20317789794 ps |
| T129 |
/workspace/coverage/default/31.sram_ctrl_alert_test.623829673 |
|
|
Apr 04 12:37:42 PM PDT 24 |
Apr 04 12:37:42 PM PDT 24 |
22512603 ps |
| T137 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3482921176 |
|
|
Apr 04 12:37:42 PM PDT 24 |
Apr 04 12:37:42 PM PDT 24 |
30408383 ps |
| T138 |
/workspace/coverage/default/34.sram_ctrl_alert_test.294772072 |
|
|
Apr 04 12:38:03 PM PDT 24 |
Apr 04 12:38:04 PM PDT 24 |
31269156 ps |
| T130 |
/workspace/coverage/default/23.sram_ctrl_bijection.1865427678 |
|
|
Apr 04 12:37:07 PM PDT 24 |
Apr 04 12:38:05 PM PDT 24 |
40813237919 ps |
| T55 |
/workspace/coverage/default/16.sram_ctrl_stress_all.2717588201 |
|
|
Apr 04 12:36:31 PM PDT 24 |
Apr 04 01:05:39 PM PDT 24 |
21449708748 ps |
| T56 |
/workspace/coverage/default/32.sram_ctrl_regwen.3705351343 |
|
|
Apr 04 12:37:51 PM PDT 24 |
Apr 04 12:47:12 PM PDT 24 |
1888795695 ps |
| T28 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.1200106302 |
|
|
Apr 04 12:40:56 PM PDT 24 |
Apr 04 12:46:15 PM PDT 24 |
1053866701 ps |
| T139 |
/workspace/coverage/default/6.sram_ctrl_executable.332460931 |
|
|
Apr 04 12:36:06 PM PDT 24 |
Apr 04 12:38:49 PM PDT 24 |
856010071 ps |
| T126 |
/workspace/coverage/default/37.sram_ctrl_partial_access.559687020 |
|
|
Apr 04 12:38:18 PM PDT 24 |
Apr 04 12:39:03 PM PDT 24 |
703257946 ps |
| T94 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1905377058 |
|
|
Apr 04 12:35:58 PM PDT 24 |
Apr 04 12:42:18 PM PDT 24 |
83125048841 ps |
| T121 |
/workspace/coverage/default/13.sram_ctrl_regwen.1005071427 |
|
|
Apr 04 12:36:24 PM PDT 24 |
Apr 04 12:40:56 PM PDT 24 |
3158915527 ps |
| T26 |
/workspace/coverage/default/9.sram_ctrl_lc_escalation.50012588 |
|
|
Apr 04 12:36:03 PM PDT 24 |
Apr 04 12:36:12 PM PDT 24 |
2364518613 ps |
| T140 |
/workspace/coverage/default/44.sram_ctrl_alert_test.3728216486 |
|
|
Apr 04 12:39:15 PM PDT 24 |
Apr 04 12:39:16 PM PDT 24 |
35856145 ps |
| T31 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.609816485 |
|
|
Apr 04 12:38:17 PM PDT 24 |
Apr 04 12:38:18 PM PDT 24 |
50150470 ps |
| T141 |
/workspace/coverage/default/49.sram_ctrl_smoke.145438214 |
|
|
Apr 04 12:39:27 PM PDT 24 |
Apr 04 12:39:30 PM PDT 24 |
216291108 ps |
| T142 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.1992308862 |
|
|
Apr 04 12:38:46 PM PDT 24 |
Apr 04 12:38:47 PM PDT 24 |
209409653 ps |
| T143 |
/workspace/coverage/default/37.sram_ctrl_smoke.2077778939 |
|
|
Apr 04 12:38:18 PM PDT 24 |
Apr 04 12:38:20 PM PDT 24 |
562753828 ps |
| T131 |
/workspace/coverage/default/15.sram_ctrl_bijection.849115771 |
|
|
Apr 04 12:36:41 PM PDT 24 |
Apr 04 12:37:30 PM PDT 24 |
1623036913 ps |
| T144 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.1893344214 |
|
|
Apr 04 12:37:38 PM PDT 24 |
Apr 04 12:40:07 PM PDT 24 |
3788173761 ps |
| T76 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2542322028 |
|
|
Apr 04 12:37:07 PM PDT 24 |
Apr 04 12:57:35 PM PDT 24 |
3126157514 ps |
| T145 |
/workspace/coverage/default/36.sram_ctrl_alert_test.1500057490 |
|
|
Apr 04 12:38:48 PM PDT 24 |
Apr 04 12:38:49 PM PDT 24 |
11357676 ps |
| T77 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.1570513251 |
|
|
Apr 04 12:36:53 PM PDT 24 |
Apr 04 12:45:15 PM PDT 24 |
1894175432 ps |
| T146 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.3145700897 |
|
|
Apr 04 12:36:28 PM PDT 24 |
Apr 04 12:36:35 PM PDT 24 |
1423390619 ps |
| T38 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1907414727 |
|
|
Apr 04 12:39:29 PM PDT 24 |
Apr 04 12:44:07 PM PDT 24 |
539964469 ps |
| T147 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.1497780401 |
|
|
Apr 04 12:36:32 PM PDT 24 |
Apr 04 12:37:13 PM PDT 24 |
367365296 ps |
| T78 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.4205355209 |
|
|
Apr 04 12:38:10 PM PDT 24 |
Apr 04 12:38:13 PM PDT 24 |
321952983 ps |
| T148 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.3647715068 |
|
|
Apr 04 12:37:25 PM PDT 24 |
Apr 04 12:42:16 PM PDT 24 |
3260631782 ps |
| T149 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.2465233381 |
|
|
Apr 04 12:36:22 PM PDT 24 |
Apr 04 12:57:16 PM PDT 24 |
3950212787 ps |
| T150 |
/workspace/coverage/default/48.sram_ctrl_executable.1216185183 |
|
|
Apr 04 12:39:31 PM PDT 24 |
Apr 04 01:05:45 PM PDT 24 |
2657413110 ps |
| T151 |
/workspace/coverage/default/2.sram_ctrl_regwen.2168786214 |
|
|
Apr 04 12:35:51 PM PDT 24 |
Apr 04 01:00:47 PM PDT 24 |
23584037439 ps |
| T86 |
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2414802768 |
|
|
Apr 04 12:36:41 PM PDT 24 |
Apr 04 12:36:45 PM PDT 24 |
148788399 ps |
| T152 |
/workspace/coverage/default/5.sram_ctrl_smoke.156381192 |
|
|
Apr 04 12:36:00 PM PDT 24 |
Apr 04 12:36:04 PM PDT 24 |
224662323 ps |
| T122 |
/workspace/coverage/default/15.sram_ctrl_executable.2250935506 |
|
|
Apr 04 12:36:36 PM PDT 24 |
Apr 04 12:52:39 PM PDT 24 |
31670765691 ps |
| T153 |
/workspace/coverage/default/45.sram_ctrl_mem_walk.3899967176 |
|
|
Apr 04 12:39:12 PM PDT 24 |
Apr 04 12:39:23 PM PDT 24 |
678722915 ps |
| T27 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.3087126774 |
|
|
Apr 04 12:38:35 PM PDT 24 |
Apr 04 12:38:39 PM PDT 24 |
447458141 ps |
| T154 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.2950370976 |
|
|
Apr 04 12:36:57 PM PDT 24 |
Apr 04 12:36:59 PM PDT 24 |
29776899 ps |
| T155 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.361862085 |
|
|
Apr 04 12:36:40 PM PDT 24 |
Apr 04 12:38:24 PM PDT 24 |
2764680556 ps |
| T156 |
/workspace/coverage/default/48.sram_ctrl_bijection.613438581 |
|
|
Apr 04 12:39:29 PM PDT 24 |
Apr 04 12:39:58 PM PDT 24 |
450669983 ps |
| T157 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.3399406614 |
|
|
Apr 04 12:36:17 PM PDT 24 |
Apr 04 12:40:10 PM PDT 24 |
17807033592 ps |
| T158 |
/workspace/coverage/default/29.sram_ctrl_partial_access.1348725300 |
|
|
Apr 04 12:37:33 PM PDT 24 |
Apr 04 12:38:24 PM PDT 24 |
324620802 ps |
| T159 |
/workspace/coverage/default/14.sram_ctrl_stress_all.2461773226 |
|
|
Apr 04 12:36:33 PM PDT 24 |
Apr 04 12:53:04 PM PDT 24 |
15346322504 ps |
| T160 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.3895233826 |
|
|
Apr 04 12:35:59 PM PDT 24 |
Apr 04 12:37:44 PM PDT 24 |
925951460 ps |
| T39 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.2347061988 |
|
|
Apr 04 12:37:26 PM PDT 24 |
Apr 04 12:37:51 PM PDT 24 |
3905176637 ps |
| T161 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2379433624 |
|
|
Apr 04 12:36:52 PM PDT 24 |
Apr 04 12:41:03 PM PDT 24 |
3584974607 ps |
| T162 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.182521401 |
|
|
Apr 04 12:36:34 PM PDT 24 |
Apr 04 12:47:56 PM PDT 24 |
5479641161 ps |
| T163 |
/workspace/coverage/default/42.sram_ctrl_smoke.2342964693 |
|
|
Apr 04 12:38:45 PM PDT 24 |
Apr 04 12:38:52 PM PDT 24 |
347782789 ps |
| T164 |
/workspace/coverage/default/24.sram_ctrl_partial_access_b2b.1927191769 |
|
|
Apr 04 12:36:59 PM PDT 24 |
Apr 04 12:41:25 PM PDT 24 |
3504993080 ps |
| T165 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2052477851 |
|
|
Apr 04 12:36:05 PM PDT 24 |
Apr 04 12:36:05 PM PDT 24 |
85069189 ps |
| T40 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2715308592 |
|
|
Apr 04 12:36:45 PM PDT 24 |
Apr 04 12:37:33 PM PDT 24 |
3846502794 ps |
| T166 |
/workspace/coverage/default/1.sram_ctrl_regwen.3775108576 |
|
|
Apr 04 12:35:50 PM PDT 24 |
Apr 04 12:39:11 PM PDT 24 |
10419837330 ps |
| T167 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1306805961 |
|
|
Apr 04 12:36:05 PM PDT 24 |
Apr 04 12:39:30 PM PDT 24 |
8797390010 ps |
| T168 |
/workspace/coverage/default/36.sram_ctrl_smoke.1874233888 |
|
|
Apr 04 12:38:09 PM PDT 24 |
Apr 04 12:38:27 PM PDT 24 |
93580250 ps |
| T169 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3973684219 |
|
|
Apr 04 12:39:36 PM PDT 24 |
Apr 04 12:39:42 PM PDT 24 |
168793667 ps |
| T123 |
/workspace/coverage/default/25.sram_ctrl_executable.4089530547 |
|
|
Apr 04 12:37:14 PM PDT 24 |
Apr 04 12:46:16 PM PDT 24 |
26851038800 ps |
| T41 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.4130287182 |
|
|
Apr 04 12:36:40 PM PDT 24 |
Apr 04 12:41:56 PM PDT 24 |
1504696857 ps |
| T170 |
/workspace/coverage/default/17.sram_ctrl_smoke.3406537641 |
|
|
Apr 04 12:36:32 PM PDT 24 |
Apr 04 12:36:41 PM PDT 24 |
2485735248 ps |
| T171 |
/workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.2346735787 |
|
|
Apr 04 12:37:55 PM PDT 24 |
Apr 04 12:39:14 PM PDT 24 |
124182621 ps |
| T172 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.606898012 |
|
|
Apr 04 12:35:59 PM PDT 24 |
Apr 04 12:52:14 PM PDT 24 |
1715855006 ps |
| T173 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.204241919 |
|
|
Apr 04 12:38:29 PM PDT 24 |
Apr 04 12:39:11 PM PDT 24 |
365111306 ps |
| T124 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.2740192665 |
|
|
Apr 04 12:37:53 PM PDT 24 |
Apr 04 12:41:21 PM PDT 24 |
9569652514 ps |
| T174 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2515365067 |
|
|
Apr 04 12:36:47 PM PDT 24 |
Apr 04 12:37:52 PM PDT 24 |
623047459 ps |
| T175 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.4006173297 |
|
|
Apr 04 12:39:19 PM PDT 24 |
Apr 04 12:39:33 PM PDT 24 |
73938663 ps |
| T127 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.1201466060 |
|
|
Apr 04 12:38:45 PM PDT 24 |
Apr 04 12:57:40 PM PDT 24 |
59647069084 ps |
| T176 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3610463065 |
|
|
Apr 04 12:39:14 PM PDT 24 |
Apr 04 12:39:18 PM PDT 24 |
311396548 ps |
| T177 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.2612184576 |
|
|
Apr 04 12:38:30 PM PDT 24 |
Apr 04 12:43:10 PM PDT 24 |
16938438216 ps |
| T178 |
/workspace/coverage/default/4.sram_ctrl_smoke.1805871295 |
|
|
Apr 04 12:35:58 PM PDT 24 |
Apr 04 12:36:02 PM PDT 24 |
141308756 ps |
| T179 |
/workspace/coverage/default/48.sram_ctrl_stress_all.3302374810 |
|
|
Apr 04 12:39:30 PM PDT 24 |
Apr 04 01:29:37 PM PDT 24 |
11054578569 ps |
| T180 |
/workspace/coverage/default/41.sram_ctrl_smoke.4230921617 |
|
|
Apr 04 12:38:42 PM PDT 24 |
Apr 04 12:41:03 PM PDT 24 |
1425814252 ps |
| T120 |
/workspace/coverage/default/39.sram_ctrl_executable.3421372729 |
|
|
Apr 04 12:38:38 PM PDT 24 |
Apr 04 12:46:16 PM PDT 24 |
8283601219 ps |
| T181 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3209128642 |
|
|
Apr 04 12:36:53 PM PDT 24 |
Apr 04 12:37:35 PM PDT 24 |
115806386 ps |
| T182 |
/workspace/coverage/default/0.sram_ctrl_executable.966997232 |
|
|
Apr 04 12:35:48 PM PDT 24 |
Apr 04 12:46:22 PM PDT 24 |
11323748394 ps |
| T183 |
/workspace/coverage/default/23.sram_ctrl_alert_test.2021574858 |
|
|
Apr 04 12:37:02 PM PDT 24 |
Apr 04 12:37:03 PM PDT 24 |
30806706 ps |
| T184 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.664941931 |
|
|
Apr 04 12:36:41 PM PDT 24 |
Apr 04 12:36:51 PM PDT 24 |
63609935 ps |
| T185 |
/workspace/coverage/default/37.sram_ctrl_stress_all.1491318405 |
|
|
Apr 04 12:38:18 PM PDT 24 |
Apr 04 01:20:54 PM PDT 24 |
7085230570 ps |
| T186 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.2348957445 |
|
|
Apr 04 12:37:01 PM PDT 24 |
Apr 04 12:40:53 PM PDT 24 |
2590939815 ps |
| T187 |
/workspace/coverage/default/30.sram_ctrl_partial_access.3844048412 |
|
|
Apr 04 12:37:34 PM PDT 24 |
Apr 04 12:39:32 PM PDT 24 |
1171077131 ps |
| T188 |
/workspace/coverage/default/4.sram_ctrl_mem_partial_access.3511314552 |
|
|
Apr 04 12:36:02 PM PDT 24 |
Apr 04 12:36:07 PM PDT 24 |
307978393 ps |
| T189 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.243758577 |
|
|
Apr 04 12:37:44 PM PDT 24 |
Apr 04 12:39:45 PM PDT 24 |
147557844 ps |
| T190 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3084194559 |
|
|
Apr 04 12:39:28 PM PDT 24 |
Apr 04 12:44:46 PM PDT 24 |
46939876763 ps |
| T191 |
/workspace/coverage/default/22.sram_ctrl_partial_access.1340798661 |
|
|
Apr 04 12:36:53 PM PDT 24 |
Apr 04 12:36:55 PM PDT 24 |
231900778 ps |
| T192 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3519366426 |
|
|
Apr 04 12:36:41 PM PDT 24 |
Apr 04 12:40:09 PM PDT 24 |
2552092186 ps |
| T193 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2655674562 |
|
|
Apr 04 12:39:28 PM PDT 24 |
Apr 04 12:39:35 PM PDT 24 |
526126807 ps |
| T194 |
/workspace/coverage/default/22.sram_ctrl_bijection.1140558304 |
|
|
Apr 04 12:36:54 PM PDT 24 |
Apr 04 12:37:42 PM PDT 24 |
21698562766 ps |
| T195 |
/workspace/coverage/default/2.sram_ctrl_alert_test.2724681056 |
|
|
Apr 04 12:35:54 PM PDT 24 |
Apr 04 12:35:54 PM PDT 24 |
41475212 ps |
| T196 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.3291061091 |
|
|
Apr 04 12:36:34 PM PDT 24 |
Apr 04 12:41:30 PM PDT 24 |
17509370744 ps |
| T197 |
/workspace/coverage/default/3.sram_ctrl_alert_test.1202748035 |
|
|
Apr 04 12:36:04 PM PDT 24 |
Apr 04 12:36:05 PM PDT 24 |
25471198 ps |
| T198 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.4118537924 |
|
|
Apr 04 12:37:51 PM PDT 24 |
Apr 04 12:43:09 PM PDT 24 |
13137293682 ps |
| T199 |
/workspace/coverage/default/16.sram_ctrl_partial_access.2915663709 |
|
|
Apr 04 12:36:34 PM PDT 24 |
Apr 04 12:36:36 PM PDT 24 |
47364628 ps |
| T200 |
/workspace/coverage/default/19.sram_ctrl_partial_access.3288429682 |
|
|
Apr 04 12:36:41 PM PDT 24 |
Apr 04 12:38:27 PM PDT 24 |
197393669 ps |
| T125 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1198310482 |
|
|
Apr 04 12:39:11 PM PDT 24 |
Apr 04 12:44:54 PM PDT 24 |
14931723194 ps |
| T201 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.2885155761 |
|
|
Apr 04 12:36:24 PM PDT 24 |
Apr 04 12:40:07 PM PDT 24 |
2402721348 ps |
| T42 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.876921844 |
|
|
Apr 04 12:35:49 PM PDT 24 |
Apr 04 12:36:26 PM PDT 24 |
1266388465 ps |
| T202 |
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.1718786911 |
|
|
Apr 04 12:39:20 PM PDT 24 |
Apr 04 12:39:41 PM PDT 24 |
172225795 ps |
| T203 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.288614622 |
|
|
Apr 04 12:36:23 PM PDT 24 |
Apr 04 12:39:19 PM PDT 24 |
7757683069 ps |
| T43 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2026883554 |
|
|
Apr 04 12:38:20 PM PDT 24 |
Apr 04 12:38:27 PM PDT 24 |
431902166 ps |
| T204 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.390861467 |
|
|
Apr 04 12:38:56 PM PDT 24 |
Apr 04 12:38:57 PM PDT 24 |
31080049 ps |
| T205 |
/workspace/coverage/default/46.sram_ctrl_regwen.1963972216 |
|
|
Apr 04 12:39:21 PM PDT 24 |
Apr 04 12:50:13 PM PDT 24 |
38240864081 ps |
| T206 |
/workspace/coverage/default/47.sram_ctrl_multiple_keys.532307511 |
|
|
Apr 04 12:39:22 PM PDT 24 |
Apr 04 12:41:03 PM PDT 24 |
257824813 ps |
| T207 |
/workspace/coverage/default/17.sram_ctrl_alert_test.234264604 |
|
|
Apr 04 12:36:45 PM PDT 24 |
Apr 04 12:36:46 PM PDT 24 |
12686685 ps |
| T208 |
/workspace/coverage/default/28.sram_ctrl_stress_all.1040331020 |
|
|
Apr 04 12:37:35 PM PDT 24 |
Apr 04 01:05:36 PM PDT 24 |
106547009500 ps |
| T209 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.4067515010 |
|
|
Apr 04 12:39:31 PM PDT 24 |
Apr 04 12:40:12 PM PDT 24 |
99487417 ps |
| T210 |
/workspace/coverage/default/29.sram_ctrl_stress_all.1512163701 |
|
|
Apr 04 12:37:38 PM PDT 24 |
Apr 04 12:48:13 PM PDT 24 |
13529690031 ps |
| T211 |
/workspace/coverage/default/33.sram_ctrl_bijection.3993712445 |
|
|
Apr 04 12:37:53 PM PDT 24 |
Apr 04 12:38:54 PM PDT 24 |
22998183756 ps |
| T212 |
/workspace/coverage/default/29.sram_ctrl_regwen.3780157346 |
|
|
Apr 04 12:37:37 PM PDT 24 |
Apr 04 12:46:59 PM PDT 24 |
33785511730 ps |
| T213 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1449612035 |
|
|
Apr 04 12:36:54 PM PDT 24 |
Apr 04 12:36:56 PM PDT 24 |
109819715 ps |
| T214 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.4105483420 |
|
|
Apr 04 12:37:28 PM PDT 24 |
Apr 04 12:43:08 PM PDT 24 |
49836489460 ps |
| T215 |
/workspace/coverage/default/7.sram_ctrl_stress_all.3071766856 |
|
|
Apr 04 12:36:02 PM PDT 24 |
Apr 04 01:02:32 PM PDT 24 |
31143535276 ps |
| T216 |
/workspace/coverage/default/49.sram_ctrl_partial_access.3583076677 |
|
|
Apr 04 12:39:29 PM PDT 24 |
Apr 04 12:39:43 PM PDT 24 |
278556440 ps |
| T217 |
/workspace/coverage/default/13.sram_ctrl_smoke.1801429995 |
|
|
Apr 04 12:36:21 PM PDT 24 |
Apr 04 12:37:56 PM PDT 24 |
551707293 ps |
| T218 |
/workspace/coverage/default/33.sram_ctrl_ram_cfg.2285981312 |
|
|
Apr 04 12:37:52 PM PDT 24 |
Apr 04 12:37:53 PM PDT 24 |
30937415 ps |
| T219 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.2009655879 |
|
|
Apr 04 12:35:54 PM PDT 24 |
Apr 04 12:35:58 PM PDT 24 |
61285819 ps |
| T220 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.3817885790 |
|
|
Apr 04 12:36:41 PM PDT 24 |
Apr 04 12:36:42 PM PDT 24 |
47524090 ps |
| T221 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.2993332278 |
|
|
Apr 04 12:39:27 PM PDT 24 |
Apr 04 12:39:36 PM PDT 24 |
61900148 ps |
| T222 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.72737017 |
|
|
Apr 04 12:35:57 PM PDT 24 |
Apr 04 12:36:03 PM PDT 24 |
3124658124 ps |
| T223 |
/workspace/coverage/default/25.sram_ctrl_regwen.3379117899 |
|
|
Apr 04 12:37:19 PM PDT 24 |
Apr 04 12:49:07 PM PDT 24 |
8225376024 ps |
| T224 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.2054090118 |
|
|
Apr 04 12:38:42 PM PDT 24 |
Apr 04 12:38:46 PM PDT 24 |
184316074 ps |
| T225 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1121634350 |
|
|
Apr 04 12:36:07 PM PDT 24 |
Apr 04 12:36:08 PM PDT 24 |
28910397 ps |
| T226 |
/workspace/coverage/default/26.sram_ctrl_executable.1079808068 |
|
|
Apr 04 12:37:18 PM PDT 24 |
Apr 04 12:56:54 PM PDT 24 |
10351754476 ps |
| T227 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2897112574 |
|
|
Apr 04 12:36:42 PM PDT 24 |
Apr 04 12:36:49 PM PDT 24 |
1615816268 ps |
| T228 |
/workspace/coverage/default/33.sram_ctrl_executable.1795169469 |
|
|
Apr 04 12:37:54 PM PDT 24 |
Apr 04 01:03:08 PM PDT 24 |
4258572407 ps |
| T229 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1195198621 |
|
|
Apr 04 12:36:47 PM PDT 24 |
Apr 04 12:36:51 PM PDT 24 |
547065396 ps |
| T230 |
/workspace/coverage/default/29.sram_ctrl_smoke.3346223708 |
|
|
Apr 04 12:37:26 PM PDT 24 |
Apr 04 12:37:54 PM PDT 24 |
358836344 ps |
| T231 |
/workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.288278624 |
|
|
Apr 04 12:36:26 PM PDT 24 |
Apr 04 12:36:32 PM PDT 24 |
55019776 ps |
| T232 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2653460324 |
|
|
Apr 04 12:36:00 PM PDT 24 |
Apr 04 12:36:01 PM PDT 24 |
36949840 ps |
| T233 |
/workspace/coverage/default/14.sram_ctrl_partial_access.3646544049 |
|
|
Apr 04 12:36:52 PM PDT 24 |
Apr 04 12:37:01 PM PDT 24 |
708991885 ps |
| T234 |
/workspace/coverage/default/3.sram_ctrl_bijection.2550996584 |
|
|
Apr 04 12:35:49 PM PDT 24 |
Apr 04 12:36:26 PM PDT 24 |
3358069555 ps |
| T235 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2703282264 |
|
|
Apr 04 12:37:27 PM PDT 24 |
Apr 04 12:39:06 PM PDT 24 |
582674517 ps |
| T236 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.1721168950 |
|
|
Apr 04 12:35:55 PM PDT 24 |
Apr 04 12:36:04 PM PDT 24 |
466632799 ps |
| T237 |
/workspace/coverage/default/42.sram_ctrl_partial_access_b2b.2177582725 |
|
|
Apr 04 12:38:54 PM PDT 24 |
Apr 04 12:44:01 PM PDT 24 |
13993608648 ps |
| T238 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2766380083 |
|
|
Apr 04 12:38:57 PM PDT 24 |
Apr 04 12:41:57 PM PDT 24 |
13760771332 ps |
| T239 |
/workspace/coverage/default/13.sram_ctrl_bijection.873903955 |
|
|
Apr 04 12:36:52 PM PDT 24 |
Apr 04 12:37:45 PM PDT 24 |
2535858228 ps |
| T104 |
/workspace/coverage/default/36.sram_ctrl_stress_all.1816481435 |
|
|
Apr 04 12:38:21 PM PDT 24 |
Apr 04 12:51:10 PM PDT 24 |
23096277527 ps |
| T240 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.2493005341 |
|
|
Apr 04 12:36:19 PM PDT 24 |
Apr 04 12:36:24 PM PDT 24 |
560354941 ps |
| T241 |
/workspace/coverage/default/11.sram_ctrl_regwen.2961167706 |
|
|
Apr 04 12:36:45 PM PDT 24 |
Apr 04 12:58:40 PM PDT 24 |
37618944533 ps |
| T242 |
/workspace/coverage/default/27.sram_ctrl_bijection.1698607098 |
|
|
Apr 04 12:37:26 PM PDT 24 |
Apr 04 12:38:38 PM PDT 24 |
11736812734 ps |
| T243 |
/workspace/coverage/default/9.sram_ctrl_alert_test.1146861844 |
|
|
Apr 04 12:36:14 PM PDT 24 |
Apr 04 12:36:14 PM PDT 24 |
105500491 ps |
| T244 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.1843136441 |
|
|
Apr 04 12:37:37 PM PDT 24 |
Apr 04 12:37:41 PM PDT 24 |
69839179 ps |
| T245 |
/workspace/coverage/default/13.sram_ctrl_stress_all.3784733683 |
|
|
Apr 04 12:36:31 PM PDT 24 |
Apr 04 01:20:13 PM PDT 24 |
129187107852 ps |
| T246 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.3857583673 |
|
|
Apr 04 12:39:04 PM PDT 24 |
Apr 04 12:39:07 PM PDT 24 |
106594547 ps |
| T247 |
/workspace/coverage/default/13.sram_ctrl_partial_access.2243611934 |
|
|
Apr 04 12:36:53 PM PDT 24 |
Apr 04 12:37:27 PM PDT 24 |
1077326736 ps |
| T248 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.63375511 |
|
|
Apr 04 12:36:39 PM PDT 24 |
Apr 04 12:43:18 PM PDT 24 |
66220707594 ps |
| T249 |
/workspace/coverage/default/0.sram_ctrl_partial_access.2929754753 |
|
|
Apr 04 12:35:41 PM PDT 24 |
Apr 04 12:35:44 PM PDT 24 |
39493047 ps |
| T250 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.3924891647 |
|
|
Apr 04 12:36:06 PM PDT 24 |
Apr 04 12:38:01 PM PDT 24 |
554122293 ps |
| T251 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.1425872385 |
|
|
Apr 04 12:38:19 PM PDT 24 |
Apr 04 12:41:32 PM PDT 24 |
3942558580 ps |
| T252 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.2602567334 |
|
|
Apr 04 12:37:26 PM PDT 24 |
Apr 04 12:38:02 PM PDT 24 |
95966441 ps |
| T253 |
/workspace/coverage/default/38.sram_ctrl_stress_all.2980537705 |
|
|
Apr 04 12:38:30 PM PDT 24 |
Apr 04 01:24:21 PM PDT 24 |
52903562368 ps |
| T254 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.791472587 |
|
|
Apr 04 12:35:59 PM PDT 24 |
Apr 04 12:36:09 PM PDT 24 |
459722887 ps |
| T255 |
/workspace/coverage/default/38.sram_ctrl_mem_partial_access.1545202173 |
|
|
Apr 04 12:38:29 PM PDT 24 |
Apr 04 12:38:36 PM PDT 24 |
1502405617 ps |
| T256 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.959944372 |
|
|
Apr 04 12:37:25 PM PDT 24 |
Apr 04 12:37:28 PM PDT 24 |
168993689 ps |
| T257 |
/workspace/coverage/default/6.sram_ctrl_regwen.2290147711 |
|
|
Apr 04 12:35:59 PM PDT 24 |
Apr 04 12:43:25 PM PDT 24 |
10329631032 ps |
| T258 |
/workspace/coverage/default/45.sram_ctrl_bijection.2350042696 |
|
|
Apr 04 12:39:12 PM PDT 24 |
Apr 04 12:39:39 PM PDT 24 |
4704483441 ps |
| T259 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1146519540 |
|
|
Apr 04 12:36:27 PM PDT 24 |
Apr 04 12:36:29 PM PDT 24 |
310516639 ps |
| T260 |
/workspace/coverage/default/38.sram_ctrl_max_throughput.4204496469 |
|
|
Apr 04 12:38:30 PM PDT 24 |
Apr 04 12:39:32 PM PDT 24 |
206353407 ps |
| T261 |
/workspace/coverage/default/29.sram_ctrl_bijection.455257691 |
|
|
Apr 04 12:37:32 PM PDT 24 |
Apr 04 12:38:18 PM PDT 24 |
13501026331 ps |
| T262 |
/workspace/coverage/default/21.sram_ctrl_alert_test.3785072904 |
|
|
Apr 04 12:36:59 PM PDT 24 |
Apr 04 12:37:00 PM PDT 24 |
48444840 ps |
| T263 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.1008641455 |
|
|
Apr 04 12:38:30 PM PDT 24 |
Apr 04 12:40:49 PM PDT 24 |
584707258 ps |
| T264 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.4167466944 |
|
|
Apr 04 12:38:46 PM PDT 24 |
Apr 04 12:45:34 PM PDT 24 |
6679620264 ps |
| T265 |
/workspace/coverage/default/7.sram_ctrl_lc_escalation.658463049 |
|
|
Apr 04 12:36:06 PM PDT 24 |
Apr 04 12:36:14 PM PDT 24 |
774324220 ps |
| T266 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2181029194 |
|
|
Apr 04 12:36:14 PM PDT 24 |
Apr 04 12:36:16 PM PDT 24 |
42597312 ps |
| T267 |
/workspace/coverage/default/14.sram_ctrl_smoke.3101109787 |
|
|
Apr 04 12:36:31 PM PDT 24 |
Apr 04 12:36:50 PM PDT 24 |
1123287206 ps |
| T268 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.3405399412 |
|
|
Apr 04 12:37:28 PM PDT 24 |
Apr 04 12:52:41 PM PDT 24 |
6615356160 ps |
| T269 |
/workspace/coverage/default/39.sram_ctrl_bijection.2919289763 |
|
|
Apr 04 12:38:31 PM PDT 24 |
Apr 04 12:39:18 PM PDT 24 |
2895308685 ps |
| T270 |
/workspace/coverage/default/49.sram_ctrl_alert_test.1178909963 |
|
|
Apr 04 12:39:35 PM PDT 24 |
Apr 04 12:39:36 PM PDT 24 |
32788457 ps |
| T271 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.1376454247 |
|
|
Apr 04 12:35:59 PM PDT 24 |
Apr 04 12:36:04 PM PDT 24 |
76622263 ps |
| T272 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.3630037947 |
|
|
Apr 04 12:37:43 PM PDT 24 |
Apr 04 12:41:19 PM PDT 24 |
8919714082 ps |
| T273 |
/workspace/coverage/default/35.sram_ctrl_regwen.2586611250 |
|
|
Apr 04 12:38:11 PM PDT 24 |
Apr 04 12:40:52 PM PDT 24 |
2158941055 ps |
| T274 |
/workspace/coverage/default/13.sram_ctrl_alert_test.1582188003 |
|
|
Apr 04 12:36:27 PM PDT 24 |
Apr 04 12:36:28 PM PDT 24 |
13498144 ps |
| T275 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.3099771818 |
|
|
Apr 04 12:35:57 PM PDT 24 |
Apr 04 12:37:51 PM PDT 24 |
4919797790 ps |
| T276 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.4275545741 |
|
|
Apr 04 12:36:43 PM PDT 24 |
Apr 04 12:36:45 PM PDT 24 |
89431705 ps |
| T277 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1774406820 |
|
|
Apr 04 12:36:01 PM PDT 24 |
Apr 04 12:36:04 PM PDT 24 |
159704674 ps |
| T278 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3271330218 |
|
|
Apr 04 12:35:59 PM PDT 24 |
Apr 04 12:36:02 PM PDT 24 |
46752695 ps |
| T279 |
/workspace/coverage/default/5.sram_ctrl_stress_all.4201078113 |
|
|
Apr 04 12:36:12 PM PDT 24 |
Apr 04 01:16:36 PM PDT 24 |
26176922417 ps |
| T280 |
/workspace/coverage/default/2.sram_ctrl_partial_access.1689827146 |
|
|
Apr 04 12:35:52 PM PDT 24 |
Apr 04 12:35:56 PM PDT 24 |
500903361 ps |
| T281 |
/workspace/coverage/default/45.sram_ctrl_stress_all.3107303212 |
|
|
Apr 04 12:39:17 PM PDT 24 |
Apr 04 12:44:06 PM PDT 24 |
50110696894 ps |
| T282 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.3488649069 |
|
|
Apr 04 12:37:25 PM PDT 24 |
Apr 04 12:39:00 PM PDT 24 |
116711477 ps |
| T283 |
/workspace/coverage/default/2.sram_ctrl_executable.1012693639 |
|
|
Apr 04 12:35:52 PM PDT 24 |
Apr 04 12:43:13 PM PDT 24 |
16249806359 ps |
| T284 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.100239658 |
|
|
Apr 04 12:36:47 PM PDT 24 |
Apr 04 12:43:54 PM PDT 24 |
7764951753 ps |
| T285 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2948268589 |
|
|
Apr 04 12:35:48 PM PDT 24 |
Apr 04 12:35:55 PM PDT 24 |
1287766468 ps |
| T286 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.3143402561 |
|
|
Apr 04 12:38:29 PM PDT 24 |
Apr 04 12:55:29 PM PDT 24 |
13954378427 ps |
| T287 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.4080682806 |
|
|
Apr 04 12:36:54 PM PDT 24 |
Apr 04 12:36:59 PM PDT 24 |
347089081 ps |
| T288 |
/workspace/coverage/default/20.sram_ctrl_lc_escalation.801890158 |
|
|
Apr 04 12:36:45 PM PDT 24 |
Apr 04 12:36:51 PM PDT 24 |
1502068190 ps |
| T289 |
/workspace/coverage/default/0.sram_ctrl_bijection.793991957 |
|
|
Apr 04 12:35:44 PM PDT 24 |
Apr 04 12:36:34 PM PDT 24 |
2995836844 ps |
| T290 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.2014205348 |
|
|
Apr 04 12:38:35 PM PDT 24 |
Apr 04 12:38:41 PM PDT 24 |
508225340 ps |
| T291 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.610232842 |
|
|
Apr 04 12:36:50 PM PDT 24 |
Apr 04 12:36:54 PM PDT 24 |
311240326 ps |
| T292 |
/workspace/coverage/default/41.sram_ctrl_partial_access.4183099227 |
|
|
Apr 04 12:38:45 PM PDT 24 |
Apr 04 12:41:20 PM PDT 24 |
1350910865 ps |
| T293 |
/workspace/coverage/default/26.sram_ctrl_bijection.1953919870 |
|
|
Apr 04 12:37:19 PM PDT 24 |
Apr 04 12:38:18 PM PDT 24 |
46085943491 ps |
| T294 |
/workspace/coverage/default/22.sram_ctrl_stress_all.3566674601 |
|
|
Apr 04 12:37:12 PM PDT 24 |
Apr 04 02:04:34 PM PDT 24 |
61226626517 ps |
| T295 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.4254443420 |
|
|
Apr 04 12:40:56 PM PDT 24 |
Apr 04 12:46:52 PM PDT 24 |
85487637718 ps |
| T296 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.2686152892 |
|
|
Apr 04 12:35:58 PM PDT 24 |
Apr 04 12:35:59 PM PDT 24 |
72294469 ps |
| T297 |
/workspace/coverage/default/47.sram_ctrl_executable.386165794 |
|
|
Apr 04 12:39:20 PM PDT 24 |
Apr 04 12:46:27 PM PDT 24 |
3419730380 ps |
| T298 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.3950508260 |
|
|
Apr 04 12:38:09 PM PDT 24 |
Apr 04 12:38:10 PM PDT 24 |
30671209 ps |
| T299 |
/workspace/coverage/default/15.sram_ctrl_alert_test.3736431246 |
|
|
Apr 04 12:36:49 PM PDT 24 |
Apr 04 12:36:50 PM PDT 24 |
16442090 ps |
| T300 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.1415171266 |
|
|
Apr 04 12:37:50 PM PDT 24 |
Apr 04 12:55:34 PM PDT 24 |
17529447340 ps |
| T301 |
/workspace/coverage/default/35.sram_ctrl_smoke.641747479 |
|
|
Apr 04 12:38:03 PM PDT 24 |
Apr 04 12:38:05 PM PDT 24 |
108084583 ps |
| T302 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.1452346675 |
|
|
Apr 04 12:37:42 PM PDT 24 |
Apr 04 12:56:32 PM PDT 24 |
7661867304 ps |
| T303 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.396279319 |
|
|
Apr 04 12:39:04 PM PDT 24 |
Apr 04 12:39:05 PM PDT 24 |
102944699 ps |
| T304 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.3304636989 |
|
|
Apr 04 12:37:35 PM PDT 24 |
Apr 04 12:54:30 PM PDT 24 |
3016783014 ps |
| T305 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.816629668 |
|
|
Apr 04 12:39:12 PM PDT 24 |
Apr 04 12:42:22 PM PDT 24 |
8551648194 ps |