Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	42538562	1			T1	140645		T2	55		T3	74909
triple_byte_access	2439042	1			T1	2868		T2	141		T3	1483
halfword_access	3660403	1			T1	4156		T2	210		T3	2246
byte_access	4893511	1			T1	5667		T2	376		T3	3047
zero_access	1230357	1			T1	1426		T2	187		T3	752

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27329749

1

T1

77375

T2

366

T3

41202

auto[1]

27432126

1

T1

77387

T2

603

T3

41235

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	21220684	1			T1	70304		T3	37491		T9	22528
auto[0]	triple_byte_access	1217797	1			T1	1450		T2	22		T3	747
auto[0]	halfword_access	1826799	1			T1	2040		T2	49		T3	1074
auto[0]	byte_access	2445479	1			T1	2894		T2	173		T3	1503
auto[0]	zero_access	618990	1			T1	687		T2	122		T3	387
auto[1]	word_access	21317878	1			T1	70341		T2	55		T3	37418
auto[1]	triple_byte_access	1221245	1			T1	1418		T2	119		T3	736
auto[1]	halfword_access	1833604	1			T1	2116		T2	161		T3	1172
auto[1]	byte_access	2448032	1			T1	2773		T2	203		T3	1544
auto[1]	zero_access	611367	1			T1	739		T2	65		T3	365