Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	149638718	1			T2	410590		T3	306340		T4	3878
instr_valid_dis	119554481	1			T2	410590		T3	306340		T4	3878
instr_en	23141093	1			T9	84		T14	211076		T15	51268

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10262952	1			T14	13960		T15	16534		T31	44896
sram_ifetch_valid_disable	118677806	1			T2	410590		T3	306340		T4	3878
sram_ifetch_enable	20697960	1			T9	84		T14	255036		T15	116624

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	149638718	1			T2	410590		T3	306340		T4	3878
hw_debug_en_valid_off	119038762	1			T2	410590		T3	306340		T4	3878
hw_debug_en_on	20326534	1			T14	49824		T15	126508		T31	21082

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	118677806	1			T2	410590		T3	306340		T4	3878
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	106092164	1			T2	410590		T3	306340		T4	3878
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	9920317	1			T15	9908		T23	96576		T24	78028
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4461282	1			T14	13960		T23	25718		T25	78902
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1659660	1			T14	13960		T138	19730		T139	4280
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1895498	1			T23	25718		T25	78902		T139	40362
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3534270	1			T15	16534		T31	21030		T24	24698
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1379770	1			T15	16534		T31	21030		T138	18734
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1648842	1			T24	24698		T140	9334		T46	15780
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8462621	1			T15	59716		T31	52		T23	46000
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3431143	1			T31	52		T138	68084		T45	38428
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3861170	1			T15	9908		T23	46000		T24	47668

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8801548	1			T9	84		T14	211076		T15	41360
lc_exec_en	8329643	1			T14	49824		T15	50258		T23	100956
valid_exec_dis	115435924	1			T2	410590		T3	306340		T4	3878
invalid_exec_dis	30960912	1			T9	84		T14	268996		T15	133158