Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 97.02 100.00 100.00 98.58 99.70 98.52


Total tests in report: 1030
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
82.58 82.58 97.66 97.66 78.02 78.02 84.69 84.69 100.00 100.00 93.10 93.10 94.90 94.90 29.68 29.68 /workspace/coverage/default/45.sram_ctrl_lc_escalation.317543953
88.94 6.36 98.24 0.59 83.93 5.91 86.55 1.86 100.00 0.00 95.40 2.30 96.70 1.80 61.78 32.10 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3911831914
93.18 4.24 98.93 0.68 87.02 3.08 88.27 1.72 100.00 0.00 97.13 1.72 96.70 0.00 84.23 22.45 /workspace/coverage/default/28.sram_ctrl_stress_all.3026756402
95.36 2.18 99.32 0.39 90.62 3.60 98.21 9.94 100.00 0.00 97.13 0.00 96.70 0.00 85.53 1.30 /workspace/coverage/default/40.sram_ctrl_regwen.4029388913
96.40 1.04 99.51 0.20 91.26 0.64 98.43 0.21 100.00 0.00 97.99 0.86 96.70 0.00 90.91 5.38 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3380264017
97.15 0.75 99.71 0.20 93.19 1.93 99.14 0.72 100.00 0.00 98.85 0.86 97.30 0.60 91.84 0.93 /workspace/coverage/default/0.sram_ctrl_sec_cm.3373815335
97.54 0.39 99.71 0.00 93.19 0.00 99.14 0.00 100.00 0.00 98.85 0.00 97.45 0.15 94.43 2.60 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.151788422
97.78 0.24 99.71 0.00 93.19 0.00 99.14 0.00 100.00 0.00 98.85 0.00 97.45 0.00 96.10 1.67 /workspace/coverage/default/42.sram_ctrl_regwen.1593788339
98.00 0.22 99.71 0.00 93.44 0.26 99.14 0.00 100.00 0.00 98.85 0.00 98.35 0.90 96.47 0.37 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.3254637705
98.18 0.18 99.71 0.00 93.44 0.00 99.21 0.07 100.00 0.00 98.85 0.00 99.55 1.20 96.47 0.00 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.432916977
98.29 0.12 99.80 0.10 93.44 0.00 99.93 0.72 100.00 0.00 98.85 0.00 99.55 0.00 96.47 0.00 /workspace/coverage/default/11.sram_ctrl_ram_cfg.3483614254
98.39 0.10 99.80 0.00 93.57 0.13 99.93 0.00 100.00 0.00 98.85 0.00 99.55 0.00 97.03 0.56 /workspace/coverage/default/19.sram_ctrl_executable.2101934830
98.47 0.08 99.80 0.00 93.57 0.00 99.93 0.00 100.00 0.00 98.85 0.00 99.55 0.00 97.59 0.56 /workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2726694831
98.54 0.07 99.80 0.00 93.96 0.39 100.00 0.07 100.00 0.00 98.85 0.00 99.55 0.00 97.59 0.00 /workspace/coverage/default/0.sram_ctrl_alert_test.312484690
98.59 0.06 99.80 0.00 94.22 0.26 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.15 97.59 0.00 /workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2233657077
98.65 0.05 99.80 0.00 94.22 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 97.96 0.37 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1651630347
98.69 0.04 99.80 0.00 94.34 0.13 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 98.14 0.19 /workspace/coverage/default/1.sram_ctrl_lc_escalation.1969853009
98.74 0.04 99.80 0.00 94.47 0.13 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 98.33 0.19 /workspace/coverage/default/3.sram_ctrl_regwen.1550607973
98.76 0.03 99.80 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.00 98.52 0.19 /workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3442952543

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3289960084
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3846432623
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3364282698
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.149070930
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1425868924
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2064475116
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3671424883
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.829384989
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3318063718
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3013599105
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.4040933499
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1804240544
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4147339018
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.75338577
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2833916193
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1658331336
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.296997013
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3823862742
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2225830104
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1708106074
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4165745037
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3674070355
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1109104748
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3621240852
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3146263596
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1915324472
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1163584513
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1919179678
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2207771657
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3338245587
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1361115788
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1779509640
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2936775548
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.1297054649
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3862342086
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.3816143589
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3711792800
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3083810577
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3412920550
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.926620032
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.72475754
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.4078903893
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2161565911
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.4056721470
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.1784771250
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3438678380
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.756826220
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2917384588
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3169683858
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1385202732
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1275775520
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.68520260
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1139907073
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3389929371
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.287676127
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1501279709
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1212670816
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.648145634
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3937390407
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.136155739
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2448794801
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2058561264
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2253152314
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1393628385
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.316733627
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.3708402995
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2428387814
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1517857330
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.339006815
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.521196049
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.4203298934
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1413573478
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3249773717
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.940763117
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.749506139
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2888157688
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1039007388
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3661747414
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3337087159
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4146198921
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3962827125
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1537069377
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.310017441
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1784298357
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1362343381
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3790613330
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.217951938
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.568970329
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1816070551
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.211746591
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2285080249
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.273481402
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1547531200
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2122591923
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.23682528
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1708503088
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.2387546466
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.447798741
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3717787428
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.535180382
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3250448894
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.805041892
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3387122422
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1156441891
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1000244309
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.208378443
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3552891688
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2993469111
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1037243596
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2263437051
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.3653146631
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.862051538
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.162791304
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2681876946
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.2558336020
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2640514260
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4255592935
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1917951025
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.124853927
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3502405308
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1795268888
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3044216364
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.470671118
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.568520253
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1425039672
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.164666054
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.4037896559
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2512399215
/workspace/coverage/default/0.sram_ctrl_bijection.2843544569
/workspace/coverage/default/0.sram_ctrl_executable.3445224996
/workspace/coverage/default/0.sram_ctrl_lc_escalation.1588584554
/workspace/coverage/default/0.sram_ctrl_max_throughput.2436865881
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1967725725
/workspace/coverage/default/0.sram_ctrl_mem_walk.556879372
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1680813483
/workspace/coverage/default/0.sram_ctrl_partial_access.1528334050
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3253344330
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1914402001
/workspace/coverage/default/0.sram_ctrl_regwen.646931405
/workspace/coverage/default/0.sram_ctrl_smoke.540488073
/workspace/coverage/default/0.sram_ctrl_stress_all.2913077229
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1325987641
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2036402911
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2066942051
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.1305043595
/workspace/coverage/default/1.sram_ctrl_alert_test.3842373901
/workspace/coverage/default/1.sram_ctrl_bijection.1412792952
/workspace/coverage/default/1.sram_ctrl_executable.3226090823
/workspace/coverage/default/1.sram_ctrl_max_throughput.3847571723
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.58718301
/workspace/coverage/default/1.sram_ctrl_mem_walk.1030081696
/workspace/coverage/default/1.sram_ctrl_multiple_keys.986251999
/workspace/coverage/default/1.sram_ctrl_partial_access.1797333144
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.1893129765
/workspace/coverage/default/1.sram_ctrl_ram_cfg.2904421429
/workspace/coverage/default/1.sram_ctrl_regwen.1890574009
/workspace/coverage/default/1.sram_ctrl_sec_cm.368683244
/workspace/coverage/default/1.sram_ctrl_smoke.3126326717
/workspace/coverage/default/1.sram_ctrl_stress_all.1138868544
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.1629458963
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.2190621562
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.777429929
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.3251123591
/workspace/coverage/default/10.sram_ctrl_alert_test.230244060
/workspace/coverage/default/10.sram_ctrl_bijection.3845925092
/workspace/coverage/default/10.sram_ctrl_executable.3319839171
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3227104626
/workspace/coverage/default/10.sram_ctrl_max_throughput.1651355330
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.304721791
/workspace/coverage/default/10.sram_ctrl_mem_walk.4131591958
/workspace/coverage/default/10.sram_ctrl_multiple_keys.331289362
/workspace/coverage/default/10.sram_ctrl_partial_access.3172268799
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.2390044252
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1748573713
/workspace/coverage/default/10.sram_ctrl_regwen.111211003
/workspace/coverage/default/10.sram_ctrl_smoke.3944302270
/workspace/coverage/default/10.sram_ctrl_stress_all.3442766035
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.302419505
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.1951667186
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.2630920286
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.389688295
/workspace/coverage/default/11.sram_ctrl_alert_test.4244492896
/workspace/coverage/default/11.sram_ctrl_bijection.1320567147
/workspace/coverage/default/11.sram_ctrl_executable.2943266001
/workspace/coverage/default/11.sram_ctrl_lc_escalation.311466869
/workspace/coverage/default/11.sram_ctrl_max_throughput.1603845872
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.2911217089
/workspace/coverage/default/11.sram_ctrl_mem_walk.332601025
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2542770963
/workspace/coverage/default/11.sram_ctrl_partial_access.1711818706
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.829915318
/workspace/coverage/default/11.sram_ctrl_regwen.958554418
/workspace/coverage/default/11.sram_ctrl_smoke.1083843701
/workspace/coverage/default/11.sram_ctrl_stress_all.78660618
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3702798937
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.4156328110
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1567044625
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2419852773
/workspace/coverage/default/12.sram_ctrl_alert_test.175168034
/workspace/coverage/default/12.sram_ctrl_bijection.1998085018
/workspace/coverage/default/12.sram_ctrl_executable.1345432722
/workspace/coverage/default/12.sram_ctrl_lc_escalation.336769041
/workspace/coverage/default/12.sram_ctrl_max_throughput.16946917
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.2550579742
/workspace/coverage/default/12.sram_ctrl_mem_walk.3634572154
/workspace/coverage/default/12.sram_ctrl_multiple_keys.870323528
/workspace/coverage/default/12.sram_ctrl_partial_access.302550347
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/workspace/coverage/default/43.sram_ctrl_max_throughput.3527085621
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2601446945
/workspace/coverage/default/43.sram_ctrl_mem_walk.458525433
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3206981627
/workspace/coverage/default/43.sram_ctrl_partial_access.1058016433
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1533919191
/workspace/coverage/default/43.sram_ctrl_ram_cfg.2956543879
/workspace/coverage/default/43.sram_ctrl_regwen.1440808026
/workspace/coverage/default/43.sram_ctrl_smoke.3135140923
/workspace/coverage/default/43.sram_ctrl_stress_all.936023086
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2861084115
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3090556454
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.1054038865
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1280209360
/workspace/coverage/default/44.sram_ctrl_alert_test.3052428481
/workspace/coverage/default/44.sram_ctrl_bijection.959711487
/workspace/coverage/default/44.sram_ctrl_executable.2165070579
/workspace/coverage/default/44.sram_ctrl_lc_escalation.952160938
/workspace/coverage/default/44.sram_ctrl_max_throughput.741921936
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.749475424
/workspace/coverage/default/44.sram_ctrl_mem_walk.2677591158
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2784589787
/workspace/coverage/default/44.sram_ctrl_partial_access.935962018
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.2956657108
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1057279438
/workspace/coverage/default/44.sram_ctrl_regwen.2674102486
/workspace/coverage/default/44.sram_ctrl_smoke.3876359120
/workspace/coverage/default/44.sram_ctrl_stress_all.2442464515
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.976344189
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1395564307
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3810123411
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.1501858030
/workspace/coverage/default/45.sram_ctrl_alert_test.278381556
/workspace/coverage/default/45.sram_ctrl_bijection.2067311334
/workspace/coverage/default/45.sram_ctrl_executable.4291987686
/workspace/coverage/default/45.sram_ctrl_max_throughput.469573644
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.3849306539
/workspace/coverage/default/45.sram_ctrl_mem_walk.3760113880
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1772404197
/workspace/coverage/default/45.sram_ctrl_partial_access.3061993087
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3864832965
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1579528173
/workspace/coverage/default/45.sram_ctrl_regwen.2656214059
/workspace/coverage/default/45.sram_ctrl_smoke.2025824054
/workspace/coverage/default/45.sram_ctrl_stress_all.2487268436
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.4103691318
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.1510316215
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.474656171
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2467082244
/workspace/coverage/default/46.sram_ctrl_alert_test.2542198635
/workspace/coverage/default/46.sram_ctrl_bijection.1632299147
/workspace/coverage/default/46.sram_ctrl_executable.3801477807
/workspace/coverage/default/46.sram_ctrl_lc_escalation.3284407414
/workspace/coverage/default/46.sram_ctrl_max_throughput.416062401
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3093722949
/workspace/coverage/default/46.sram_ctrl_mem_walk.1997869631
/workspace/coverage/default/46.sram_ctrl_multiple_keys.238739125
/workspace/coverage/default/46.sram_ctrl_partial_access.1897305880
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3088666224
/workspace/coverage/default/46.sram_ctrl_regwen.3199367038
/workspace/coverage/default/46.sram_ctrl_smoke.344003311
/workspace/coverage/default/46.sram_ctrl_stress_all.1226946560
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.3880636806
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.4009645709
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.3927584411
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.508029626
/workspace/coverage/default/47.sram_ctrl_alert_test.1582307326
/workspace/coverage/default/47.sram_ctrl_bijection.1702223350
/workspace/coverage/default/47.sram_ctrl_executable.3136968977
/workspace/coverage/default/47.sram_ctrl_lc_escalation.566343842
/workspace/coverage/default/47.sram_ctrl_max_throughput.2009325527
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2814756183
/workspace/coverage/default/47.sram_ctrl_mem_walk.3590351550
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2722528833
/workspace/coverage/default/47.sram_ctrl_partial_access.2862041599
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2695570256
/workspace/coverage/default/47.sram_ctrl_ram_cfg.2103080983
/workspace/coverage/default/47.sram_ctrl_regwen.119406713
/workspace/coverage/default/47.sram_ctrl_smoke.499043391
/workspace/coverage/default/47.sram_ctrl_stress_all.1613650444
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1189619797
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.1919843500
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3254132447
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.381939187
/workspace/coverage/default/48.sram_ctrl_alert_test.484592196
/workspace/coverage/default/48.sram_ctrl_bijection.2932547812
/workspace/coverage/default/48.sram_ctrl_executable.2183335976
/workspace/coverage/default/48.sram_ctrl_lc_escalation.145985936
/workspace/coverage/default/48.sram_ctrl_max_throughput.1928495403
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.4243368560
/workspace/coverage/default/48.sram_ctrl_mem_walk.2464775528
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1353994489
/workspace/coverage/default/48.sram_ctrl_partial_access.677954299
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.73076917
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3881573948
/workspace/coverage/default/48.sram_ctrl_regwen.475179271
/workspace/coverage/default/48.sram_ctrl_smoke.3293867353
/workspace/coverage/default/48.sram_ctrl_stress_all.818700542
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2496547819
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1603817818
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2843770148
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.919819240
/workspace/coverage/default/49.sram_ctrl_alert_test.3859702335
/workspace/coverage/default/49.sram_ctrl_bijection.949593885
/workspace/coverage/default/49.sram_ctrl_executable.4018598710
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1565050936
/workspace/coverage/default/49.sram_ctrl_max_throughput.770150552
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2414371695
/workspace/coverage/default/49.sram_ctrl_mem_walk.1782068831
/workspace/coverage/default/49.sram_ctrl_multiple_keys.3941385692
/workspace/coverage/default/49.sram_ctrl_partial_access.805756226
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.780868623
/workspace/coverage/default/49.sram_ctrl_ram_cfg.439098726
/workspace/coverage/default/49.sram_ctrl_regwen.670617707
/workspace/coverage/default/49.sram_ctrl_smoke.1628356512
/workspace/coverage/default/49.sram_ctrl_stress_all.4165071514
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.2080888777
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2210902099
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3079749473
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1900884359
/workspace/coverage/default/5.sram_ctrl_alert_test.1350647634
/workspace/coverage/default/5.sram_ctrl_bijection.65205814
/workspace/coverage/default/5.sram_ctrl_executable.2203330124
/workspace/coverage/default/5.sram_ctrl_lc_escalation.321693572
/workspace/coverage/default/5.sram_ctrl_max_throughput.2995061635
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2004059864
/workspace/coverage/default/5.sram_ctrl_mem_walk.4292631168
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1938553142
/workspace/coverage/default/5.sram_ctrl_partial_access.4078468623
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1332450141
/workspace/coverage/default/5.sram_ctrl_ram_cfg.3574719666
/workspace/coverage/default/5.sram_ctrl_regwen.1081488593
/workspace/coverage/default/5.sram_ctrl_smoke.2018204939
/workspace/coverage/default/5.sram_ctrl_stress_all.2252544156
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2019113415
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.4167115661
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3325629888
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2179695717
/workspace/coverage/default/6.sram_ctrl_alert_test.1596787813
/workspace/coverage/default/6.sram_ctrl_bijection.295051832
/workspace/coverage/default/6.sram_ctrl_executable.618917699
/workspace/coverage/default/6.sram_ctrl_lc_escalation.467175735
/workspace/coverage/default/6.sram_ctrl_max_throughput.1685432573
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.480030923
/workspace/coverage/default/6.sram_ctrl_mem_walk.2689141201
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3895007200
/workspace/coverage/default/6.sram_ctrl_partial_access.1029909335
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3511933420
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3022046740
/workspace/coverage/default/6.sram_ctrl_regwen.2226702386
/workspace/coverage/default/6.sram_ctrl_smoke.2748557921
/workspace/coverage/default/6.sram_ctrl_stress_all.2035759985
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.77472768
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.781910335
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4100100758
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.562272165
/workspace/coverage/default/7.sram_ctrl_alert_test.143222489
/workspace/coverage/default/7.sram_ctrl_bijection.797226479
/workspace/coverage/default/7.sram_ctrl_executable.3882068164
/workspace/coverage/default/7.sram_ctrl_lc_escalation.2436019939
/workspace/coverage/default/7.sram_ctrl_max_throughput.2296071521
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3187155693
/workspace/coverage/default/7.sram_ctrl_mem_walk.3405315529
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1224885847
/workspace/coverage/default/7.sram_ctrl_partial_access.3183454867
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2148158373
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2595055534
/workspace/coverage/default/7.sram_ctrl_regwen.1386925605
/workspace/coverage/default/7.sram_ctrl_smoke.3770363378
/workspace/coverage/default/7.sram_ctrl_stress_all.1510775737
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.494969460
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1530253479
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1856049206
/workspace/coverage/default/8.sram_ctrl_alert_test.133903840
/workspace/coverage/default/8.sram_ctrl_bijection.1303109515
/workspace/coverage/default/8.sram_ctrl_executable.398860302
/workspace/coverage/default/8.sram_ctrl_lc_escalation.4047045770
/workspace/coverage/default/8.sram_ctrl_max_throughput.3101251362
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1659477689
/workspace/coverage/default/8.sram_ctrl_mem_walk.2934269615
/workspace/coverage/default/8.sram_ctrl_multiple_keys.2013584949
/workspace/coverage/default/8.sram_ctrl_partial_access.3670026558
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.3396001939
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3576309262
/workspace/coverage/default/8.sram_ctrl_regwen.2296070447
/workspace/coverage/default/8.sram_ctrl_smoke.3781741491
/workspace/coverage/default/8.sram_ctrl_stress_all.116646953
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.1633008334
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.43255444
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.204492930
/workspace/coverage/default/9.sram_ctrl_alert_test.3164482335
/workspace/coverage/default/9.sram_ctrl_bijection.1856710668
/workspace/coverage/default/9.sram_ctrl_executable.1722470733
/workspace/coverage/default/9.sram_ctrl_lc_escalation.2196241427
/workspace/coverage/default/9.sram_ctrl_max_throughput.3255002357
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3385707856
/workspace/coverage/default/9.sram_ctrl_mem_walk.10987224
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3482690661
/workspace/coverage/default/9.sram_ctrl_partial_access.4052514138
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.3827834023
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1655994760
/workspace/coverage/default/9.sram_ctrl_regwen.2895450667
/workspace/coverage/default/9.sram_ctrl_smoke.3008653004
/workspace/coverage/default/9.sram_ctrl_stress_all.1274695467
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.4074883938
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.923943747
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.637912107



Total test records in report: 1030
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/33.sram_ctrl_ram_cfg.2529041115 Apr 15 02:32:33 PM PDT 24 Apr 15 02:32:34 PM PDT 24 76833149 ps
T2 /workspace/coverage/default/39.sram_ctrl_access_during_key_req.2930274523 Apr 15 02:33:26 PM PDT 24 Apr 15 02:51:30 PM PDT 24 31435339235 ps
T3 /workspace/coverage/default/1.sram_ctrl_multiple_keys.986251999 Apr 15 02:29:47 PM PDT 24 Apr 15 02:41:54 PM PDT 24 2817459672 ps
T4 /workspace/coverage/default/8.sram_ctrl_lc_escalation.4047045770 Apr 15 02:30:10 PM PDT 24 Apr 15 02:30:15 PM PDT 24 281309322 ps
T5 /workspace/coverage/default/45.sram_ctrl_lc_escalation.317543953 Apr 15 02:34:31 PM PDT 24 Apr 15 02:34:39 PM PDT 24 2450158225 ps
T6 /workspace/coverage/default/49.sram_ctrl_access_during_key_req.919819240 Apr 15 02:35:06 PM PDT 24 Apr 15 02:46:41 PM PDT 24 3481850163 ps
T8 /workspace/coverage/default/15.sram_ctrl_smoke.3260187790 Apr 15 02:30:38 PM PDT 24 Apr 15 02:32:32 PM PDT 24 125812918 ps
T9 /workspace/coverage/default/0.sram_ctrl_regwen.646931405 Apr 15 02:29:43 PM PDT 24 Apr 15 02:32:06 PM PDT 24 3239332451 ps
T10 /workspace/coverage/default/35.sram_ctrl_max_throughput.2656543307 Apr 15 02:32:51 PM PDT 24 Apr 15 02:33:21 PM PDT 24 93962144 ps
T11 /workspace/coverage/default/48.sram_ctrl_smoke.3293867353 Apr 15 02:34:54 PM PDT 24 Apr 15 02:35:08 PM PDT 24 254683128 ps
T12 /workspace/coverage/default/38.sram_ctrl_mem_partial_access.1852674667 Apr 15 02:33:22 PM PDT 24 Apr 15 02:33:25 PM PDT 24 99075679 ps
T13 /workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2842481044 Apr 15 02:30:24 PM PDT 24 Apr 15 02:37:05 PM PDT 24 72497027047 ps
T14 /workspace/coverage/default/28.sram_ctrl_stress_all.3026756402 Apr 15 02:31:53 PM PDT 24 Apr 15 03:08:17 PM PDT 24 151348818027 ps
T89 /workspace/coverage/default/3.sram_ctrl_mem_walk.2983390072 Apr 15 02:29:58 PM PDT 24 Apr 15 02:30:07 PM PDT 24 138232819 ps
T90 /workspace/coverage/default/40.sram_ctrl_bijection.62251990 Apr 15 02:33:35 PM PDT 24 Apr 15 02:34:16 PM PDT 24 649941988 ps
T91 /workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.1861757103 Apr 15 02:30:58 PM PDT 24 Apr 15 02:33:06 PM PDT 24 324716820 ps
T27 /workspace/coverage/default/16.sram_ctrl_partial_access.1002726855 Apr 15 02:30:39 PM PDT 24 Apr 15 02:30:47 PM PDT 24 158249254 ps
T92 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.2190621562 Apr 15 02:29:52 PM PDT 24 Apr 15 02:32:19 PM PDT 24 1529192255 ps
T7 /workspace/coverage/default/28.sram_ctrl_lc_escalation.2055853718 Apr 15 02:31:43 PM PDT 24 Apr 15 02:31:52 PM PDT 24 889663238 ps
T15 /workspace/coverage/default/3.sram_ctrl_executable.2180283343 Apr 15 02:29:56 PM PDT 24 Apr 15 02:37:40 PM PDT 24 16543759286 ps
T17 /workspace/coverage/default/46.sram_ctrl_alert_test.2542198635 Apr 15 02:34:44 PM PDT 24 Apr 15 02:34:46 PM PDT 24 36969309 ps
T154 /workspace/coverage/default/22.sram_ctrl_mem_walk.2248577508 Apr 15 02:31:13 PM PDT 24 Apr 15 02:31:19 PM PDT 24 329996210 ps
T32 /workspace/coverage/default/37.sram_ctrl_ram_cfg.2020665536 Apr 15 02:33:11 PM PDT 24 Apr 15 02:33:12 PM PDT 24 31990679 ps
T155 /workspace/coverage/default/39.sram_ctrl_multiple_keys.304623579 Apr 15 02:33:22 PM PDT 24 Apr 15 02:33:39 PM PDT 24 538999264 ps
T31 /workspace/coverage/default/40.sram_ctrl_regwen.4029388913 Apr 15 02:33:38 PM PDT 24 Apr 15 02:39:53 PM PDT 24 665333036 ps
T26 /workspace/coverage/default/30.sram_ctrl_lc_escalation.2768087695 Apr 15 02:32:07 PM PDT 24 Apr 15 02:32:11 PM PDT 24 1482351107 ps
T61 /workspace/coverage/default/35.sram_ctrl_lc_escalation.330233898 Apr 15 02:32:52 PM PDT 24 Apr 15 02:32:54 PM PDT 24 250955359 ps
T23 /workspace/coverage/default/27.sram_ctrl_stress_all.520771824 Apr 15 02:31:44 PM PDT 24 Apr 15 03:01:19 PM PDT 24 7149999354 ps
T33 /workspace/coverage/default/22.sram_ctrl_ram_cfg.1540191169 Apr 15 02:31:10 PM PDT 24 Apr 15 02:31:11 PM PDT 24 81902174 ps
T62 /workspace/coverage/default/49.sram_ctrl_lc_escalation.1565050936 Apr 15 02:35:06 PM PDT 24 Apr 15 02:35:11 PM PDT 24 1290944537 ps
T24 /workspace/coverage/default/38.sram_ctrl_stress_all.3839464068 Apr 15 02:33:19 PM PDT 24 Apr 15 02:59:22 PM PDT 24 48183184671 ps
T156 /workspace/coverage/default/11.sram_ctrl_ram_cfg.3483614254 Apr 15 02:30:20 PM PDT 24 Apr 15 02:30:21 PM PDT 24 83529129 ps
T25 /workspace/coverage/default/2.sram_ctrl_regwen.2262389274 Apr 15 02:29:52 PM PDT 24 Apr 15 02:41:48 PM PDT 24 1393512724 ps
T157 /workspace/coverage/default/29.sram_ctrl_mem_walk.2305166613 Apr 15 02:31:55 PM PDT 24 Apr 15 02:32:01 PM PDT 24 672974121 ps
T123 /workspace/coverage/default/40.sram_ctrl_lc_escalation.4060926196 Apr 15 02:33:38 PM PDT 24 Apr 15 02:33:47 PM PDT 24 2920808608 ps
T16 /workspace/coverage/default/16.sram_ctrl_access_during_key_req.3254637705 Apr 15 02:30:39 PM PDT 24 Apr 15 02:43:34 PM PDT 24 10293999443 ps
T138 /workspace/coverage/default/11.sram_ctrl_executable.2943266001 Apr 15 02:30:20 PM PDT 24 Apr 15 02:44:37 PM PDT 24 20868851196 ps
T142 /workspace/coverage/default/15.sram_ctrl_multiple_keys.834555894 Apr 15 02:30:36 PM PDT 24 Apr 15 02:35:16 PM PDT 24 52594918208 ps
T139 /workspace/coverage/default/38.sram_ctrl_executable.1024617552 Apr 15 02:33:19 PM PDT 24 Apr 15 02:52:38 PM PDT 24 44942636658 ps
T158 /workspace/coverage/default/35.sram_ctrl_bijection.608464780 Apr 15 02:32:47 PM PDT 24 Apr 15 02:33:11 PM PDT 24 1550555012 ps
T159 /workspace/coverage/default/14.sram_ctrl_max_throughput.3934916435 Apr 15 02:30:34 PM PDT 24 Apr 15 02:30:36 PM PDT 24 37533996 ps
T96 /workspace/coverage/default/24.sram_ctrl_partial_access_b2b.759203299 Apr 15 02:31:22 PM PDT 24 Apr 15 02:39:31 PM PDT 24 304077856162 ps
T153 /workspace/coverage/default/8.sram_ctrl_smoke.3781741491 Apr 15 02:30:07 PM PDT 24 Apr 15 02:30:24 PM PDT 24 956105087 ps
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T58 /workspace/coverage/default/34.sram_ctrl_partial_access.1285826400 Apr 15 02:32:37 PM PDT 24 Apr 15 02:33:27 PM PDT 24 686345217 ps
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T30 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.3911831914 Apr 15 02:30:58 PM PDT 24 Apr 15 02:33:25 PM PDT 24 1458221386 ps
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T119 /workspace/coverage/default/15.sram_ctrl_mem_walk.4187630689 Apr 15 02:30:35 PM PDT 24 Apr 15 02:30:46 PM PDT 24 1129138009 ps
T120 /workspace/coverage/default/16.sram_ctrl_stress_all.234041343 Apr 15 02:30:45 PM PDT 24 Apr 15 02:57:09 PM PDT 24 7149485318 ps
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T20 /workspace/coverage/default/0.sram_ctrl_sec_cm.3373815335 Apr 15 02:29:44 PM PDT 24 Apr 15 02:29:47 PM PDT 24 172439414 ps
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T40 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.3626120877 Apr 15 02:30:47 PM PDT 24 Apr 15 02:35:04 PM PDT 24 2286568255 ps
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T42 /workspace/coverage/default/29.sram_ctrl_stress_all.1909213531 Apr 15 02:32:00 PM PDT 24 Apr 15 03:22:38 PM PDT 24 66214055802 ps
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T176 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.3251123591 Apr 15 02:30:14 PM PDT 24 Apr 15 02:36:26 PM PDT 24 3356815134 ps
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T179 /workspace/coverage/default/3.sram_ctrl_regwen.1550607973 Apr 15 02:29:56 PM PDT 24 Apr 15 02:48:09 PM PDT 24 56726031252 ps
T180 /workspace/coverage/default/1.sram_ctrl_stress_all.1138868544 Apr 15 02:29:48 PM PDT 24 Apr 15 02:43:26 PM PDT 24 20495131181 ps
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T47 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.638857364 Apr 15 02:32:53 PM PDT 24 Apr 15 02:33:51 PM PDT 24 1491339461 ps
T182 /workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3079749473 Apr 15 02:35:05 PM PDT 24 Apr 15 02:36:38 PM PDT 24 140221397 ps
T183 /workspace/coverage/default/49.sram_ctrl_partial_access_b2b.780868623 Apr 15 02:35:08 PM PDT 24 Apr 15 02:40:34 PM PDT 24 49911710541 ps
T184 /workspace/coverage/default/26.sram_ctrl_multiple_keys.3975342640 Apr 15 02:31:33 PM PDT 24 Apr 15 02:47:36 PM PDT 24 12009179005 ps
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T48 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1733004659 Apr 15 02:32:10 PM PDT 24 Apr 15 02:32:46 PM PDT 24 208017545 ps
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T189 /workspace/coverage/default/28.sram_ctrl_access_during_key_req.3385314955 Apr 15 02:31:54 PM PDT 24 Apr 15 02:38:18 PM PDT 24 2733437803 ps
T190 /workspace/coverage/default/28.sram_ctrl_max_throughput.2069632475 Apr 15 02:31:44 PM PDT 24 Apr 15 02:31:48 PM PDT 24 167793241 ps
T191 /workspace/coverage/default/18.sram_ctrl_mem_walk.2917375578 Apr 15 02:30:52 PM PDT 24 Apr 15 02:30:57 PM PDT 24 142980969 ps
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T194 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1919843500 Apr 15 02:34:44 PM PDT 24 Apr 15 02:38:00 PM PDT 24 14287628283 ps
T195 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3898675566 Apr 15 02:32:52 PM PDT 24 Apr 15 02:34:14 PM PDT 24 903759819 ps
T196 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.2843770148 Apr 15 02:34:56 PM PDT 24 Apr 15 02:35:12 PM PDT 24 150143282 ps
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T198 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.2911217089 Apr 15 02:30:17 PM PDT 24 Apr 15 02:30:23 PM PDT 24 162325006 ps
T199 /workspace/coverage/default/45.sram_ctrl_regwen.2656214059 Apr 15 02:34:34 PM PDT 24 Apr 15 02:41:19 PM PDT 24 5562998344 ps
T200 /workspace/coverage/default/5.sram_ctrl_executable.2203330124 Apr 15 02:30:04 PM PDT 24 Apr 15 02:39:09 PM PDT 24 1585541766 ps
T201 /workspace/coverage/default/30.sram_ctrl_regwen.3835067938 Apr 15 02:32:10 PM PDT 24 Apr 15 02:39:29 PM PDT 24 4136868817 ps
T202 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.191165129 Apr 15 02:32:14 PM PDT 24 Apr 15 02:32:17 PM PDT 24 176899069 ps
T203 /workspace/coverage/default/39.sram_ctrl_smoke.2070880941 Apr 15 02:33:23 PM PDT 24 Apr 15 02:33:36 PM PDT 24 200404335 ps
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T49 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3127550744 Apr 15 02:33:33 PM PDT 24 Apr 15 02:35:33 PM PDT 24 8210165527 ps
T206 /workspace/coverage/default/6.sram_ctrl_lc_escalation.467175735 Apr 15 02:30:05 PM PDT 24 Apr 15 02:30:13 PM PDT 24 448534657 ps
T207 /workspace/coverage/default/26.sram_ctrl_lc_escalation.2869298894 Apr 15 02:31:39 PM PDT 24 Apr 15 02:31:46 PM PDT 24 719210543 ps
T208 /workspace/coverage/default/16.sram_ctrl_smoke.1439148625 Apr 15 02:30:40 PM PDT 24 Apr 15 02:30:57 PM PDT 24 3145372231 ps
T50 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.600446076 Apr 15 02:30:37 PM PDT 24 Apr 15 02:37:24 PM PDT 24 1801362659 ps
T209 /workspace/coverage/default/33.sram_ctrl_regwen.177028306 Apr 15 02:32:36 PM PDT 24 Apr 15 02:35:37 PM PDT 24 12590244589 ps
T210 /workspace/coverage/default/29.sram_ctrl_ram_cfg.3666764351 Apr 15 02:31:58 PM PDT 24 Apr 15 02:32:00 PM PDT 24 82757089 ps
T211 /workspace/coverage/default/11.sram_ctrl_lc_escalation.311466869 Apr 15 02:30:18 PM PDT 24 Apr 15 02:30:20 PM PDT 24 271872096 ps
T212 /workspace/coverage/default/7.sram_ctrl_alert_test.143222489 Apr 15 02:30:10 PM PDT 24 Apr 15 02:30:12 PM PDT 24 25558901 ps
T213 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.3596194038 Apr 15 02:30:21 PM PDT 24 Apr 15 02:30:23 PM PDT 24 41056485 ps
T214 /workspace/coverage/default/21.sram_ctrl_executable.3573336788 Apr 15 02:31:04 PM PDT 24 Apr 15 02:45:18 PM PDT 24 23929199657 ps
T215 /workspace/coverage/default/24.sram_ctrl_ram_cfg.286569855 Apr 15 02:31:24 PM PDT 24 Apr 15 02:31:25 PM PDT 24 207487605 ps
T216 /workspace/coverage/default/15.sram_ctrl_lc_escalation.2957387682 Apr 15 02:30:38 PM PDT 24 Apr 15 02:30:41 PM PDT 24 189150337 ps
T217 /workspace/coverage/default/38.sram_ctrl_regwen.456920424 Apr 15 02:33:20 PM PDT 24 Apr 15 02:54:32 PM PDT 24 51993386753 ps
T218 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.3922423618 Apr 15 02:31:31 PM PDT 24 Apr 15 02:34:30 PM PDT 24 3803202390 ps
T219 /workspace/coverage/default/28.sram_ctrl_partial_access_b2b.315347051 Apr 15 02:31:46 PM PDT 24 Apr 15 02:38:00 PM PDT 24 6469531386 ps
T220 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.993314160 Apr 15 02:33:12 PM PDT 24 Apr 15 02:33:17 PM PDT 24 74327223 ps
T221 /workspace/coverage/default/45.sram_ctrl_executable.4291987686 Apr 15 02:34:30 PM PDT 24 Apr 15 02:51:07 PM PDT 24 17400492606 ps
T222 /workspace/coverage/default/20.sram_ctrl_mem_partial_access.4118322862 Apr 15 02:30:58 PM PDT 24 Apr 15 02:31:02 PM PDT 24 627063836 ps
T223 /workspace/coverage/default/42.sram_ctrl_multiple_keys.1723614999 Apr 15 02:33:55 PM PDT 24 Apr 15 02:49:11 PM PDT 24 175898418089 ps
T224 /workspace/coverage/default/7.sram_ctrl_max_throughput.2296071521 Apr 15 02:30:09 PM PDT 24 Apr 15 02:30:22 PM PDT 24 131296305 ps
T225 /workspace/coverage/default/21.sram_ctrl_max_throughput.2190988631 Apr 15 02:31:01 PM PDT 24 Apr 15 02:31:03 PM PDT 24 119148616 ps
T226 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.1090458078 Apr 15 02:30:01 PM PDT 24 Apr 15 02:30:07 PM PDT 24 107679121 ps
T227 /workspace/coverage/default/24.sram_ctrl_lc_escalation.2488028420 Apr 15 02:31:23 PM PDT 24 Apr 15 02:31:28 PM PDT 24 812561483 ps
T228 /workspace/coverage/default/43.sram_ctrl_executable.1178198676 Apr 15 02:34:04 PM PDT 24 Apr 15 02:39:12 PM PDT 24 10416770021 ps
T229 /workspace/coverage/default/17.sram_ctrl_stress_all.513764105 Apr 15 02:30:49 PM PDT 24 Apr 15 02:39:37 PM PDT 24 18732521132 ps
T230 /workspace/coverage/default/32.sram_ctrl_stress_all.3951650693 Apr 15 02:32:27 PM PDT 24 Apr 15 02:52:18 PM PDT 24 16726136567 ps
T231 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.3254318621 Apr 15 02:32:24 PM PDT 24 Apr 15 02:36:30 PM PDT 24 10522414932 ps
T232 /workspace/coverage/default/15.sram_ctrl_partial_access.3343028534 Apr 15 02:30:35 PM PDT 24 Apr 15 02:30:55 PM PDT 24 4055669618 ps
T233 /workspace/coverage/default/25.sram_ctrl_smoke.3103416758 Apr 15 02:31:26 PM PDT 24 Apr 15 02:31:39 PM PDT 24 222745412 ps
T234 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.3850724777 Apr 15 02:29:52 PM PDT 24 Apr 15 02:29:58 PM PDT 24 161170114 ps
T235 /workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.632687059 Apr 15 02:33:27 PM PDT 24 Apr 15 02:33:50 PM PDT 24 103495029 ps
T51 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3787370922 Apr 15 02:32:20 PM PDT 24 Apr 15 02:32:44 PM PDT 24 2939536027 ps
T236 /workspace/coverage/default/23.sram_ctrl_lc_escalation.2946875939 Apr 15 02:31:19 PM PDT 24 Apr 15 02:31:25 PM PDT 24 375051280 ps
T237 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.363504204 Apr 15 02:30:36 PM PDT 24 Apr 15 02:35:30 PM PDT 24 8035292985 ps
T238 /workspace/coverage/default/12.sram_ctrl_stress_all.2836088749 Apr 15 02:30:21 PM PDT 24 Apr 15 02:52:30 PM PDT 24 12022317036 ps
T239 /workspace/coverage/default/43.sram_ctrl_lc_escalation.4070625581 Apr 15 02:34:06 PM PDT 24 Apr 15 02:34:13 PM PDT 24 1726530951 ps
T240 /workspace/coverage/default/39.sram_ctrl_max_throughput.3225433329 Apr 15 02:33:23 PM PDT 24 Apr 15 02:33:29 PM PDT 24 206027314 ps
T241 /workspace/coverage/default/12.sram_ctrl_partial_access.302550347 Apr 15 02:30:22 PM PDT 24 Apr 15 02:30:42 PM PDT 24 9878662761 ps
T242 /workspace/coverage/default/37.sram_ctrl_lc_escalation.1493888585 Apr 15 02:33:08 PM PDT 24 Apr 15 02:33:16 PM PDT 24 6598403011 ps
T243 /workspace/coverage/default/36.sram_ctrl_regwen.3723965071 Apr 15 02:33:01 PM PDT 24 Apr 15 02:46:00 PM PDT 24 12257670646 ps
T244 /workspace/coverage/default/10.sram_ctrl_executable.3319839171 Apr 15 02:30:18 PM PDT 24 Apr 15 02:37:10 PM PDT 24 4167686509 ps
T245 /workspace/coverage/default/41.sram_ctrl_lc_escalation.760835966 Apr 15 02:33:50 PM PDT 24 Apr 15 02:33:56 PM PDT 24 1107113266 ps
T246 /workspace/coverage/default/4.sram_ctrl_lc_escalation.1738075751 Apr 15 02:30:02 PM PDT 24 Apr 15 02:30:05 PM PDT 24 285697473 ps
T247 /workspace/coverage/default/9.sram_ctrl_bijection.1856710668 Apr 15 02:30:17 PM PDT 24 Apr 15 02:31:15 PM PDT 24 3571796851 ps
T248 /workspace/coverage/default/25.sram_ctrl_multiple_keys.1551678559 Apr 15 02:31:28 PM PDT 24 Apr 15 02:42:13 PM PDT 24 11465614856 ps
T249 /workspace/coverage/default/17.sram_ctrl_stress_pipeline.3649069819 Apr 15 02:30:46 PM PDT 24 Apr 15 02:34:14 PM PDT 24 4604230736 ps
T250 /workspace/coverage/default/20.sram_ctrl_bijection.1329779697 Apr 15 02:30:58 PM PDT 24 Apr 15 02:31:44 PM PDT 24 1389596620 ps
T251 /workspace/coverage/default/25.sram_ctrl_max_throughput.1214107368 Apr 15 02:31:27 PM PDT 24 Apr 15 02:32:38 PM PDT 24 227025506 ps
T252 /workspace/coverage/default/45.sram_ctrl_ram_cfg.1579528173 Apr 15 02:34:31 PM PDT 24 Apr 15 02:34:33 PM PDT 24 136016202 ps
T253 /workspace/coverage/default/42.sram_ctrl_mem_walk.3727895763 Apr 15 02:33:58 PM PDT 24 Apr 15 02:34:07 PM PDT 24 1014960463 ps
T52 /workspace/coverage/default/23.sram_ctrl_stress_all_with_rand_reset.3873956267 Apr 15 02:31:18 PM PDT 24 Apr 15 02:31:26 PM PDT 24 690627875 ps
T254 /workspace/coverage/default/26.sram_ctrl_access_during_key_req.1886517641 Apr 15 02:31:30 PM PDT 24 Apr 15 02:50:43 PM PDT 24 14158388972 ps
T255 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.4167115661 Apr 15 02:30:01 PM PDT 24 Apr 15 02:36:03 PM PDT 24 6986792298 ps
T256 /workspace/coverage/default/34.sram_ctrl_max_throughput.291776668 Apr 15 02:32:42 PM PDT 24 Apr 15 02:32:43 PM PDT 24 136390237 ps
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T258 /workspace/coverage/default/7.sram_ctrl_multiple_keys.1224885847 Apr 15 02:30:06 PM PDT 24 Apr 15 02:46:07 PM PDT 24 2995788083 ps
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T260 /workspace/coverage/default/43.sram_ctrl_regwen.1440808026 Apr 15 02:34:05 PM PDT 24 Apr 15 02:52:57 PM PDT 24 82554985544 ps
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T263 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.3850615295 Apr 15 02:31:50 PM PDT 24 Apr 15 02:31:53 PM PDT 24 60173641 ps
T264 /workspace/coverage/default/28.sram_ctrl_regwen.1331388450 Apr 15 02:31:50 PM PDT 24 Apr 15 02:41:10 PM PDT 24 1327869154 ps
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T266 /workspace/coverage/default/12.sram_ctrl_bijection.1998085018 Apr 15 02:30:20 PM PDT 24 Apr 15 02:31:34 PM PDT 24 13553197404 ps
T267 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.204492930 Apr 15 02:30:17 PM PDT 24 Apr 15 02:54:45 PM PDT 24 52499748310 ps
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T269 /workspace/coverage/default/18.sram_ctrl_smoke.112360991 Apr 15 02:30:50 PM PDT 24 Apr 15 02:30:54 PM PDT 24 115485072 ps
T270 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.2550579742 Apr 15 02:30:26 PM PDT 24 Apr 15 02:30:32 PM PDT 24 152975269 ps
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T272 /workspace/coverage/default/26.sram_ctrl_ram_cfg.1319414647 Apr 15 02:31:40 PM PDT 24 Apr 15 02:31:42 PM PDT 24 29249696 ps
T108 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2694884288 Apr 15 02:32:31 PM PDT 24 Apr 15 02:38:12 PM PDT 24 5409070139 ps
T273 /workspace/coverage/default/31.sram_ctrl_alert_test.1203042362 Apr 15 02:32:20 PM PDT 24 Apr 15 02:32:21 PM PDT 24 14226702 ps
T274 /workspace/coverage/default/49.sram_ctrl_multiple_keys.3941385692 Apr 15 02:35:03 PM PDT 24 Apr 15 02:51:49 PM PDT 24 3068796350 ps
T275 /workspace/coverage/default/29.sram_ctrl_regwen.4210770097 Apr 15 02:32:15 PM PDT 24 Apr 15 02:45:29 PM PDT 24 139418833594 ps
T276 /workspace/coverage/default/32.sram_ctrl_smoke.49189848 Apr 15 02:32:21 PM PDT 24 Apr 15 02:32:31 PM PDT 24 171081458 ps
T277 /workspace/coverage/default/12.sram_ctrl_smoke.26818691 Apr 15 02:30:21 PM PDT 24 Apr 15 02:30:58 PM PDT 24 865957349 ps
T278 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.90739112 Apr 15 02:33:15 PM PDT 24 Apr 15 02:36:24 PM PDT 24 3861195832 ps
T279 /workspace/coverage/default/29.sram_ctrl_lc_escalation.388611215 Apr 15 02:31:58 PM PDT 24 Apr 15 02:32:04 PM PDT 24 1110155932 ps
T280 /workspace/coverage/default/24.sram_ctrl_mem_walk.4168242249 Apr 15 02:31:25 PM PDT 24 Apr 15 02:31:31 PM PDT 24 148520288 ps
T281 /workspace/coverage/default/32.sram_ctrl_partial_access.7356963 Apr 15 02:32:23 PM PDT 24 Apr 15 02:32:26 PM PDT 24 477166162 ps
T282 /workspace/coverage/default/49.sram_ctrl_executable.4018598710 Apr 15 02:35:06 PM PDT 24 Apr 15 02:42:00 PM PDT 24 5030775057 ps
T283 /workspace/coverage/default/47.sram_ctrl_ram_cfg.2103080983 Apr 15 02:34:51 PM PDT 24 Apr 15 02:34:52 PM PDT 24 50514660 ps
T284 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.1900884359 Apr 15 02:30:02 PM PDT 24 Apr 15 02:43:38 PM PDT 24 10368729498 ps
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T286 /workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.2531540231 Apr 15 02:30:41 PM PDT 24 Apr 15 02:30:49 PM PDT 24 121423267 ps
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T288 /workspace/coverage/default/36.sram_ctrl_bijection.1506176255 Apr 15 02:32:57 PM PDT 24 Apr 15 02:33:16 PM PDT 24 6453300816 ps
T289 /workspace/coverage/default/21.sram_ctrl_bijection.3924351567 Apr 15 02:31:01 PM PDT 24 Apr 15 02:31:39 PM PDT 24 2478121861 ps
T290 /workspace/coverage/default/36.sram_ctrl_stress_all.689937632 Apr 15 02:33:06 PM PDT 24 Apr 15 03:33:31 PM PDT 24 74799174904 ps
T291 /workspace/coverage/default/41.sram_ctrl_ram_cfg.1558730211 Apr 15 02:33:51 PM PDT 24 Apr 15 02:33:52 PM PDT 24 29187425 ps
T292 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.2714393090 Apr 15 02:34:06 PM PDT 24 Apr 15 02:38:03 PM PDT 24 1761239845 ps
T293 /workspace/coverage/default/3.sram_ctrl_smoke.2620744502 Apr 15 02:29:52 PM PDT 24 Apr 15 02:29:54 PM PDT 24 150543119 ps
T294 /workspace/coverage/default/30.sram_ctrl_executable.2190493031 Apr 15 02:32:07 PM PDT 24 Apr 15 02:44:27 PM PDT 24 2861559712 ps
T295 /workspace/coverage/default/21.sram_ctrl_alert_test.378102741 Apr 15 02:31:08 PM PDT 24 Apr 15 02:31:09 PM PDT 24 14439623 ps
T296 /workspace/coverage/default/41.sram_ctrl_max_throughput.1184913534 Apr 15 02:33:47 PM PDT 24 Apr 15 02:35:24 PM PDT 24 126777971 ps
T297 /workspace/coverage/default/44.sram_ctrl_partial_access.935962018 Apr 15 02:34:12 PM PDT 24 Apr 15 02:34:22 PM PDT 24 699705200 ps
T298 /workspace/coverage/default/15.sram_ctrl_regwen.753018384 Apr 15 02:30:34 PM PDT 24 Apr 15 02:33:09 PM PDT 24 3722543361 ps
T299 /workspace/coverage/default/22.sram_ctrl_executable.3388176828 Apr 15 02:31:09 PM PDT 24 Apr 15 02:40:20 PM PDT 24 5379902910 ps
T300 /workspace/coverage/default/37.sram_ctrl_executable.4134476318 Apr 15 02:33:13 PM PDT 24 Apr 15 02:47:15 PM PDT 24 33276302849 ps
T301 /workspace/coverage/default/10.sram_ctrl_alert_test.230244060 Apr 15 02:30:22 PM PDT 24 Apr 15 02:30:24 PM PDT 24 53261444 ps
T302 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.3203510858 Apr 15 02:32:41 PM PDT 24 Apr 15 02:32:46 PM PDT 24 742810215 ps
T303 /workspace/coverage/default/23.sram_ctrl_stress_pipeline.1667003942 Apr 15 02:31:13 PM PDT 24 Apr 15 02:33:40 PM PDT 24 12390140960 ps
T304 /workspace/coverage/default/30.sram_ctrl_bijection.3239712753 Apr 15 02:32:00 PM PDT 24 Apr 15 02:33:28 PM PDT 24 44981158139 ps
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