Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	46067160	1			T2	186712		T3	139163		T4	649
triple_byte_access	2560176	1			T2	3732		T3	2809		T4	14
halfword_access	3842650	1			T2	5547		T3	4185		T4	21
byte_access	5127796	1			T2	7433		T3	5625		T4	27
zero_access	1289058	1			T2	1871		T3	1388		T4	7

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29387776

1

T2

102899

T3

76317

T4

347

auto[1]

29499064

1

T2

102396

T3

76853

T4

371

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22983462	1			T2	93667		T3	69328		T4	321
auto[0]	triple_byte_access	1276712	1			T2	1845		T3	1381		T4	5
auto[0]	halfword_access	1917628	1			T2	2737		T3	2074		T4	4
auto[0]	byte_access	2561554	1			T2	3750		T3	2829		T4	14
auto[0]	zero_access	648420	1			T2	900		T3	705		T4	3
auto[1]	word_access	23083698	1			T2	93045		T3	69835		T4	328
auto[1]	triple_byte_access	1283464	1			T2	1887		T3	1428		T4	9
auto[1]	halfword_access	1925022	1			T2	2810		T3	2111		T4	17
auto[1]	byte_access	2566242	1			T2	3683		T3	2796		T4	13
auto[1]	zero_access	640638	1			T2	971		T3	683		T4	4