Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	149472666	1			T2	14678		T3	322744		T4	471746
instr_valid_dis	118668014	1			T2	14678		T3	234020		T4	471746
instr_en	21405649	1			T3	88724		T17	97036		T32	11014

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10060487	1			T3	13884		T17	60818		T32	91358
sram_ifetch_valid_disable	118122308	1			T2	14678		T3	67676		T4	471746
sram_ifetch_enable	21289871	1			T3	241184		T17	133280		T32	128400

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	149472666	1			T2	14678		T3	322744		T4	471746
hw_debug_en_valid_off	117888259	1			T2	14678		T3	90190		T4	471746
hw_debug_en_on	21077491	1			T3	196520		T17	119430		T32	129846

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	118122308	1			T2	14678		T3	67676		T4	471746
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	105515430	1			T2	14678		T3	25538		T4	471746
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8842654	1			T3	42138		T17	37400		T42	31262
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4815448	1			T3	1738		T17	40512		T32	22846
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1974978	1			T3	1738		T32	11900		T114	14800
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1795237	1			T17	40000		T32	10946		T27	36012
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	3615400	1			T3	12146		T17	20306		T32	68512
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1624176	1			T17	20306		T32	48544		T116	88998
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1255050	1			T3	12146		T53	4114		T29	25408
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8173526	1			T3	40060		T17	55140		T32	110
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3464618	1			T3	16896		T17	17740		T32	110
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	3438796	1			T3	23164		T17	37400		T114	38236

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	8918696	1			T3	34440		T17	19636		T32	68
lc_exec_en	9288565	1			T3	144314		T17	43984		T32	61224
valid_exec_dis	113573453	1			T2	14678		T3	234360		T4	471746
invalid_exec_dis	31350358	1			T3	255068		T17	194098		T32	219758