Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 97.02 100.00 100.00 98.58 99.70 98.52


Total tests in report: 1023
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.30 85.30 97.37 97.37 83.93 83.93 96.78 96.78 71.43 71.43 91.38 91.38 95.51 95.51 60.67 60.67 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4046133904
92.45 7.15 99.03 1.66 90.23 6.30 98.21 1.43 100.00 28.57 96.84 5.46 95.66 0.15 67.16 6.49 /workspace/coverage/default/46.sram_ctrl_stress_all.1993657502
95.12 2.67 99.03 0.00 90.36 0.13 98.21 0.00 100.00 0.00 96.84 0.00 95.66 0.00 85.71 18.55 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1318985224
96.12 1.01 99.42 0.39 92.54 2.19 99.14 0.93 100.00 0.00 98.56 1.72 96.56 0.90 86.64 0.93 /workspace/coverage/default/4.sram_ctrl_sec_cm.1726809320
96.89 0.77 99.42 0.00 92.93 0.39 99.14 0.00 100.00 0.00 98.56 0.00 96.56 0.00 91.65 5.01 /workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1184928536
97.42 0.53 99.71 0.29 93.06 0.13 99.14 0.00 100.00 0.00 98.85 0.29 97.31 0.75 93.88 2.23 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1142776053
97.73 0.31 99.71 0.00 93.19 0.13 99.14 0.00 100.00 0.00 98.85 0.00 97.31 0.00 95.92 2.04 /workspace/coverage/default/11.sram_ctrl_stress_all.3835963163
98.00 0.27 99.71 0.00 93.44 0.26 99.21 0.07 100.00 0.00 98.85 0.00 98.50 1.20 96.29 0.37 /workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3719722320
98.20 0.20 99.71 0.00 93.96 0.51 99.21 0.00 100.00 0.00 98.85 0.00 99.40 0.90 96.29 0.00 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2222391219
98.32 0.12 99.81 0.10 93.96 0.00 99.93 0.72 100.00 0.00 98.85 0.00 99.40 0.00 96.29 0.00 /workspace/coverage/default/1.sram_ctrl_ram_cfg.4128758212
98.43 0.11 99.81 0.00 93.96 0.00 99.93 0.00 100.00 0.00 98.85 0.00 99.40 0.00 97.03 0.74 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2858196013
98.50 0.08 99.81 0.00 93.96 0.00 99.93 0.00 100.00 0.00 98.85 0.00 99.40 0.00 97.59 0.56 /workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.634090494
98.57 0.07 99.81 0.00 94.34 0.39 100.00 0.07 100.00 0.00 98.85 0.00 99.40 0.00 97.59 0.00 /workspace/coverage/default/1.sram_ctrl_alert_test.388190665
98.62 0.05 99.81 0.00 94.34 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.40 0.00 97.96 0.37 /workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3218792099
98.68 0.05 99.81 0.00 94.34 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.40 0.00 98.33 0.37 /workspace/coverage/default/26.sram_ctrl_stress_all.387621735
98.72 0.04 99.81 0.00 94.47 0.13 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.15 98.33 0.00 /workspace/coverage/default/23.sram_ctrl_stress_all.1636777260
98.74 0.03 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 98.52 0.19 /workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3643718928
98.76 0.02 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.15 98.52 0.00 /workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.821304010

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2226195229
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.214383169
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3609896212
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3916268967
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4136397759
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.279810265
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3583066248
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.482161085
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2547579471
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.309798377
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.871806329
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3060289022
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1382068611
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.523585932
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.670181439
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1983979027
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2067614489
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2194447913
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3494929963
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3442703692
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4244433622
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1120453750
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2216157774
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.548343492
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.117536008
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.180007624
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1947323535
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1302260602
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2084221826
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.750763685
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2466956360
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2702991463
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.188833241
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2699652229
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2433848285
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.51267462
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1205678879
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1416521227
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4059716778
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.283849258
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3174903863
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.670491897
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1782917740
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3597333681
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2765667532
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.238512968
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2042664389
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3175642352
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3532320571
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.322116941
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3318567770
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.876970347
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2189181828
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1991138539
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.382433985
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.421687390
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2512013858
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4029999924
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1357317739
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1533880054
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.572700241
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3577114335
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3609931319
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4031497872
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4250390541
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1985340757
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2980771435
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1625730864
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2789728100
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2569281168
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3760198825
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3766928036
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3621700698
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2095969772
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4032201799
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.27506173
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.226488183
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.700403210
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1066301907
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.120186090
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1801836198
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3330910425
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1082247560
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.20941368
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1754000398
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1071714148
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.95116462
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.129666555
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1328913922
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1155112752
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1458813508
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1536396592
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3291459202
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3942051221
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4230290709
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.976727586
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.389248228
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2938242478
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3706173046
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1100500907
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1567442237
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.176722917
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2477180375
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1371895313
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.894664492
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4055984371
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2536841308
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1228235226
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.509376184
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.395938570
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3924356764
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.360851385
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1047353622
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3454454809
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.169608077
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.328620772
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4043461058
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1043538714
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3285854139
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.741444663
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4149064856
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3247671211
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.4243458015
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.285408396
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.162446905
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3420655676
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1106470143
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1812867510
/workspace/coverage/default/0.sram_ctrl_alert_test.3263252888
/workspace/coverage/default/0.sram_ctrl_bijection.162735134
/workspace/coverage/default/0.sram_ctrl_executable.3997969863
/workspace/coverage/default/0.sram_ctrl_lc_escalation.772564410
/workspace/coverage/default/0.sram_ctrl_max_throughput.2260811182
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1302766066
/workspace/coverage/default/0.sram_ctrl_mem_walk.1818868682
/workspace/coverage/default/0.sram_ctrl_multiple_keys.955351955
/workspace/coverage/default/0.sram_ctrl_partial_access.1770462993
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.1516104005
/workspace/coverage/default/0.sram_ctrl_ram_cfg.4277105102
/workspace/coverage/default/0.sram_ctrl_regwen.1671842197
/workspace/coverage/default/0.sram_ctrl_sec_cm.2719816401
/workspace/coverage/default/0.sram_ctrl_smoke.1795820411
/workspace/coverage/default/0.sram_ctrl_stress_all.3339529235
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3270613911
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.1578279393
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.3769644666
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.532323106
/workspace/coverage/default/1.sram_ctrl_bijection.3756308799
/workspace/coverage/default/1.sram_ctrl_executable.4031900146
/workspace/coverage/default/1.sram_ctrl_lc_escalation.290951536
/workspace/coverage/default/1.sram_ctrl_max_throughput.3014176941
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1054096397
/workspace/coverage/default/1.sram_ctrl_mem_walk.1152939159
/workspace/coverage/default/1.sram_ctrl_multiple_keys.3253221498
/workspace/coverage/default/1.sram_ctrl_partial_access.279098207
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3443812619
/workspace/coverage/default/1.sram_ctrl_regwen.1403070275
/workspace/coverage/default/1.sram_ctrl_sec_cm.2555840104
/workspace/coverage/default/1.sram_ctrl_smoke.2743122955
/workspace/coverage/default/1.sram_ctrl_stress_all.1571504054
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2565323821
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.542198394
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.707033473
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2838968623
/workspace/coverage/default/10.sram_ctrl_alert_test.1989427937
/workspace/coverage/default/10.sram_ctrl_bijection.1107755601
/workspace/coverage/default/10.sram_ctrl_executable.3465822243
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3607634860
/workspace/coverage/default/10.sram_ctrl_max_throughput.1893993376
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.130266795
/workspace/coverage/default/10.sram_ctrl_mem_walk.3716227566
/workspace/coverage/default/10.sram_ctrl_multiple_keys.3433387184
/workspace/coverage/default/10.sram_ctrl_partial_access.647222557
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1255268436
/workspace/coverage/default/10.sram_ctrl_ram_cfg.640554458
/workspace/coverage/default/10.sram_ctrl_regwen.3287849448
/workspace/coverage/default/10.sram_ctrl_smoke.1585767237
/workspace/coverage/default/10.sram_ctrl_stress_all.3328592229
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3216746924
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.162337744
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.1397198386
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.423162609
/workspace/coverage/default/11.sram_ctrl_alert_test.784816586
/workspace/coverage/default/11.sram_ctrl_bijection.3342511811
/workspace/coverage/default/11.sram_ctrl_executable.529787199
/workspace/coverage/default/11.sram_ctrl_lc_escalation.2979671591
/workspace/coverage/default/11.sram_ctrl_max_throughput.908159370
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.1570165362
/workspace/coverage/default/11.sram_ctrl_mem_walk.2388104966
/workspace/coverage/default/11.sram_ctrl_multiple_keys.2583269896
/workspace/coverage/default/11.sram_ctrl_partial_access.3348172572
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.20004950
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1427273530
/workspace/coverage/default/11.sram_ctrl_regwen.458294815
/workspace/coverage/default/11.sram_ctrl_smoke.2922671126
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3791052213
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3107161391
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.594350127
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.577165965
/workspace/coverage/default/12.sram_ctrl_alert_test.432248472
/workspace/coverage/default/12.sram_ctrl_bijection.4108262164
/workspace/coverage/default/12.sram_ctrl_executable.1834955130
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3877158014
/workspace/coverage/default/12.sram_ctrl_max_throughput.3254259497
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.848915635
/workspace/coverage/default/12.sram_ctrl_mem_walk.4006734586
/workspace/coverage/default/12.sram_ctrl_multiple_keys.912721607
/workspace/coverage/default/12.sram_ctrl_partial_access.265529498
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.249759467
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/workspace/coverage/default/43.sram_ctrl_mem_walk.1634098048
/workspace/coverage/default/43.sram_ctrl_partial_access.1517556183
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1238156066
/workspace/coverage/default/43.sram_ctrl_ram_cfg.1138520823
/workspace/coverage/default/43.sram_ctrl_regwen.2823909874
/workspace/coverage/default/43.sram_ctrl_smoke.4012244303
/workspace/coverage/default/43.sram_ctrl_stress_all.4146433202
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.3600544867
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2805704912
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2996474341
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.2722218285
/workspace/coverage/default/44.sram_ctrl_alert_test.1729630101
/workspace/coverage/default/44.sram_ctrl_bijection.1305884871
/workspace/coverage/default/44.sram_ctrl_executable.2968694178
/workspace/coverage/default/44.sram_ctrl_lc_escalation.179800656
/workspace/coverage/default/44.sram_ctrl_max_throughput.741928927
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3330688662
/workspace/coverage/default/44.sram_ctrl_mem_walk.1209995331
/workspace/coverage/default/44.sram_ctrl_multiple_keys.1659507276
/workspace/coverage/default/44.sram_ctrl_partial_access.922534740
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1725482603
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2157541115
/workspace/coverage/default/44.sram_ctrl_regwen.1894760860
/workspace/coverage/default/44.sram_ctrl_smoke.445960452
/workspace/coverage/default/44.sram_ctrl_stress_all.2359532289
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3480068818
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1105802768
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.142796966
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2154176924
/workspace/coverage/default/45.sram_ctrl_alert_test.2732618567
/workspace/coverage/default/45.sram_ctrl_bijection.2445414683
/workspace/coverage/default/45.sram_ctrl_executable.3089548822
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1303531845
/workspace/coverage/default/45.sram_ctrl_max_throughput.3432422398
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.950561894
/workspace/coverage/default/45.sram_ctrl_mem_walk.10095755
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3300603017
/workspace/coverage/default/45.sram_ctrl_partial_access.1973189880
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.3656657721
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3943914790
/workspace/coverage/default/45.sram_ctrl_smoke.2429058125
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.1552438780
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2606111924
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.275765208
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1159478053
/workspace/coverage/default/46.sram_ctrl_alert_test.1465913583
/workspace/coverage/default/46.sram_ctrl_bijection.1990891381
/workspace/coverage/default/46.sram_ctrl_executable.560851954
/workspace/coverage/default/46.sram_ctrl_lc_escalation.1287005508
/workspace/coverage/default/46.sram_ctrl_max_throughput.564815960
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.409560917
/workspace/coverage/default/46.sram_ctrl_mem_walk.1868169259
/workspace/coverage/default/46.sram_ctrl_multiple_keys.534086134
/workspace/coverage/default/46.sram_ctrl_partial_access.415945308
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.626084718
/workspace/coverage/default/46.sram_ctrl_ram_cfg.3083383366
/workspace/coverage/default/46.sram_ctrl_regwen.1808250392
/workspace/coverage/default/46.sram_ctrl_smoke.2178474900
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.635252022
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.97000632
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.4214469506
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.217158618
/workspace/coverage/default/47.sram_ctrl_alert_test.2094471489
/workspace/coverage/default/47.sram_ctrl_bijection.493506276
/workspace/coverage/default/47.sram_ctrl_executable.616339852
/workspace/coverage/default/47.sram_ctrl_lc_escalation.463018822
/workspace/coverage/default/47.sram_ctrl_max_throughput.1014461791
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.3258916720
/workspace/coverage/default/47.sram_ctrl_mem_walk.2267553796
/workspace/coverage/default/47.sram_ctrl_multiple_keys.939800609
/workspace/coverage/default/47.sram_ctrl_partial_access.1815136209
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.4111477626
/workspace/coverage/default/47.sram_ctrl_ram_cfg.729479685
/workspace/coverage/default/47.sram_ctrl_regwen.2647158234
/workspace/coverage/default/47.sram_ctrl_smoke.1954027497
/workspace/coverage/default/47.sram_ctrl_stress_all.3139483425
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2356028607
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.249459529
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3879442700
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1613425611
/workspace/coverage/default/48.sram_ctrl_alert_test.3425804362
/workspace/coverage/default/48.sram_ctrl_bijection.2218787517
/workspace/coverage/default/48.sram_ctrl_executable.3876222287
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1417373269
/workspace/coverage/default/48.sram_ctrl_max_throughput.1164780355
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.2519055073
/workspace/coverage/default/48.sram_ctrl_mem_walk.4288188550
/workspace/coverage/default/48.sram_ctrl_multiple_keys.576057216
/workspace/coverage/default/48.sram_ctrl_partial_access.1084715151
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3689405501
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3873589613
/workspace/coverage/default/48.sram_ctrl_regwen.2541613255
/workspace/coverage/default/48.sram_ctrl_smoke.2130680264
/workspace/coverage/default/48.sram_ctrl_stress_all.4230966289
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.2613897200
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3593781011
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.129482170
/workspace/coverage/default/49.sram_ctrl_alert_test.839754384
/workspace/coverage/default/49.sram_ctrl_bijection.1507799772
/workspace/coverage/default/49.sram_ctrl_executable.1008580273
/workspace/coverage/default/49.sram_ctrl_lc_escalation.586519285
/workspace/coverage/default/49.sram_ctrl_max_throughput.951350341
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.981380193
/workspace/coverage/default/49.sram_ctrl_mem_walk.2470201127
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1851050786
/workspace/coverage/default/49.sram_ctrl_partial_access.3559559359
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3002516520
/workspace/coverage/default/49.sram_ctrl_ram_cfg.741072615
/workspace/coverage/default/49.sram_ctrl_regwen.2374115888
/workspace/coverage/default/49.sram_ctrl_smoke.1765246518
/workspace/coverage/default/49.sram_ctrl_stress_all.4181183797
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.3810349315
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3471555853
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1973281644
/workspace/coverage/default/5.sram_ctrl_alert_test.3800350958
/workspace/coverage/default/5.sram_ctrl_bijection.827567911
/workspace/coverage/default/5.sram_ctrl_executable.3315634731
/workspace/coverage/default/5.sram_ctrl_lc_escalation.233958467
/workspace/coverage/default/5.sram_ctrl_max_throughput.2186224161
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2828133977
/workspace/coverage/default/5.sram_ctrl_mem_walk.2251975475
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1995970841
/workspace/coverage/default/5.sram_ctrl_partial_access.291834857
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.4290487554
/workspace/coverage/default/5.sram_ctrl_ram_cfg.1329003810
/workspace/coverage/default/5.sram_ctrl_regwen.3963031609
/workspace/coverage/default/5.sram_ctrl_smoke.3445926469
/workspace/coverage/default/5.sram_ctrl_stress_all.399535891
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.785457556
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.4265557973
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2494713256
/workspace/coverage/default/6.sram_ctrl_alert_test.3033685584
/workspace/coverage/default/6.sram_ctrl_bijection.2669513753
/workspace/coverage/default/6.sram_ctrl_executable.2013137956
/workspace/coverage/default/6.sram_ctrl_lc_escalation.1478350434
/workspace/coverage/default/6.sram_ctrl_max_throughput.3912393668
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.2483913814
/workspace/coverage/default/6.sram_ctrl_mem_walk.2769750265
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3138205008
/workspace/coverage/default/6.sram_ctrl_partial_access.904706532
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.1433614182
/workspace/coverage/default/6.sram_ctrl_ram_cfg.3072152303
/workspace/coverage/default/6.sram_ctrl_regwen.2237202508
/workspace/coverage/default/6.sram_ctrl_smoke.3065348936
/workspace/coverage/default/6.sram_ctrl_stress_all.165030769
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.4002148556
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2532212687
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.2022330277
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.731768999
/workspace/coverage/default/7.sram_ctrl_alert_test.1382743085
/workspace/coverage/default/7.sram_ctrl_bijection.2835390819
/workspace/coverage/default/7.sram_ctrl_executable.3418375850
/workspace/coverage/default/7.sram_ctrl_lc_escalation.4120996469
/workspace/coverage/default/7.sram_ctrl_max_throughput.707007462
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2511507558
/workspace/coverage/default/7.sram_ctrl_mem_walk.1894137312
/workspace/coverage/default/7.sram_ctrl_multiple_keys.2976093729
/workspace/coverage/default/7.sram_ctrl_partial_access.2490257799
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.153403711
/workspace/coverage/default/7.sram_ctrl_ram_cfg.2390228285
/workspace/coverage/default/7.sram_ctrl_regwen.2747829077
/workspace/coverage/default/7.sram_ctrl_smoke.196944729
/workspace/coverage/default/7.sram_ctrl_stress_all.2609802187
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.1572069137
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.4025494145
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2069693172
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.3115075060
/workspace/coverage/default/8.sram_ctrl_alert_test.625182911
/workspace/coverage/default/8.sram_ctrl_bijection.2401530553
/workspace/coverage/default/8.sram_ctrl_executable.2801597604
/workspace/coverage/default/8.sram_ctrl_lc_escalation.2620248336
/workspace/coverage/default/8.sram_ctrl_max_throughput.444549996
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3057648271
/workspace/coverage/default/8.sram_ctrl_mem_walk.902251022
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3353541134
/workspace/coverage/default/8.sram_ctrl_partial_access.1683522098
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.982640072
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3589852621
/workspace/coverage/default/8.sram_ctrl_regwen.213740967
/workspace/coverage/default/8.sram_ctrl_smoke.55994744
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2454051768
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3455791398
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3524064060
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3475864411
/workspace/coverage/default/9.sram_ctrl_alert_test.3315919676
/workspace/coverage/default/9.sram_ctrl_bijection.1301808462
/workspace/coverage/default/9.sram_ctrl_executable.3893911267
/workspace/coverage/default/9.sram_ctrl_lc_escalation.1096849262
/workspace/coverage/default/9.sram_ctrl_max_throughput.991446650
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.1146066301
/workspace/coverage/default/9.sram_ctrl_mem_walk.671790515
/workspace/coverage/default/9.sram_ctrl_multiple_keys.1330194948
/workspace/coverage/default/9.sram_ctrl_partial_access.488747481
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2118712534
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1433412588
/workspace/coverage/default/9.sram_ctrl_regwen.1685285336
/workspace/coverage/default/9.sram_ctrl_smoke.3866208273
/workspace/coverage/default/9.sram_ctrl_stress_all.3930473030
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.32290263
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.268604491



Total test records in report: 1023
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/5.sram_ctrl_ram_cfg.1329003810 Apr 16 12:51:55 PM PDT 24 Apr 16 12:51:58 PM PDT 24 141111699 ps
T2 /workspace/coverage/default/3.sram_ctrl_smoke.1196924590 Apr 16 12:51:27 PM PDT 24 Apr 16 12:52:25 PM PDT 24 2097333555 ps
T3 /workspace/coverage/default/27.sram_ctrl_executable.3603543673 Apr 16 12:52:48 PM PDT 24 Apr 16 01:04:47 PM PDT 24 2714133160 ps
T4 /workspace/coverage/default/42.sram_ctrl_partial_access_b2b.1142776053 Apr 16 12:54:39 PM PDT 24 Apr 16 01:01:36 PM PDT 24 94278833273 ps
T10 /workspace/coverage/default/49.sram_ctrl_partial_access.3559559359 Apr 16 12:55:51 PM PDT 24 Apr 16 12:56:02 PM PDT 24 880827216 ps
T11 /workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1960744673 Apr 16 12:51:54 PM PDT 24 Apr 16 12:52:21 PM PDT 24 189478166 ps
T12 /workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.3593781011 Apr 16 12:55:45 PM PDT 24 Apr 16 12:57:25 PM PDT 24 144405189 ps
T13 /workspace/coverage/default/23.sram_ctrl_multiple_keys.3564000290 Apr 16 12:52:29 PM PDT 24 Apr 16 01:05:28 PM PDT 24 3201084169 ps
T5 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.4046133904 Apr 16 12:51:34 PM PDT 24 Apr 16 12:53:12 PM PDT 24 2438571305 ps
T14 /workspace/coverage/default/47.sram_ctrl_mem_partial_access.3258916720 Apr 16 12:55:41 PM PDT 24 Apr 16 12:55:47 PM PDT 24 159450684 ps
T16 /workspace/coverage/default/30.sram_ctrl_mem_walk.827245760 Apr 16 12:53:10 PM PDT 24 Apr 16 12:53:19 PM PDT 24 142246482 ps
T15 /workspace/coverage/default/0.sram_ctrl_partial_access.1770462993 Apr 16 12:51:25 PM PDT 24 Apr 16 12:51:40 PM PDT 24 1035348996 ps
T50 /workspace/coverage/default/25.sram_ctrl_smoke.1883149601 Apr 16 12:52:38 PM PDT 24 Apr 16 12:52:42 PM PDT 24 37621721 ps
T33 /workspace/coverage/default/15.sram_ctrl_ram_cfg.2784709550 Apr 16 12:51:57 PM PDT 24 Apr 16 12:51:59 PM PDT 24 79570676 ps
T51 /workspace/coverage/default/9.sram_ctrl_partial_access_b2b.2118712534 Apr 16 12:51:39 PM PDT 24 Apr 16 12:56:44 PM PDT 24 16960563023 ps
T9 /workspace/coverage/default/4.sram_ctrl_sec_cm.1726809320 Apr 16 12:51:53 PM PDT 24 Apr 16 12:51:59 PM PDT 24 229629596 ps
T37 /workspace/coverage/default/48.sram_ctrl_multiple_keys.576057216 Apr 16 12:55:39 PM PDT 24 Apr 16 01:11:14 PM PDT 24 22962973906 ps
T17 /workspace/coverage/default/32.sram_ctrl_executable.1389103985 Apr 16 12:53:15 PM PDT 24 Apr 16 01:07:00 PM PDT 24 14335458734 ps
T38 /workspace/coverage/default/32.sram_ctrl_max_throughput.3998770492 Apr 16 12:53:19 PM PDT 24 Apr 16 12:53:23 PM PDT 24 127140656 ps
T39 /workspace/coverage/default/35.sram_ctrl_partial_access_b2b.3243295604 Apr 16 12:53:35 PM PDT 24 Apr 16 12:58:54 PM PDT 24 47636434284 ps
T40 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.1920798305 Apr 16 12:51:26 PM PDT 24 Apr 16 12:51:31 PM PDT 24 88095799 ps
T41 /workspace/coverage/default/34.sram_ctrl_stress_pipeline.2139814733 Apr 16 12:53:31 PM PDT 24 Apr 16 12:59:23 PM PDT 24 15512503432 ps
T26 /workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1602962402 Apr 16 12:51:34 PM PDT 24 Apr 16 12:54:54 PM PDT 24 5187297058 ps
T32 /workspace/coverage/default/24.sram_ctrl_executable.3242921008 Apr 16 12:52:37 PM PDT 24 Apr 16 01:01:58 PM PDT 24 36624255484 ps
T42 /workspace/coverage/default/41.sram_ctrl_executable.553878841 Apr 16 12:54:29 PM PDT 24 Apr 16 12:56:44 PM PDT 24 15713208278 ps
T6 /workspace/coverage/default/23.sram_ctrl_stress_all.1636777260 Apr 16 12:52:37 PM PDT 24 Apr 16 01:09:12 PM PDT 24 14712991872 ps
T23 /workspace/coverage/default/20.sram_ctrl_alert_test.1373794184 Apr 16 12:52:16 PM PDT 24 Apr 16 12:52:17 PM PDT 24 41678513 ps
T65 /workspace/coverage/default/42.sram_ctrl_partial_access.2212780118 Apr 16 12:54:39 PM PDT 24 Apr 16 12:55:07 PM PDT 24 1774212340 ps
T24 /workspace/coverage/default/12.sram_ctrl_alert_test.432248472 Apr 16 12:52:02 PM PDT 24 Apr 16 12:52:03 PM PDT 24 21123043 ps
T27 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.1318985224 Apr 16 12:51:53 PM PDT 24 Apr 16 12:59:31 PM PDT 24 1361449467 ps
T43 /workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1214563282 Apr 16 12:53:42 PM PDT 24 Apr 16 12:56:53 PM PDT 24 1081601134 ps
T87 /workspace/coverage/default/41.sram_ctrl_stress_pipeline.3125613234 Apr 16 12:54:30 PM PDT 24 Apr 16 12:57:26 PM PDT 24 1915950220 ps
T121 /workspace/coverage/default/43.sram_ctrl_bijection.719512050 Apr 16 12:54:44 PM PDT 24 Apr 16 12:55:15 PM PDT 24 5471863262 ps
T70 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2575123993 Apr 16 12:53:44 PM PDT 24 Apr 16 12:53:49 PM PDT 24 66544647 ps
T122 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.268604491 Apr 16 12:51:46 PM PDT 24 Apr 16 12:51:48 PM PDT 24 324239539 ps
T123 /workspace/coverage/default/12.sram_ctrl_max_throughput.3254259497 Apr 16 12:51:47 PM PDT 24 Apr 16 12:52:29 PM PDT 24 192184114 ps
T124 /workspace/coverage/default/20.sram_ctrl_multiple_keys.2770817258 Apr 16 12:52:11 PM PDT 24 Apr 16 01:01:30 PM PDT 24 12191170229 ps
T125 /workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.3751666886 Apr 16 12:53:16 PM PDT 24 Apr 16 12:54:55 PM PDT 24 605880781 ps
T114 /workspace/coverage/default/23.sram_ctrl_executable.1524333398 Apr 16 12:52:36 PM PDT 24 Apr 16 01:05:16 PM PDT 24 11253627783 ps
T44 /workspace/coverage/default/39.sram_ctrl_stress_all_with_rand_reset.3645040050 Apr 16 12:54:17 PM PDT 24 Apr 16 12:55:34 PM PDT 24 818473812 ps
T34 /workspace/coverage/default/25.sram_ctrl_ram_cfg.2229740732 Apr 16 12:52:43 PM PDT 24 Apr 16 12:52:45 PM PDT 24 45989008 ps
T126 /workspace/coverage/default/5.sram_ctrl_bijection.827567911 Apr 16 12:51:41 PM PDT 24 Apr 16 12:52:00 PM PDT 24 1396492139 ps
T88 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.4025494145 Apr 16 12:51:41 PM PDT 24 Apr 16 12:56:11 PM PDT 24 2791556747 ps
T127 /workspace/coverage/default/21.sram_ctrl_multiple_keys.282288490 Apr 16 12:52:17 PM PDT 24 Apr 16 01:08:10 PM PDT 24 11534005536 ps
T128 /workspace/coverage/default/33.sram_ctrl_ram_cfg.2383524903 Apr 16 12:53:22 PM PDT 24 Apr 16 12:53:24 PM PDT 24 151881648 ps
T129 /workspace/coverage/default/48.sram_ctrl_bijection.2218787517 Apr 16 12:55:42 PM PDT 24 Apr 16 12:56:41 PM PDT 24 3268228202 ps
T130 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.594350127 Apr 16 12:51:53 PM PDT 24 Apr 16 12:52:06 PM PDT 24 73653828 ps
T131 /workspace/coverage/default/1.sram_ctrl_bijection.3756308799 Apr 16 12:51:29 PM PDT 24 Apr 16 12:51:58 PM PDT 24 7526816089 ps
T18 /workspace/coverage/default/43.sram_ctrl_access_during_key_req.521842504 Apr 16 12:54:49 PM PDT 24 Apr 16 01:02:06 PM PDT 24 6449573240 ps
T52 /workspace/coverage/default/19.sram_ctrl_regwen.3413855951 Apr 16 12:52:12 PM PDT 24 Apr 16 01:01:15 PM PDT 24 35596427832 ps
T28 /workspace/coverage/default/25.sram_ctrl_regwen.2531399034 Apr 16 12:52:42 PM PDT 24 Apr 16 12:54:40 PM PDT 24 50477142620 ps
T7 /workspace/coverage/default/46.sram_ctrl_stress_all.1993657502 Apr 16 12:55:28 PM PDT 24 Apr 16 01:53:15 PM PDT 24 206409742009 ps
T19 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.1806753390 Apr 16 12:52:22 PM PDT 24 Apr 16 01:01:03 PM PDT 24 2468899473 ps
T20 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.2722218285 Apr 16 12:54:57 PM PDT 24 Apr 16 01:04:50 PM PDT 24 2802869918 ps
T132 /workspace/coverage/default/25.sram_ctrl_bijection.2213693480 Apr 16 12:52:37 PM PDT 24 Apr 16 12:53:36 PM PDT 24 13834654147 ps
T45 /workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.800104545 Apr 16 12:54:04 PM PDT 24 Apr 16 12:55:12 PM PDT 24 1301546412 ps
T46 /workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.3216746924 Apr 16 12:51:51 PM PDT 24 Apr 16 12:52:31 PM PDT 24 446051482 ps
T8 /workspace/coverage/default/46.sram_ctrl_lc_escalation.1287005508 Apr 16 12:55:25 PM PDT 24 Apr 16 12:55:29 PM PDT 24 506898129 ps
T133 /workspace/coverage/default/39.sram_ctrl_max_throughput.1961470513 Apr 16 12:54:09 PM PDT 24 Apr 16 12:54:49 PM PDT 24 390327094 ps
T134 /workspace/coverage/default/8.sram_ctrl_multiple_keys.3353541134 Apr 16 12:51:55 PM PDT 24 Apr 16 01:03:48 PM PDT 24 7012565913 ps
T89 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.153403711 Apr 16 12:51:43 PM PDT 24 Apr 16 12:56:41 PM PDT 24 60109931016 ps
T135 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.977663020 Apr 16 12:53:04 PM PDT 24 Apr 16 12:55:17 PM PDT 24 1237157675 ps
T115 /workspace/coverage/default/4.sram_ctrl_executable.2745251316 Apr 16 12:51:26 PM PDT 24 Apr 16 01:04:43 PM PDT 24 33283118088 ps
T136 /workspace/coverage/default/11.sram_ctrl_smoke.2922671126 Apr 16 12:51:53 PM PDT 24 Apr 16 12:52:02 PM PDT 24 1358571729 ps
T137 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.2996474341 Apr 16 12:54:43 PM PDT 24 Apr 16 12:56:24 PM PDT 24 306191480 ps
T138 /workspace/coverage/default/9.sram_ctrl_smoke.3866208273 Apr 16 12:51:45 PM PDT 24 Apr 16 12:52:00 PM PDT 24 877026830 ps
T90 /workspace/coverage/default/2.sram_ctrl_stress_pipeline.958413711 Apr 16 12:51:30 PM PDT 24 Apr 16 12:55:11 PM PDT 24 9295114059 ps
T139 /workspace/coverage/default/27.sram_ctrl_mem_walk.3292092317 Apr 16 12:52:48 PM PDT 24 Apr 16 12:53:00 PM PDT 24 2734420436 ps
T140 /workspace/coverage/default/12.sram_ctrl_smoke.2185491822 Apr 16 12:51:53 PM PDT 24 Apr 16 12:52:06 PM PDT 24 1011422296 ps
T141 /workspace/coverage/default/34.sram_ctrl_max_throughput.1705198285 Apr 16 12:53:30 PM PDT 24 Apr 16 12:53:58 PM PDT 24 90915799 ps
T142 /workspace/coverage/default/15.sram_ctrl_smoke.2109135628 Apr 16 12:51:55 PM PDT 24 Apr 16 12:52:13 PM PDT 24 1047362067 ps
T143 /workspace/coverage/default/0.sram_ctrl_bijection.162735134 Apr 16 12:51:30 PM PDT 24 Apr 16 12:51:52 PM PDT 24 335660582 ps
T116 /workspace/coverage/default/17.sram_ctrl_executable.2780510013 Apr 16 12:52:06 PM PDT 24 Apr 16 01:05:24 PM PDT 24 7758271004 ps
T53 /workspace/coverage/default/29.sram_ctrl_regwen.3220541363 Apr 16 12:53:02 PM PDT 24 Apr 16 01:03:08 PM PDT 24 35948097457 ps
T144 /workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1554108434 Apr 16 12:52:18 PM PDT 24 Apr 16 12:53:49 PM PDT 24 148463056 ps
T145 /workspace/coverage/default/32.sram_ctrl_mem_walk.274286742 Apr 16 12:53:16 PM PDT 24 Apr 16 12:53:26 PM PDT 24 578433200 ps
T31 /workspace/coverage/default/12.sram_ctrl_lc_escalation.3877158014 Apr 16 12:51:55 PM PDT 24 Apr 16 12:52:06 PM PDT 24 2706244905 ps
T146 /workspace/coverage/default/43.sram_ctrl_max_throughput.289197709 Apr 16 12:54:47 PM PDT 24 Apr 16 12:54:51 PM PDT 24 100974388 ps
T47 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.427812538 Apr 16 12:52:52 PM PDT 24 Apr 16 12:53:04 PM PDT 24 4058916884 ps
T48 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.960025624 Apr 16 12:53:29 PM PDT 24 Apr 16 12:54:04 PM PDT 24 1052976623 ps
T71 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.2604378298 Apr 16 12:53:19 PM PDT 24 Apr 16 12:53:22 PM PDT 24 567721616 ps
T147 /workspace/coverage/default/7.sram_ctrl_mem_walk.1894137312 Apr 16 12:51:45 PM PDT 24 Apr 16 12:51:50 PM PDT 24 150030234 ps
T49 /workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.2052198872 Apr 16 12:52:07 PM PDT 24 Apr 16 12:52:30 PM PDT 24 729909280 ps
T148 /workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3480068818 Apr 16 12:55:08 PM PDT 24 Apr 16 12:56:19 PM PDT 24 1484372143 ps
T149 /workspace/coverage/default/29.sram_ctrl_executable.3153945461 Apr 16 12:53:03 PM PDT 24 Apr 16 01:00:34 PM PDT 24 8609995440 ps
T72 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3249303380 Apr 16 12:52:37 PM PDT 24 Apr 16 01:00:14 PM PDT 24 3156738367 ps
T150 /workspace/coverage/default/16.sram_ctrl_smoke.4077741517 Apr 16 12:52:00 PM PDT 24 Apr 16 12:52:23 PM PDT 24 145045605 ps
T151 /workspace/coverage/default/23.sram_ctrl_partial_access.1599106390 Apr 16 12:52:30 PM PDT 24 Apr 16 12:52:34 PM PDT 24 148398455 ps
T152 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.3517443928 Apr 16 12:51:27 PM PDT 24 Apr 16 12:51:38 PM PDT 24 305577395 ps
T29 /workspace/coverage/default/11.sram_ctrl_stress_all.3835963163 Apr 16 12:51:48 PM PDT 24 Apr 16 01:33:38 PM PDT 24 17697037108 ps
T153 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.4069300494 Apr 16 12:51:49 PM PDT 24 Apr 16 12:52:24 PM PDT 24 430081121 ps
T73 /workspace/coverage/default/18.sram_ctrl_access_during_key_req.2222391219 Apr 16 12:52:12 PM PDT 24 Apr 16 01:23:52 PM PDT 24 10903598188 ps
T54 /workspace/coverage/default/35.sram_ctrl_lc_escalation.3813976290 Apr 16 12:53:37 PM PDT 24 Apr 16 12:53:45 PM PDT 24 1441830435 ps
T74 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.269615881 Apr 16 12:51:32 PM PDT 24 Apr 16 12:51:40 PM PDT 24 3244454850 ps
T154 /workspace/coverage/default/0.sram_ctrl_max_throughput.2260811182 Apr 16 12:51:29 PM PDT 24 Apr 16 12:51:33 PM PDT 24 49733801 ps
T117 /workspace/coverage/default/28.sram_ctrl_executable.2281327468 Apr 16 12:52:54 PM PDT 24 Apr 16 01:07:23 PM PDT 24 6469206342 ps
T155 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1054096397 Apr 16 12:51:26 PM PDT 24 Apr 16 12:51:33 PM PDT 24 1580342632 ps
T156 /workspace/coverage/default/45.sram_ctrl_mem_walk.10095755 Apr 16 12:55:14 PM PDT 24 Apr 16 12:55:20 PM PDT 24 257787697 ps
T157 /workspace/coverage/default/0.sram_ctrl_smoke.1795820411 Apr 16 12:51:32 PM PDT 24 Apr 16 12:53:23 PM PDT 24 981798494 ps
T91 /workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1862886524 Apr 16 12:53:41 PM PDT 24 Apr 16 12:59:01 PM PDT 24 4639213095 ps
T25 /workspace/coverage/default/3.sram_ctrl_alert_test.533701905 Apr 16 12:51:32 PM PDT 24 Apr 16 12:51:34 PM PDT 24 29276624 ps
T158 /workspace/coverage/default/37.sram_ctrl_partial_access.458713581 Apr 16 12:53:53 PM PDT 24 Apr 16 12:54:03 PM PDT 24 207715228 ps
T159 /workspace/coverage/default/22.sram_ctrl_bijection.4223290257 Apr 16 12:52:21 PM PDT 24 Apr 16 12:53:19 PM PDT 24 1754443887 ps
T160 /workspace/coverage/default/10.sram_ctrl_access_during_key_req.2838968623 Apr 16 12:51:47 PM PDT 24 Apr 16 01:04:39 PM PDT 24 8628168236 ps
T161 /workspace/coverage/default/14.sram_ctrl_lc_escalation.2226053731 Apr 16 12:51:56 PM PDT 24 Apr 16 12:52:05 PM PDT 24 6448676455 ps
T162 /workspace/coverage/default/48.sram_ctrl_smoke.2130680264 Apr 16 12:55:42 PM PDT 24 Apr 16 12:55:44 PM PDT 24 128846097 ps
T119 /workspace/coverage/default/33.sram_ctrl_executable.2861259120 Apr 16 12:53:22 PM PDT 24 Apr 16 01:11:14 PM PDT 24 3991159280 ps
T30 /workspace/coverage/default/5.sram_ctrl_stress_all.399535891 Apr 16 12:51:52 PM PDT 24 Apr 16 01:21:34 PM PDT 24 95155554214 ps
T163 /workspace/coverage/default/18.sram_ctrl_alert_test.2945105641 Apr 16 12:52:17 PM PDT 24 Apr 16 12:52:19 PM PDT 24 41471110 ps
T164 /workspace/coverage/default/22.sram_ctrl_alert_test.2117592899 Apr 16 12:52:30 PM PDT 24 Apr 16 12:52:32 PM PDT 24 70522780 ps
T165 /workspace/coverage/default/19.sram_ctrl_access_during_key_req.4191341986 Apr 16 12:52:12 PM PDT 24 Apr 16 01:00:01 PM PDT 24 6898542236 ps
T166 /workspace/coverage/default/15.sram_ctrl_bijection.4006450832 Apr 16 12:51:59 PM PDT 24 Apr 16 12:52:44 PM PDT 24 1392502098 ps
T167 /workspace/coverage/default/47.sram_ctrl_max_throughput.1014461791 Apr 16 12:55:33 PM PDT 24 Apr 16 12:56:15 PM PDT 24 346774935 ps
T168 /workspace/coverage/default/46.sram_ctrl_ram_cfg.3083383366 Apr 16 12:55:27 PM PDT 24 Apr 16 12:55:29 PM PDT 24 30372612 ps
T169 /workspace/coverage/default/6.sram_ctrl_ram_cfg.3072152303 Apr 16 12:51:39 PM PDT 24 Apr 16 12:51:41 PM PDT 24 87119596 ps
T170 /workspace/coverage/default/12.sram_ctrl_mem_walk.4006734586 Apr 16 12:51:56 PM PDT 24 Apr 16 12:52:02 PM PDT 24 446237515 ps
T171 /workspace/coverage/default/1.sram_ctrl_ram_cfg.4128758212 Apr 16 12:51:22 PM PDT 24 Apr 16 12:51:24 PM PDT 24 53372752 ps
T172 /workspace/coverage/default/27.sram_ctrl_access_during_key_req.4170786047 Apr 16 12:52:50 PM PDT 24 Apr 16 01:04:11 PM PDT 24 4187247801 ps
T173 /workspace/coverage/default/17.sram_ctrl_partial_access.814814172 Apr 16 12:52:07 PM PDT 24 Apr 16 12:52:17 PM PDT 24 189017211 ps
T174 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.2134986538 Apr 16 12:53:37 PM PDT 24 Apr 16 01:00:23 PM PDT 24 3713256335 ps
T175 /workspace/coverage/default/11.sram_ctrl_multiple_keys.2583269896 Apr 16 12:51:48 PM PDT 24 Apr 16 12:53:47 PM PDT 24 7759348892 ps
T120 /workspace/coverage/default/34.sram_ctrl_stress_all.1906247357 Apr 16 12:53:39 PM PDT 24 Apr 16 01:38:50 PM PDT 24 50221667439 ps
T176 /workspace/coverage/default/8.sram_ctrl_mem_walk.902251022 Apr 16 12:51:45 PM PDT 24 Apr 16 12:51:54 PM PDT 24 204223037 ps
T177 /workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.2010535596 Apr 16 12:53:37 PM PDT 24 Apr 16 12:55:48 PM PDT 24 299103737 ps
T178 /workspace/coverage/default/20.sram_ctrl_mem_walk.2759868056 Apr 16 12:52:15 PM PDT 24 Apr 16 12:52:24 PM PDT 24 2617230690 ps
T179 /workspace/coverage/default/45.sram_ctrl_smoke.2429058125 Apr 16 12:55:08 PM PDT 24 Apr 16 12:55:26 PM PDT 24 908504109 ps
T118 /workspace/coverage/default/19.sram_ctrl_stress_all.2196277292 Apr 16 12:52:11 PM PDT 24 Apr 16 01:23:09 PM PDT 24 180883036822 ps
T180 /workspace/coverage/default/44.sram_ctrl_mem_partial_access.3330688662 Apr 16 12:55:10 PM PDT 24 Apr 16 12:55:13 PM PDT 24 98723564 ps
T181 /workspace/coverage/default/37.sram_ctrl_access_during_key_req.94456657 Apr 16 12:53:56 PM PDT 24 Apr 16 01:06:55 PM PDT 24 3250669391 ps
T182 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.1816688897 Apr 16 12:53:32 PM PDT 24 Apr 16 12:53:36 PM PDT 24 253173031 ps
T183 /workspace/coverage/default/16.sram_ctrl_ram_cfg.3403061029 Apr 16 12:52:05 PM PDT 24 Apr 16 12:52:07 PM PDT 24 48190630 ps
T184 /workspace/coverage/default/19.sram_ctrl_executable.2850854113 Apr 16 12:52:14 PM PDT 24 Apr 16 01:03:03 PM PDT 24 19074967374 ps
T97 /workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.3957779967 Apr 16 12:52:02 PM PDT 24 Apr 16 12:52:45 PM PDT 24 3174595031 ps
T185 /workspace/coverage/default/9.sram_ctrl_max_throughput.991446650 Apr 16 12:51:50 PM PDT 24 Apr 16 12:52:47 PM PDT 24 116967897 ps
T186 /workspace/coverage/default/10.sram_ctrl_ram_cfg.640554458 Apr 16 12:51:51 PM PDT 24 Apr 16 12:51:53 PM PDT 24 74184653 ps
T92 /workspace/coverage/default/43.sram_ctrl_stress_pipeline.2805704912 Apr 16 12:54:46 PM PDT 24 Apr 16 12:57:37 PM PDT 24 2098505627 ps
T187 /workspace/coverage/default/0.sram_ctrl_multiple_keys.955351955 Apr 16 12:51:26 PM PDT 24 Apr 16 01:17:40 PM PDT 24 22978851994 ps
T188 /workspace/coverage/default/1.sram_ctrl_alert_test.388190665 Apr 16 12:51:29 PM PDT 24 Apr 16 12:51:32 PM PDT 24 20674826 ps
T189 /workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.310703730 Apr 16 12:54:27 PM PDT 24 Apr 16 12:56:07 PM PDT 24 1479952301 ps
T190 /workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2858196013 Apr 16 12:51:49 PM PDT 24 Apr 16 01:06:14 PM PDT 24 9553623435 ps
T191 /workspace/coverage/default/43.sram_ctrl_regwen.2823909874 Apr 16 12:54:48 PM PDT 24 Apr 16 01:04:57 PM PDT 24 41669598961 ps
T192 /workspace/coverage/default/27.sram_ctrl_stress_all.2009521960 Apr 16 12:52:55 PM PDT 24 Apr 16 01:21:26 PM PDT 24 144310405085 ps
T193 /workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.1738860375 Apr 16 12:52:58 PM PDT 24 Apr 16 12:53:47 PM PDT 24 616009260 ps
T194 /workspace/coverage/default/34.sram_ctrl_mem_walk.1148903040 Apr 16 12:53:29 PM PDT 24 Apr 16 12:53:35 PM PDT 24 449570610 ps
T195 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.2782315242 Apr 16 12:52:48 PM PDT 24 Apr 16 12:52:52 PM PDT 24 184079734 ps
T196 /workspace/coverage/default/2.sram_ctrl_mem_walk.2524838392 Apr 16 12:51:30 PM PDT 24 Apr 16 12:51:40 PM PDT 24 494153968 ps
T197 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.2553005135 Apr 16 12:52:30 PM PDT 24 Apr 16 12:52:34 PM PDT 24 89407264 ps
T198 /workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.1993235401 Apr 16 12:53:42 PM PDT 24 Apr 16 12:53:51 PM PDT 24 544279466 ps
T199 /workspace/coverage/default/24.sram_ctrl_stress_all.3392391194 Apr 16 12:52:35 PM PDT 24 Apr 16 01:15:15 PM PDT 24 71810585966 ps
T200 /workspace/coverage/default/9.sram_ctrl_partial_access.488747481 Apr 16 12:51:39 PM PDT 24 Apr 16 12:51:45 PM PDT 24 64091028 ps
T201 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1303643189 Apr 16 12:52:11 PM PDT 24 Apr 16 12:52:17 PM PDT 24 212581811 ps
T202 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.1146066301 Apr 16 12:51:46 PM PDT 24 Apr 16 12:51:50 PM PDT 24 167074367 ps
T203 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.3695400290 Apr 16 12:53:22 PM PDT 24 Apr 16 01:08:21 PM PDT 24 5457935185 ps
T204 /workspace/coverage/default/24.sram_ctrl_lc_escalation.2644107250 Apr 16 12:52:38 PM PDT 24 Apr 16 12:52:42 PM PDT 24 193521104 ps
T205 /workspace/coverage/default/37.sram_ctrl_lc_escalation.3808311327 Apr 16 12:53:55 PM PDT 24 Apr 16 12:53:57 PM PDT 24 141856110 ps
T206 /workspace/coverage/default/13.sram_ctrl_max_throughput.4054882483 Apr 16 12:51:51 PM PDT 24 Apr 16 12:52:00 PM PDT 24 445141653 ps
T207 /workspace/coverage/default/25.sram_ctrl_access_during_key_req.2660959775 Apr 16 12:52:43 PM PDT 24 Apr 16 01:06:36 PM PDT 24 3532395923 ps
T208 /workspace/coverage/default/37.sram_ctrl_mem_partial_access.1145745471 Apr 16 12:53:59 PM PDT 24 Apr 16 12:54:04 PM PDT 24 586334858 ps
T209 /workspace/coverage/default/39.sram_ctrl_partial_access.1594606874 Apr 16 12:54:09 PM PDT 24 Apr 16 12:54:17 PM PDT 24 416282903 ps
T210 /workspace/coverage/default/43.sram_ctrl_mem_walk.1634098048 Apr 16 12:54:48 PM PDT 24 Apr 16 12:54:53 PM PDT 24 284942317 ps
T211 /workspace/coverage/default/2.sram_ctrl_multiple_keys.1833111145 Apr 16 12:51:36 PM PDT 24 Apr 16 01:03:44 PM PDT 24 21739741771 ps
T212 /workspace/coverage/default/34.sram_ctrl_access_during_key_req.4099103468 Apr 16 12:53:29 PM PDT 24 Apr 16 01:06:12 PM PDT 24 29386846877 ps
T213 /workspace/coverage/default/25.sram_ctrl_stress_pipeline.3077249101 Apr 16 12:52:35 PM PDT 24 Apr 16 12:57:00 PM PDT 24 5462161620 ps
T214 /workspace/coverage/default/19.sram_ctrl_multiple_keys.1353066576 Apr 16 12:52:18 PM PDT 24 Apr 16 01:05:15 PM PDT 24 15807395017 ps
T215 /workspace/coverage/default/26.sram_ctrl_executable.3784043055 Apr 16 12:52:45 PM PDT 24 Apr 16 01:10:18 PM PDT 24 88797312485 ps
T216 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3524064060 Apr 16 12:51:47 PM PDT 24 Apr 16 12:53:39 PM PDT 24 295164462 ps
T217 /workspace/coverage/default/29.sram_ctrl_smoke.1018642450 Apr 16 12:53:02 PM PDT 24 Apr 16 12:53:49 PM PDT 24 104213370 ps
T218 /workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.4017262200 Apr 16 12:52:23 PM PDT 24 Apr 16 12:52:58 PM PDT 24 201777380 ps
T219 /workspace/coverage/default/5.sram_ctrl_multiple_keys.1995970841 Apr 16 12:51:46 PM PDT 24 Apr 16 01:07:47 PM PDT 24 3944468655 ps
T220 /workspace/coverage/default/20.sram_ctrl_lc_escalation.3968373565 Apr 16 12:52:18 PM PDT 24 Apr 16 12:52:24 PM PDT 24 895599858 ps
T221 /workspace/coverage/default/11.sram_ctrl_partial_access_b2b.20004950 Apr 16 12:51:47 PM PDT 24 Apr 16 12:58:37 PM PDT 24 18869906941 ps
T222 /workspace/coverage/default/23.sram_ctrl_alert_test.98060715 Apr 16 12:52:37 PM PDT 24 Apr 16 12:52:40 PM PDT 24 21087265 ps
T223 /workspace/coverage/default/48.sram_ctrl_mem_walk.4288188550 Apr 16 12:55:50 PM PDT 24 Apr 16 12:55:55 PM PDT 24 71959811 ps
T224 /workspace/coverage/default/13.sram_ctrl_lc_escalation.949151312 Apr 16 12:51:55 PM PDT 24 Apr 16 12:52:07 PM PDT 24 1202959700 ps
T98 /workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.2454051768 Apr 16 12:51:40 PM PDT 24 Apr 16 12:53:05 PM PDT 24 1781740540 ps
T225 /workspace/coverage/default/37.sram_ctrl_mem_walk.1384536691 Apr 16 12:53:57 PM PDT 24 Apr 16 12:54:03 PM PDT 24 1139531320 ps
T226 /workspace/coverage/default/20.sram_ctrl_partial_access.623731205 Apr 16 12:52:14 PM PDT 24 Apr 16 12:52:29 PM PDT 24 1242137762 ps
T227 /workspace/coverage/default/29.sram_ctrl_mem_partial_access.1968783681 Apr 16 12:53:03 PM PDT 24 Apr 16 12:53:06 PM PDT 24 88177232 ps
T228 /workspace/coverage/default/13.sram_ctrl_stress_all.905354357 Apr 16 12:51:51 PM PDT 24 Apr 16 01:15:51 PM PDT 24 28233421709 ps
T229 /workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.2945014370 Apr 16 12:53:23 PM PDT 24 Apr 16 12:53:53 PM PDT 24 199926729 ps
T99 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.536247683 Apr 16 12:52:18 PM PDT 24 Apr 16 12:53:55 PM PDT 24 5534953187 ps
T230 /workspace/coverage/default/34.sram_ctrl_partial_access.1585543911 Apr 16 12:53:29 PM PDT 24 Apr 16 12:53:41 PM PDT 24 674577877 ps
T231 /workspace/coverage/default/28.sram_ctrl_smoke.4000594855 Apr 16 12:52:56 PM PDT 24 Apr 16 12:53:50 PM PDT 24 117735468 ps
T232 /workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1171282634 Apr 16 12:52:42 PM PDT 24 Apr 16 12:53:49 PM PDT 24 569631341 ps
T233 /workspace/coverage/default/14.sram_ctrl_regwen.2900376053 Apr 16 12:52:01 PM PDT 24 Apr 16 12:57:15 PM PDT 24 13042405094 ps
T234 /workspace/coverage/default/30.sram_ctrl_smoke.2396808599 Apr 16 12:53:04 PM PDT 24 Apr 16 12:53:21 PM PDT 24 1088715541 ps
T235 /workspace/coverage/default/20.sram_ctrl_ram_cfg.1466449129 Apr 16 12:52:17 PM PDT 24 Apr 16 12:52:19 PM PDT 24 136829857 ps
T236 /workspace/coverage/default/41.sram_ctrl_multiple_keys.4267481301 Apr 16 12:54:28 PM PDT 24 Apr 16 01:12:46 PM PDT 24 16926968289 ps
T237 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.1725482603 Apr 16 12:54:56 PM PDT 24 Apr 16 01:02:19 PM PDT 24 12973715172 ps
T238 /workspace/coverage/default/1.sram_ctrl_multiple_keys.3253221498 Apr 16 12:51:31 PM PDT 24 Apr 16 12:55:31 PM PDT 24 1649022797 ps
T239 /workspace/coverage/default/5.sram_ctrl_regwen.3963031609 Apr 16 12:51:51 PM PDT 24 Apr 16 01:18:46 PM PDT 24 7725051887 ps
T240 /workspace/coverage/default/35.sram_ctrl_executable.3849056630 Apr 16 12:53:42 PM PDT 24 Apr 16 01:18:22 PM PDT 24 50997906195 ps
T241 /workspace/coverage/default/12.sram_ctrl_stress_pipeline.3871377021 Apr 16 12:51:50 PM PDT 24 Apr 16 12:55:07 PM PDT 24 4712502110 ps
T242 /workspace/coverage/default/49.sram_ctrl_mem_walk.2470201127 Apr 16 12:55:56 PM PDT 24 Apr 16 12:56:06 PM PDT 24 1127906320 ps
T243 /workspace/coverage/default/21.sram_ctrl_alert_test.3039363344 Apr 16 12:52:24 PM PDT 24 Apr 16 12:52:26 PM PDT 24 22735811 ps
T244 /workspace/coverage/default/30.sram_ctrl_executable.3488235450 Apr 16 12:53:12 PM PDT 24 Apr 16 01:11:42 PM PDT 24 10109180538 ps
T245 /workspace/coverage/default/17.sram_ctrl_stress_all.1139648316 Apr 16 12:52:14 PM PDT 24 Apr 16 02:03:40 PM PDT 24 66004228287 ps
T246 /workspace/coverage/default/35.sram_ctrl_partial_access.3854978897 Apr 16 12:53:35 PM PDT 24 Apr 16 12:55:38 PM PDT 24 230549135 ps
T247 /workspace/coverage/default/24.sram_ctrl_max_throughput.3963070590 Apr 16 12:52:36 PM PDT 24 Apr 16 12:53:00 PM PDT 24 166529059 ps
T248 /workspace/coverage/default/10.sram_ctrl_bijection.1107755601 Apr 16 12:51:52 PM PDT 24 Apr 16 12:52:34 PM PDT 24 3659401951 ps
T249 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.4030515932 Apr 16 12:51:58 PM PDT 24 Apr 16 01:00:42 PM PDT 24 2151001301 ps
T250 /workspace/coverage/default/26.sram_ctrl_stress_all.387621735 Apr 16 12:52:51 PM PDT 24 Apr 16 01:02:41 PM PDT 24 9927608006 ps
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T252 /workspace/coverage/default/43.sram_ctrl_partial_access_b2b.1238156066 Apr 16 12:54:44 PM PDT 24 Apr 16 12:59:25 PM PDT 24 49472177907 ps
T253 /workspace/coverage/default/48.sram_ctrl_lc_escalation.1417373269 Apr 16 12:55:46 PM PDT 24 Apr 16 12:55:54 PM PDT 24 2527738782 ps
T254 /workspace/coverage/default/2.sram_ctrl_alert_test.2884838396 Apr 16 12:51:26 PM PDT 24 Apr 16 12:51:28 PM PDT 24 39052712 ps
T255 /workspace/coverage/default/38.sram_ctrl_regwen.3051220101 Apr 16 12:54:04 PM PDT 24 Apr 16 12:59:17 PM PDT 24 25069339566 ps
T256 /workspace/coverage/default/1.sram_ctrl_stress_pipeline.542198394 Apr 16 12:51:20 PM PDT 24 Apr 16 12:54:12 PM PDT 24 1911034519 ps
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T258 /workspace/coverage/default/48.sram_ctrl_regwen.2541613255 Apr 16 12:55:47 PM PDT 24 Apr 16 01:08:50 PM PDT 24 69280536599 ps
T259 /workspace/coverage/default/33.sram_ctrl_alert_test.1910996876 Apr 16 12:53:28 PM PDT 24 Apr 16 12:53:29 PM PDT 24 13287637 ps
T260 /workspace/coverage/default/18.sram_ctrl_stress_all.3291529660 Apr 16 12:52:12 PM PDT 24 Apr 16 01:21:32 PM PDT 24 6429917254 ps
T261 /workspace/coverage/default/11.sram_ctrl_executable.529787199 Apr 16 12:51:54 PM PDT 24 Apr 16 01:07:03 PM PDT 24 13281640450 ps
T262 /workspace/coverage/default/13.sram_ctrl_mem_walk.2239068942 Apr 16 12:51:58 PM PDT 24 Apr 16 12:52:04 PM PDT 24 71751242 ps
T263 /workspace/coverage/default/39.sram_ctrl_mem_walk.1390491870 Apr 16 12:54:16 PM PDT 24 Apr 16 12:54:22 PM PDT 24 932670070 ps
T264 /workspace/coverage/default/36.sram_ctrl_access_during_key_req.4085732392 Apr 16 12:53:45 PM PDT 24 Apr 16 01:02:59 PM PDT 24 3328443301 ps
T265 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1528216861 Apr 16 12:53:16 PM PDT 24 Apr 16 12:56:49 PM PDT 24 4724069556 ps
T266 /workspace/coverage/default/29.sram_ctrl_stress_pipeline.3167549314 Apr 16 12:53:03 PM PDT 24 Apr 16 12:59:26 PM PDT 24 17971107529 ps
T267 /workspace/coverage/default/47.sram_ctrl_regwen.2647158234 Apr 16 12:55:35 PM PDT 24 Apr 16 01:03:28 PM PDT 24 19862528029 ps
T268 /workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3749104844 Apr 16 12:54:33 PM PDT 24 Apr 16 12:55:19 PM PDT 24 1907560536 ps
T269 /workspace/coverage/default/33.sram_ctrl_partial_access.2790173184 Apr 16 12:53:22 PM PDT 24 Apr 16 12:53:40 PM PDT 24 1659143694 ps
T270 /workspace/coverage/default/1.sram_ctrl_smoke.2743122955 Apr 16 12:51:27 PM PDT 24 Apr 16 12:51:45 PM PDT 24 709316070 ps
T271 /workspace/coverage/default/27.sram_ctrl_max_throughput.563063939 Apr 16 12:52:53 PM PDT 24 Apr 16 12:52:56 PM PDT 24 201249565 ps
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T273 /workspace/coverage/default/13.sram_ctrl_partial_access.1002062748 Apr 16 12:51:55 PM PDT 24 Apr 16 12:52:10 PM PDT 24 332616186 ps
T274 /workspace/coverage/default/1.sram_ctrl_regwen.1403070275 Apr 16 12:51:33 PM PDT 24 Apr 16 01:02:51 PM PDT 24 85914932436 ps
T275 /workspace/coverage/default/22.sram_ctrl_partial_access_b2b.962780742 Apr 16 12:52:25 PM PDT 24 Apr 16 12:59:00 PM PDT 24 59851421573 ps
T276 /workspace/coverage/default/1.sram_ctrl_partial_access.279098207 Apr 16 12:51:30 PM PDT 24 Apr 16 12:51:52 PM PDT 24 4775733714 ps
T277 /workspace/coverage/default/12.sram_ctrl_multiple_keys.912721607 Apr 16 12:51:52 PM PDT 24 Apr 16 01:02:55 PM PDT 24 19485156625 ps
T278 /workspace/coverage/default/19.sram_ctrl_alert_test.713752587 Apr 16 12:52:11 PM PDT 24 Apr 16 12:52:12 PM PDT 24 13161578 ps
T279 /workspace/coverage/default/49.sram_ctrl_executable.1008580273 Apr 16 12:55:56 PM PDT 24 Apr 16 01:04:51 PM PDT 24 24505652150 ps
T280 /workspace/coverage/default/4.sram_ctrl_stress_pipeline.3206364307 Apr 16 12:51:42 PM PDT 24 Apr 16 12:54:17 PM PDT 24 2969492064 ps
T281 /workspace/coverage/default/41.sram_ctrl_ram_cfg.4211140039 Apr 16 12:54:32 PM PDT 24 Apr 16 12:54:34 PM PDT 24 172946950 ps
T282 /workspace/coverage/default/35.sram_ctrl_stress_all.3863794096 Apr 16 12:53:45 PM PDT 24 Apr 16 01:31:30 PM PDT 24 45177388598 ps
T283 /workspace/coverage/default/22.sram_ctrl_mem_walk.1938718387 Apr 16 12:52:29 PM PDT 24 Apr 16 12:52:39 PM PDT 24 872662588 ps
T284 /workspace/coverage/default/48.sram_ctrl_partial_access_b2b.3689405501 Apr 16 12:55:45 PM PDT 24 Apr 16 01:01:15 PM PDT 24 26742000381 ps
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T286 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2660950161 Apr 16 12:52:01 PM PDT 24 Apr 16 01:02:40 PM PDT 24 56788173075 ps
T287 /workspace/coverage/default/47.sram_ctrl_alert_test.2094471489 Apr 16 12:55:41 PM PDT 24 Apr 16 12:55:42 PM PDT 24 12759674 ps
T288 /workspace/coverage/default/14.sram_ctrl_mem_partial_access.2519266015 Apr 16 12:51:51 PM PDT 24 Apr 16 12:51:57 PM PDT 24 698158714 ps
T289 /workspace/coverage/default/20.sram_ctrl_smoke.94853946 Apr 16 12:52:13 PM PDT 24 Apr 16 12:53:36 PM PDT 24 510196401 ps
T290 /workspace/coverage/default/42.sram_ctrl_regwen.685314065 Apr 16 12:54:40 PM PDT 24 Apr 16 12:55:42 PM PDT 24 659471993 ps
T291 /workspace/coverage/default/14.sram_ctrl_alert_test.2617916187 Apr 16 12:51:49 PM PDT 24 Apr 16 12:51:51 PM PDT 24 48304501 ps
T292 /workspace/coverage/default/26.sram_ctrl_ram_cfg.3617019115 Apr 16 12:52:46 PM PDT 24 Apr 16 12:52:48 PM PDT 24 165143481 ps
T293 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3131637675 Apr 16 12:52:18 PM PDT 24 Apr 16 12:57:49 PM PDT 24 18420655409 ps
T294 /workspace/coverage/default/26.sram_ctrl_alert_test.3717353687 Apr 16 12:52:51 PM PDT 24 Apr 16 12:52:52 PM PDT 24 46395250 ps
T295 /workspace/coverage/default/16.sram_ctrl_alert_test.666416242 Apr 16 12:52:05 PM PDT 24 Apr 16 12:52:07 PM PDT 24 48621581 ps
T296 /workspace/coverage/default/24.sram_ctrl_stress_pipeline.3027961678 Apr 16 12:52:36 PM PDT 24 Apr 16 12:54:27 PM PDT 24 2348536691 ps
T297 /workspace/coverage/default/8.sram_ctrl_alert_test.625182911 Apr 16 12:51:45 PM PDT 24 Apr 16 12:51:46 PM PDT 24 37855631 ps
T298 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1302766066 Apr 16 12:51:29 PM PDT 24 Apr 16 12:51:34 PM PDT 24 582519089 ps
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