Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	45222086	1			T2	6688		T3	58847		T4	42727
triple_byte_access	2625130	1			T2	135		T3	1159		T4	38545
halfword_access	3940625	1			T2	202		T3	1746		T4	57838
byte_access	5260145	1			T2	245		T3	2365		T4	77635
zero_access	1325007	1			T2	69		T3	548		T4	19128

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29130224

1

T2

3647

T3

32494

T4

118040

auto[1]

29242769

1

T2

3692

T3

32171

T4

117833

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	22558430	1			T2	3339		T3	29571		T4	21385
auto[0]	triple_byte_access	1308643	1			T2	59		T3	574		T4	19313
auto[0]	halfword_access	1966507	1			T2	106		T3	897		T4	28784
auto[0]	byte_access	2630137	1			T2	120		T3	1198		T4	38922
auto[0]	zero_access	666507	1			T2	23		T3	254		T4	9636
auto[1]	word_access	22663656	1			T2	3349		T3	29276		T4	21342
auto[1]	triple_byte_access	1316487	1			T2	76		T3	585		T4	19232
auto[1]	halfword_access	1974118	1			T2	96		T3	849		T4	29054
auto[1]	byte_access	2630008	1			T2	125		T3	1167		T4	38713
auto[1]	zero_access	658500	1			T2	46		T3	294		T4	9492