| T792 |
/workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.3399978091 |
|
|
Apr 16 12:53:57 PM PDT 24 |
Apr 16 12:54:34 PM PDT 24 |
174613978 ps |
| T793 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3943914790 |
|
|
Apr 16 12:55:13 PM PDT 24 |
Apr 16 12:55:15 PM PDT 24 |
220699740 ps |
| T794 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1127251360 |
|
|
Apr 16 12:53:02 PM PDT 24 |
Apr 16 12:54:57 PM PDT 24 |
6818410079 ps |
| T795 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.1427273530 |
|
|
Apr 16 12:51:47 PM PDT 24 |
Apr 16 12:51:50 PM PDT 24 |
41489508 ps |
| T796 |
/workspace/coverage/default/21.sram_ctrl_stress_all.3014305289 |
|
|
Apr 16 12:52:23 PM PDT 24 |
Apr 16 01:29:33 PM PDT 24 |
39580738186 ps |
| T797 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.2395604507 |
|
|
Apr 16 12:53:13 PM PDT 24 |
Apr 16 12:54:00 PM PDT 24 |
357562126 ps |
| T798 |
/workspace/coverage/default/21.sram_ctrl_executable.1900390011 |
|
|
Apr 16 12:52:21 PM PDT 24 |
Apr 16 01:13:01 PM PDT 24 |
93019252336 ps |
| T799 |
/workspace/coverage/default/3.sram_ctrl_bijection.3726161338 |
|
|
Apr 16 12:51:27 PM PDT 24 |
Apr 16 12:52:08 PM PDT 24 |
2473278948 ps |
| T800 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.1818868682 |
|
|
Apr 16 12:51:18 PM PDT 24 |
Apr 16 12:51:24 PM PDT 24 |
303480877 ps |
| T801 |
/workspace/coverage/default/40.sram_ctrl_regwen.1503196872 |
|
|
Apr 16 12:54:28 PM PDT 24 |
Apr 16 01:05:01 PM PDT 24 |
6865955626 ps |
| T802 |
/workspace/coverage/default/46.sram_ctrl_bijection.1990891381 |
|
|
Apr 16 12:55:26 PM PDT 24 |
Apr 16 12:56:02 PM PDT 24 |
4171377079 ps |
| T803 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.466340696 |
|
|
Apr 16 12:53:11 PM PDT 24 |
Apr 16 12:53:51 PM PDT 24 |
113303199 ps |
| T804 |
/workspace/coverage/default/27.sram_ctrl_smoke.743262352 |
|
|
Apr 16 12:52:49 PM PDT 24 |
Apr 16 12:52:54 PM PDT 24 |
797730666 ps |
| T805 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.1636877484 |
|
|
Apr 16 12:51:58 PM PDT 24 |
Apr 16 12:57:11 PM PDT 24 |
21891656752 ps |
| T806 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2069693172 |
|
|
Apr 16 12:51:47 PM PDT 24 |
Apr 16 12:52:14 PM PDT 24 |
346013227 ps |
| T807 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.2811099502 |
|
|
Apr 16 12:53:03 PM PDT 24 |
Apr 16 12:54:13 PM PDT 24 |
425929757 ps |
| T808 |
/workspace/coverage/default/7.sram_ctrl_alert_test.1382743085 |
|
|
Apr 16 12:51:46 PM PDT 24 |
Apr 16 12:51:48 PM PDT 24 |
13889773 ps |
| T809 |
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.3475864411 |
|
|
Apr 16 12:51:43 PM PDT 24 |
Apr 16 01:10:27 PM PDT 24 |
12903023698 ps |
| T810 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2837183268 |
|
|
Apr 16 12:54:28 PM PDT 24 |
Apr 16 12:56:20 PM PDT 24 |
1835114719 ps |
| T811 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.4277105102 |
|
|
Apr 16 12:51:16 PM PDT 24 |
Apr 16 12:51:18 PM PDT 24 |
71223183 ps |
| T812 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.1379985131 |
|
|
Apr 16 12:54:11 PM PDT 24 |
Apr 16 12:56:20 PM PDT 24 |
1324589784 ps |
| T813 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.249759467 |
|
|
Apr 16 12:51:55 PM PDT 24 |
Apr 16 12:58:36 PM PDT 24 |
16415674169 ps |
| T814 |
/workspace/coverage/default/3.sram_ctrl_executable.2085671462 |
|
|
Apr 16 12:51:42 PM PDT 24 |
Apr 16 01:01:33 PM PDT 24 |
15273145210 ps |
| T815 |
/workspace/coverage/default/10.sram_ctrl_partial_access.647222557 |
|
|
Apr 16 12:51:50 PM PDT 24 |
Apr 16 12:51:58 PM PDT 24 |
1383433582 ps |
| T816 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.2866795107 |
|
|
Apr 16 12:52:13 PM PDT 24 |
Apr 16 12:52:22 PM PDT 24 |
540995203 ps |
| T817 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.1715333161 |
|
|
Apr 16 12:53:10 PM PDT 24 |
Apr 16 12:53:12 PM PDT 24 |
49449189 ps |
| T818 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1455244777 |
|
|
Apr 16 12:53:51 PM PDT 24 |
Apr 16 01:00:41 PM PDT 24 |
32341086642 ps |
| T819 |
/workspace/coverage/default/45.sram_ctrl_executable.3089548822 |
|
|
Apr 16 12:55:14 PM PDT 24 |
Apr 16 01:08:34 PM PDT 24 |
89779644073 ps |
| T820 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.741928927 |
|
|
Apr 16 12:54:57 PM PDT 24 |
Apr 16 12:55:06 PM PDT 24 |
173160943 ps |
| T821 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.3567245097 |
|
|
Apr 16 12:52:25 PM PDT 24 |
Apr 16 12:52:34 PM PDT 24 |
135579447 ps |
| T822 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.3578326788 |
|
|
Apr 16 12:51:58 PM PDT 24 |
Apr 16 12:52:00 PM PDT 24 |
94914883 ps |
| T823 |
/workspace/coverage/default/33.sram_ctrl_stress_all.4036883413 |
|
|
Apr 16 12:53:28 PM PDT 24 |
Apr 16 01:16:19 PM PDT 24 |
5487876199 ps |
| T824 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.419188199 |
|
|
Apr 16 12:53:23 PM PDT 24 |
Apr 16 12:58:33 PM PDT 24 |
49167697047 ps |
| T825 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.517245695 |
|
|
Apr 16 12:54:40 PM PDT 24 |
Apr 16 12:54:41 PM PDT 24 |
78511816 ps |
| T826 |
/workspace/coverage/default/10.sram_ctrl_regwen.3287849448 |
|
|
Apr 16 12:51:49 PM PDT 24 |
Apr 16 01:04:59 PM PDT 24 |
6685569175 ps |
| T827 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1348710125 |
|
|
Apr 16 12:51:59 PM PDT 24 |
Apr 16 12:56:31 PM PDT 24 |
12510795508 ps |
| T828 |
/workspace/coverage/default/41.sram_ctrl_alert_test.2812262212 |
|
|
Apr 16 12:54:39 PM PDT 24 |
Apr 16 12:54:41 PM PDT 24 |
15844934 ps |
| T829 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.217158618 |
|
|
Apr 16 12:55:36 PM PDT 24 |
Apr 16 01:10:12 PM PDT 24 |
8012592487 ps |
| T830 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2737288024 |
|
|
Apr 16 12:51:53 PM PDT 24 |
Apr 16 12:53:13 PM PDT 24 |
6554515625 ps |
| T831 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.345824276 |
|
|
Apr 16 12:53:36 PM PDT 24 |
Apr 16 01:04:09 PM PDT 24 |
6218369807 ps |
| T832 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.3432422398 |
|
|
Apr 16 12:55:15 PM PDT 24 |
Apr 16 12:55:20 PM PDT 24 |
221993177 ps |
| T833 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.4180804250 |
|
|
Apr 16 12:53:48 PM PDT 24 |
Apr 16 12:55:30 PM PDT 24 |
4311258355 ps |
| T834 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.3827140383 |
|
|
Apr 16 12:54:37 PM PDT 24 |
Apr 16 12:54:41 PM PDT 24 |
102527883 ps |
| T835 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.2458358903 |
|
|
Apr 16 12:53:02 PM PDT 24 |
Apr 16 01:02:03 PM PDT 24 |
46253014436 ps |
| T836 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.3057648271 |
|
|
Apr 16 12:51:47 PM PDT 24 |
Apr 16 12:51:52 PM PDT 24 |
96714549 ps |
| T837 |
/workspace/coverage/default/13.sram_ctrl_executable.4088440074 |
|
|
Apr 16 12:51:52 PM PDT 24 |
Apr 16 12:52:11 PM PDT 24 |
3396318774 ps |
| T838 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.2251975475 |
|
|
Apr 16 12:51:42 PM PDT 24 |
Apr 16 12:51:47 PM PDT 24 |
283010824 ps |
| T839 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.2831939087 |
|
|
Apr 16 12:52:29 PM PDT 24 |
Apr 16 12:59:02 PM PDT 24 |
1761719482 ps |
| T840 |
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.3107161391 |
|
|
Apr 16 12:51:47 PM PDT 24 |
Apr 16 12:55:02 PM PDT 24 |
2063003341 ps |
| T841 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.2511507558 |
|
|
Apr 16 12:51:50 PM PDT 24 |
Apr 16 12:51:57 PM PDT 24 |
330099913 ps |
| T842 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3138205008 |
|
|
Apr 16 12:51:34 PM PDT 24 |
Apr 16 12:57:12 PM PDT 24 |
16309329581 ps |
| T843 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.3443812619 |
|
|
Apr 16 12:51:29 PM PDT 24 |
Apr 16 12:56:39 PM PDT 24 |
65671277573 ps |
| T844 |
/workspace/coverage/default/23.sram_ctrl_smoke.652909535 |
|
|
Apr 16 12:52:32 PM PDT 24 |
Apr 16 12:53:01 PM PDT 24 |
99745897 ps |
| T845 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.1912213571 |
|
|
Apr 16 12:52:08 PM PDT 24 |
Apr 16 12:57:16 PM PDT 24 |
18581297871 ps |
| T846 |
/workspace/coverage/default/3.sram_ctrl_partial_access.2998572051 |
|
|
Apr 16 12:51:27 PM PDT 24 |
Apr 16 12:51:41 PM PDT 24 |
432014384 ps |
| T36 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.2015162835 |
|
|
Apr 16 12:51:33 PM PDT 24 |
Apr 16 12:51:36 PM PDT 24 |
410952217 ps |
| T847 |
/workspace/coverage/default/38.sram_ctrl_stress_all.3453268853 |
|
|
Apr 16 12:54:03 PM PDT 24 |
Apr 16 01:07:50 PM PDT 24 |
134430036142 ps |
| T848 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.173435530 |
|
|
Apr 16 12:51:37 PM PDT 24 |
Apr 16 12:54:47 PM PDT 24 |
8093608245 ps |
| T849 |
/workspace/coverage/default/43.sram_ctrl_smoke.4012244303 |
|
|
Apr 16 12:54:43 PM PDT 24 |
Apr 16 12:56:46 PM PDT 24 |
748735484 ps |
| T77 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3869085691 |
|
|
Apr 16 12:52:38 PM PDT 24 |
Apr 16 12:52:44 PM PDT 24 |
121542054 ps |
| T850 |
/workspace/coverage/default/39.sram_ctrl_smoke.3733011 |
|
|
Apr 16 12:54:09 PM PDT 24 |
Apr 16 12:54:20 PM PDT 24 |
180198871 ps |
| T851 |
/workspace/coverage/default/32.sram_ctrl_stress_all.1615166697 |
|
|
Apr 16 12:53:19 PM PDT 24 |
Apr 16 01:29:56 PM PDT 24 |
72997081058 ps |
| T852 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.2606224753 |
|
|
Apr 16 12:53:23 PM PDT 24 |
Apr 16 12:53:29 PM PDT 24 |
65429699 ps |
| T853 |
/workspace/coverage/default/13.sram_ctrl_regwen.3663468633 |
|
|
Apr 16 12:51:49 PM PDT 24 |
Apr 16 01:06:21 PM PDT 24 |
11254258375 ps |
| T854 |
/workspace/coverage/default/47.sram_ctrl_bijection.493506276 |
|
|
Apr 16 12:55:29 PM PDT 24 |
Apr 16 12:55:49 PM PDT 24 |
1321951456 ps |
| T855 |
/workspace/coverage/default/41.sram_ctrl_partial_access.803829039 |
|
|
Apr 16 12:54:30 PM PDT 24 |
Apr 16 12:54:40 PM PDT 24 |
212517818 ps |
| T856 |
/workspace/coverage/default/37.sram_ctrl_stress_all.4036146040 |
|
|
Apr 16 12:53:58 PM PDT 24 |
Apr 16 01:25:54 PM PDT 24 |
22707858268 ps |
| T857 |
/workspace/coverage/default/40.sram_ctrl_alert_test.1222840170 |
|
|
Apr 16 12:54:30 PM PDT 24 |
Apr 16 12:54:31 PM PDT 24 |
56655614 ps |
| T858 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2315424868 |
|
|
Apr 16 12:51:28 PM PDT 24 |
Apr 16 12:57:11 PM PDT 24 |
18600920803 ps |
| T859 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.2708733325 |
|
|
Apr 16 12:53:44 PM PDT 24 |
Apr 16 01:02:05 PM PDT 24 |
1299722831 ps |
| T860 |
/workspace/coverage/default/4.sram_ctrl_partial_access.4019035800 |
|
|
Apr 16 12:51:33 PM PDT 24 |
Apr 16 12:53:15 PM PDT 24 |
3175547667 ps |
| T861 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.3300603017 |
|
|
Apr 16 12:55:09 PM PDT 24 |
Apr 16 01:08:15 PM PDT 24 |
2501769940 ps |
| T862 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.1069930871 |
|
|
Apr 16 12:51:54 PM PDT 24 |
Apr 16 01:02:37 PM PDT 24 |
4239338967 ps |
| T863 |
/workspace/coverage/default/6.sram_ctrl_stress_all.165030769 |
|
|
Apr 16 12:51:38 PM PDT 24 |
Apr 16 01:08:50 PM PDT 24 |
25005153600 ps |
| T864 |
/workspace/coverage/default/32.sram_ctrl_regwen.1452364077 |
|
|
Apr 16 12:53:19 PM PDT 24 |
Apr 16 01:02:58 PM PDT 24 |
14479283312 ps |
| T865 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.3838063163 |
|
|
Apr 16 12:52:42 PM PDT 24 |
Apr 16 01:12:53 PM PDT 24 |
3984046870 ps |
| T866 |
/workspace/coverage/default/42.sram_ctrl_stress_all_with_rand_reset.1937314863 |
|
|
Apr 16 12:54:40 PM PDT 24 |
Apr 16 12:56:15 PM PDT 24 |
1797950944 ps |
| T867 |
/workspace/coverage/default/24.sram_ctrl_partial_access.954232837 |
|
|
Apr 16 12:52:36 PM PDT 24 |
Apr 16 12:52:55 PM PDT 24 |
3139248025 ps |
| T868 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.4111477626 |
|
|
Apr 16 12:55:35 PM PDT 24 |
Apr 16 12:59:39 PM PDT 24 |
11896918801 ps |
| T869 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.1701326930 |
|
|
Apr 16 12:53:21 PM PDT 24 |
Apr 16 12:53:26 PM PDT 24 |
692365040 ps |
| T870 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.845481184 |
|
|
Apr 16 12:52:04 PM PDT 24 |
Apr 16 12:52:10 PM PDT 24 |
1569744088 ps |
| T871 |
/workspace/coverage/default/16.sram_ctrl_stress_all.3420424964 |
|
|
Apr 16 12:52:07 PM PDT 24 |
Apr 16 01:42:26 PM PDT 24 |
115107578975 ps |
| T872 |
/workspace/coverage/default/11.sram_ctrl_partial_access.3348172572 |
|
|
Apr 16 12:51:55 PM PDT 24 |
Apr 16 12:52:03 PM PDT 24 |
162537664 ps |
| T873 |
/workspace/coverage/default/40.sram_ctrl_smoke.3880263817 |
|
|
Apr 16 12:54:29 PM PDT 24 |
Apr 16 12:54:46 PM PDT 24 |
2938399925 ps |
| T874 |
/workspace/coverage/default/46.sram_ctrl_alert_test.1465913583 |
|
|
Apr 16 12:55:32 PM PDT 24 |
Apr 16 12:55:34 PM PDT 24 |
30085438 ps |
| T875 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1973281644 |
|
|
Apr 16 12:51:34 PM PDT 24 |
Apr 16 01:11:04 PM PDT 24 |
2883968373 ps |
| T876 |
/workspace/coverage/default/18.sram_ctrl_mem_walk.3784429732 |
|
|
Apr 16 12:52:17 PM PDT 24 |
Apr 16 12:52:23 PM PDT 24 |
2027541542 ps |
| T877 |
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.129482170 |
|
|
Apr 16 12:55:56 PM PDT 24 |
Apr 16 01:03:18 PM PDT 24 |
4184541437 ps |
| T878 |
/workspace/coverage/default/28.sram_ctrl_alert_test.3118622586 |
|
|
Apr 16 12:53:02 PM PDT 24 |
Apr 16 12:53:04 PM PDT 24 |
14588830 ps |
| T879 |
/workspace/coverage/default/13.sram_ctrl_alert_test.3522101850 |
|
|
Apr 16 12:51:55 PM PDT 24 |
Apr 16 12:51:58 PM PDT 24 |
18357708 ps |
| T880 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.996838350 |
|
|
Apr 16 12:51:26 PM PDT 24 |
Apr 16 12:51:35 PM PDT 24 |
113189620 ps |
| T881 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.824038068 |
|
|
Apr 16 12:53:14 PM PDT 24 |
Apr 16 12:57:44 PM PDT 24 |
12606995699 ps |
| T882 |
/workspace/coverage/default/33.sram_ctrl_lc_escalation.3110667763 |
|
|
Apr 16 12:53:23 PM PDT 24 |
Apr 16 12:53:29 PM PDT 24 |
2016027825 ps |
| T883 |
/workspace/coverage/default/32.sram_ctrl_smoke.4058164065 |
|
|
Apr 16 12:53:19 PM PDT 24 |
Apr 16 12:55:28 PM PDT 24 |
2544874741 ps |
| T884 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.2058557796 |
|
|
Apr 16 12:51:56 PM PDT 24 |
Apr 16 12:59:07 PM PDT 24 |
69630256450 ps |
| T885 |
/workspace/coverage/default/11.sram_ctrl_alert_test.784816586 |
|
|
Apr 16 12:51:46 PM PDT 24 |
Apr 16 12:51:49 PM PDT 24 |
19963790 ps |
| T886 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.3716449105 |
|
|
Apr 16 12:54:33 PM PDT 24 |
Apr 16 12:58:14 PM PDT 24 |
6151542171 ps |
| T887 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.4091365133 |
|
|
Apr 16 12:52:04 PM PDT 24 |
Apr 16 12:52:07 PM PDT 24 |
509528996 ps |
| T888 |
/workspace/coverage/default/0.sram_ctrl_stress_all.3339529235 |
|
|
Apr 16 12:51:31 PM PDT 24 |
Apr 16 01:46:34 PM PDT 24 |
69791696018 ps |
| T889 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.2058499248 |
|
|
Apr 16 12:52:02 PM PDT 24 |
Apr 16 12:52:08 PM PDT 24 |
80479594 ps |
| T890 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.1283156643 |
|
|
Apr 16 12:51:59 PM PDT 24 |
Apr 16 12:52:34 PM PDT 24 |
382980901 ps |
| T891 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.322130674 |
|
|
Apr 16 12:51:51 PM PDT 24 |
Apr 16 12:52:53 PM PDT 24 |
1406276130 ps |
| T892 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.4003619348 |
|
|
Apr 16 12:52:16 PM PDT 24 |
Apr 16 12:56:03 PM PDT 24 |
13478077811 ps |
| T893 |
/workspace/coverage/default/25.sram_ctrl_alert_test.2754734697 |
|
|
Apr 16 12:52:45 PM PDT 24 |
Apr 16 12:52:46 PM PDT 24 |
14624867 ps |
| T894 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.469375644 |
|
|
Apr 16 12:51:32 PM PDT 24 |
Apr 16 12:51:35 PM PDT 24 |
198336785 ps |
| T895 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.1678623209 |
|
|
Apr 16 12:52:53 PM PDT 24 |
Apr 16 12:56:31 PM PDT 24 |
355655227 ps |
| T896 |
/workspace/coverage/default/9.sram_ctrl_regwen.1685285336 |
|
|
Apr 16 12:51:43 PM PDT 24 |
Apr 16 01:08:28 PM PDT 24 |
41706498158 ps |
| T897 |
/workspace/coverage/default/28.sram_ctrl_partial_access.3713292087 |
|
|
Apr 16 12:52:58 PM PDT 24 |
Apr 16 12:54:43 PM PDT 24 |
1324221288 ps |
| T898 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2970690784 |
|
|
Apr 16 12:54:10 PM PDT 24 |
Apr 16 12:59:29 PM PDT 24 |
9515401061 ps |
| T899 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.2594908664 |
|
|
Apr 16 12:52:21 PM PDT 24 |
Apr 16 12:57:06 PM PDT 24 |
3065172887 ps |
| T900 |
/workspace/coverage/default/44.sram_ctrl_regwen.1894760860 |
|
|
Apr 16 12:55:01 PM PDT 24 |
Apr 16 01:07:25 PM PDT 24 |
85501640783 ps |
| T901 |
/workspace/coverage/default/20.sram_ctrl_stress_all.1470540111 |
|
|
Apr 16 12:52:17 PM PDT 24 |
Apr 16 01:24:57 PM PDT 24 |
8130494998 ps |
| T902 |
/workspace/coverage/default/3.sram_ctrl_stress_all.598849025 |
|
|
Apr 16 12:51:27 PM PDT 24 |
Apr 16 12:52:57 PM PDT 24 |
5867920088 ps |
| T903 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.3047168549 |
|
|
Apr 16 12:52:45 PM PDT 24 |
Apr 16 12:52:49 PM PDT 24 |
99323015 ps |
| T904 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.2595414866 |
|
|
Apr 16 12:52:45 PM PDT 24 |
Apr 16 12:52:48 PM PDT 24 |
892165677 ps |
| T905 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.4228489265 |
|
|
Apr 16 12:54:29 PM PDT 24 |
Apr 16 12:54:45 PM PDT 24 |
157134049 ps |
| T906 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.1105802768 |
|
|
Apr 16 12:54:57 PM PDT 24 |
Apr 16 12:58:13 PM PDT 24 |
3677883071 ps |
| T907 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.4195034805 |
|
|
Apr 16 12:54:51 PM PDT 24 |
Apr 16 12:54:56 PM PDT 24 |
375932899 ps |
| T908 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3970683242 |
|
|
Apr 16 12:54:37 PM PDT 24 |
Apr 16 12:54:53 PM PDT 24 |
82924228 ps |
| T909 |
/workspace/coverage/default/27.sram_ctrl_bijection.3331062988 |
|
|
Apr 16 12:52:49 PM PDT 24 |
Apr 16 12:53:44 PM PDT 24 |
3744372699 ps |
| T910 |
/workspace/coverage/default/3.sram_ctrl_mem_walk.4202617560 |
|
|
Apr 16 12:51:26 PM PDT 24 |
Apr 16 12:51:33 PM PDT 24 |
213363956 ps |
| T911 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.2157541115 |
|
|
Apr 16 12:55:01 PM PDT 24 |
Apr 16 12:55:03 PM PDT 24 |
54045111 ps |
| T912 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.359497492 |
|
|
Apr 16 12:52:07 PM PDT 24 |
Apr 16 12:52:45 PM PDT 24 |
342474169 ps |
| T913 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.619147387 |
|
|
Apr 16 12:53:16 PM PDT 24 |
Apr 16 01:10:11 PM PDT 24 |
16373136462 ps |
| T914 |
/workspace/coverage/default/16.sram_ctrl_access_during_key_req.3280603230 |
|
|
Apr 16 12:51:57 PM PDT 24 |
Apr 16 01:05:16 PM PDT 24 |
3037358601 ps |
| T915 |
/workspace/coverage/default/9.sram_ctrl_stress_all.3930473030 |
|
|
Apr 16 12:51:48 PM PDT 24 |
Apr 16 12:56:28 PM PDT 24 |
13520260547 ps |
| T916 |
/workspace/coverage/default/49.sram_ctrl_stress_all.4181183797 |
|
|
Apr 16 12:55:56 PM PDT 24 |
Apr 16 01:44:06 PM PDT 24 |
8954113671 ps |
| T917 |
/workspace/coverage/default/18.sram_ctrl_smoke.3970848083 |
|
|
Apr 16 12:52:12 PM PDT 24 |
Apr 16 12:53:51 PM PDT 24 |
2437675679 ps |
| T918 |
/workspace/coverage/default/40.sram_ctrl_stress_all.4104615632 |
|
|
Apr 16 12:54:29 PM PDT 24 |
Apr 16 01:07:36 PM PDT 24 |
6321516488 ps |
| T919 |
/workspace/coverage/default/44.sram_ctrl_bijection.1305884871 |
|
|
Apr 16 12:54:55 PM PDT 24 |
Apr 16 12:55:29 PM PDT 24 |
4429903001 ps |
| T920 |
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.1255268436 |
|
|
Apr 16 12:51:46 PM PDT 24 |
Apr 16 12:58:48 PM PDT 24 |
19368714670 ps |
| T921 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.3879442700 |
|
|
Apr 16 12:55:34 PM PDT 24 |
Apr 16 12:55:44 PM PDT 24 |
67319867 ps |
| T922 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.2132605800 |
|
|
Apr 16 12:52:15 PM PDT 24 |
Apr 16 12:53:09 PM PDT 24 |
1523843776 ps |
| T923 |
/workspace/coverage/default/3.sram_ctrl_multiple_keys.1744839674 |
|
|
Apr 16 12:51:25 PM PDT 24 |
Apr 16 12:57:16 PM PDT 24 |
22781860335 ps |
| T924 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.250845887 |
|
|
Apr 16 12:52:12 PM PDT 24 |
Apr 16 12:53:10 PM PDT 24 |
117839418 ps |
| T925 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1613425611 |
|
|
Apr 16 12:55:50 PM PDT 24 |
Apr 16 01:04:51 PM PDT 24 |
2786583974 ps |
| T926 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.3607634860 |
|
|
Apr 16 12:51:52 PM PDT 24 |
Apr 16 12:51:59 PM PDT 24 |
454952691 ps |
| T927 |
/workspace/coverage/default/41.sram_ctrl_access_during_key_req.1995187742 |
|
|
Apr 16 12:54:26 PM PDT 24 |
Apr 16 01:00:08 PM PDT 24 |
3055777642 ps |
| T928 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.4290083699 |
|
|
Apr 16 12:52:25 PM PDT 24 |
Apr 16 12:52:27 PM PDT 24 |
81113825 ps |
| T929 |
/workspace/coverage/default/39.sram_ctrl_regwen.2396990190 |
|
|
Apr 16 12:54:16 PM PDT 24 |
Apr 16 01:04:26 PM PDT 24 |
6297106677 ps |
| T55 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3285854139 |
|
|
Apr 16 12:46:58 PM PDT 24 |
Apr 16 12:47:04 PM PDT 24 |
246703277 ps |
| T56 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.1371895313 |
|
|
Apr 16 12:46:59 PM PDT 24 |
Apr 16 12:47:04 PM PDT 24 |
140375897 ps |
| T57 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.176722917 |
|
|
Apr 16 12:46:57 PM PDT 24 |
Apr 16 12:47:02 PM PDT 24 |
18175355 ps |
| T85 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.670181439 |
|
|
Apr 16 12:46:46 PM PDT 24 |
Apr 16 12:46:48 PM PDT 24 |
58227730 ps |
| T930 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.894664492 |
|
|
Apr 16 12:46:58 PM PDT 24 |
Apr 16 12:47:05 PM PDT 24 |
32336093 ps |
| T113 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1071714148 |
|
|
Apr 16 12:46:55 PM PDT 24 |
Apr 16 12:47:00 PM PDT 24 |
161309442 ps |
| T931 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3916268967 |
|
|
Apr 16 12:46:45 PM PDT 24 |
Apr 16 12:46:48 PM PDT 24 |
52404125 ps |
| T932 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3247671211 |
|
|
Apr 16 12:46:54 PM PDT 24 |
Apr 16 12:47:04 PM PDT 24 |
45185136 ps |
| T933 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.3420655676 |
|
|
Apr 16 12:46:53 PM PDT 24 |
Apr 16 12:46:59 PM PDT 24 |
134809473 ps |
| T58 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3719722320 |
|
|
Apr 16 12:46:43 PM PDT 24 |
Apr 16 12:46:49 PM PDT 24 |
475949455 ps |
| T934 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2699652229 |
|
|
Apr 16 12:47:03 PM PDT 24 |
Apr 16 12:47:08 PM PDT 24 |
154113195 ps |
| T94 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.2547579471 |
|
|
Apr 16 12:46:43 PM PDT 24 |
Apr 16 12:46:46 PM PDT 24 |
118515119 ps |
| T935 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1100500907 |
|
|
Apr 16 12:46:52 PM PDT 24 |
Apr 16 12:46:55 PM PDT 24 |
257776462 ps |
| T86 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.4250390541 |
|
|
Apr 16 12:47:06 PM PDT 24 |
Apr 16 12:47:09 PM PDT 24 |
13111938 ps |
| T59 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4244433622 |
|
|
Apr 16 12:46:59 PM PDT 24 |
Apr 16 12:47:03 PM PDT 24 |
48024877 ps |
| T60 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.382433985 |
|
|
Apr 16 12:47:07 PM PDT 24 |
Apr 16 12:47:11 PM PDT 24 |
36875114 ps |
| T93 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.700403210 |
|
|
Apr 16 12:46:48 PM PDT 24 |
Apr 16 12:46:50 PM PDT 24 |
20973809 ps |
| T95 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4055984371 |
|
|
Apr 16 12:46:52 PM PDT 24 |
Apr 16 12:46:56 PM PDT 24 |
774746042 ps |
| T61 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.4230290709 |
|
|
Apr 16 12:46:48 PM PDT 24 |
Apr 16 12:46:52 PM PDT 24 |
693106328 ps |
| T936 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.548343492 |
|
|
Apr 16 12:46:57 PM PDT 24 |
Apr 16 12:47:02 PM PDT 24 |
129031146 ps |
| T937 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.283849258 |
|
|
Apr 16 12:46:54 PM PDT 24 |
Apr 16 12:46:59 PM PDT 24 |
25160468 ps |
| T62 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1382068611 |
|
|
Apr 16 12:46:45 PM PDT 24 |
Apr 16 12:46:47 PM PDT 24 |
44758115 ps |
| T96 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3218792099 |
|
|
Apr 16 12:46:57 PM PDT 24 |
Apr 16 12:47:02 PM PDT 24 |
87263653 ps |
| T63 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1991138539 |
|
|
Apr 16 12:46:52 PM PDT 24 |
Apr 16 12:46:56 PM PDT 24 |
411729750 ps |
| T938 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3174903863 |
|
|
Apr 16 12:46:50 PM PDT 24 |
Apr 16 12:46:52 PM PDT 24 |
21902105 ps |
| T64 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.279810265 |
|
|
Apr 16 12:46:34 PM PDT 24 |
Apr 16 12:46:40 PM PDT 24 |
1640838476 ps |
| T66 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1155112752 |
|
|
Apr 16 12:46:37 PM PDT 24 |
Apr 16 12:46:41 PM PDT 24 |
851168866 ps |
| T939 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.4059716778 |
|
|
Apr 16 12:46:54 PM PDT 24 |
Apr 16 12:46:57 PM PDT 24 |
21847017 ps |
| T940 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3494929963 |
|
|
Apr 16 12:46:54 PM PDT 24 |
Apr 16 12:46:57 PM PDT 24 |
44484723 ps |
| T941 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2042664389 |
|
|
Apr 16 12:47:05 PM PDT 24 |
Apr 16 12:47:07 PM PDT 24 |
30613716 ps |
| T942 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2226195229 |
|
|
Apr 16 12:46:42 PM PDT 24 |
Apr 16 12:46:44 PM PDT 24 |
43094740 ps |
| T943 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2938242478 |
|
|
Apr 16 12:46:48 PM PDT 24 |
Apr 16 12:46:50 PM PDT 24 |
76248338 ps |
| T944 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3577114335 |
|
|
Apr 16 12:47:09 PM PDT 24 |
Apr 16 12:47:14 PM PDT 24 |
25456662 ps |
| T105 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2789728100 |
|
|
Apr 16 12:46:56 PM PDT 24 |
Apr 16 12:47:01 PM PDT 24 |
347134405 ps |
| T945 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.976727586 |
|
|
Apr 16 12:47:04 PM PDT 24 |
Apr 16 12:47:07 PM PDT 24 |
29752834 ps |
| T103 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.4032201799 |
|
|
Apr 16 12:47:02 PM PDT 24 |
Apr 16 12:47:07 PM PDT 24 |
351187982 ps |
| T106 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.634090494 |
|
|
Apr 16 12:46:54 PM PDT 24 |
Apr 16 12:47:00 PM PDT 24 |
607895488 ps |
| T946 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.4043461058 |
|
|
Apr 16 12:46:54 PM PDT 24 |
Apr 16 12:46:58 PM PDT 24 |
663438557 ps |
| T947 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.572700241 |
|
|
Apr 16 12:46:54 PM PDT 24 |
Apr 16 12:46:58 PM PDT 24 |
48429585 ps |
| T78 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1228235226 |
|
|
Apr 16 12:46:56 PM PDT 24 |
Apr 16 12:47:00 PM PDT 24 |
15920776 ps |
| T107 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2512013858 |
|
|
Apr 16 12:46:56 PM PDT 24 |
Apr 16 12:47:02 PM PDT 24 |
450425290 ps |
| T104 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3291459202 |
|
|
Apr 16 12:46:53 PM PDT 24 |
Apr 16 12:46:59 PM PDT 24 |
454637405 ps |
| T948 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1458813508 |
|
|
Apr 16 12:46:43 PM PDT 24 |
Apr 16 12:46:46 PM PDT 24 |
35573891 ps |
| T949 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3760198825 |
|
|
Apr 16 12:47:02 PM PDT 24 |
Apr 16 12:47:05 PM PDT 24 |
28030449 ps |
| T950 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.523585932 |
|
|
Apr 16 12:46:36 PM PDT 24 |
Apr 16 12:46:42 PM PDT 24 |
2530817385 ps |
| T951 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.421687390 |
|
|
Apr 16 12:46:51 PM PDT 24 |
Apr 16 12:46:57 PM PDT 24 |
292354161 ps |
| T67 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2466956360 |
|
|
Apr 16 12:46:54 PM PDT 24 |
Apr 16 12:46:57 PM PDT 24 |
14118556 ps |
| T952 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.322116941 |
|
|
Apr 16 12:47:05 PM PDT 24 |
Apr 16 12:47:11 PM PDT 24 |
432882056 ps |
| T102 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1184928536 |
|
|
Apr 16 12:46:49 PM PDT 24 |
Apr 16 12:46:53 PM PDT 24 |
774785940 ps |
| T953 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1983979027 |
|
|
Apr 16 12:46:52 PM PDT 24 |
Apr 16 12:46:59 PM PDT 24 |
453838981 ps |
| T954 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1625730864 |
|
|
Apr 16 12:47:05 PM PDT 24 |
Apr 16 12:47:10 PM PDT 24 |
35436897 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.129666555 |
|
|
Apr 16 12:46:46 PM PDT 24 |
Apr 16 12:46:49 PM PDT 24 |
323690277 ps |
| T956 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3175642352 |
|
|
Apr 16 12:46:55 PM PDT 24 |
Apr 16 12:47:01 PM PDT 24 |
844764468 ps |
| T109 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3609931319 |
|
|
Apr 16 12:46:54 PM PDT 24 |
Apr 16 12:46:59 PM PDT 24 |
311448516 ps |
| T957 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.226488183 |
|
|
Apr 16 12:46:47 PM PDT 24 |
Apr 16 12:46:50 PM PDT 24 |
403275241 ps |
| T958 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.2067614489 |
|
|
Apr 16 12:46:32 PM PDT 24 |
Apr 16 12:46:37 PM PDT 24 |
351815625 ps |
| T959 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2536841308 |
|
|
Apr 16 12:46:58 PM PDT 24 |
Apr 16 12:47:03 PM PDT 24 |
137498959 ps |
| T68 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.1801836198 |
|
|
Apr 16 12:46:53 PM PDT 24 |
Apr 16 12:46:59 PM PDT 24 |
743553577 ps |
| T960 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1567442237 |
|
|
Apr 16 12:46:53 PM PDT 24 |
Apr 16 12:46:57 PM PDT 24 |
93314668 ps |
| T69 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.821304010 |
|
|
Apr 16 12:46:45 PM PDT 24 |
Apr 16 12:46:47 PM PDT 24 |
44818926 ps |
| T961 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3942051221 |
|
|
Apr 16 12:46:48 PM PDT 24 |
Apr 16 12:46:50 PM PDT 24 |
25398158 ps |
| T962 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3060289022 |
|
|
Apr 16 12:47:01 PM PDT 24 |
Apr 16 12:47:06 PM PDT 24 |
33292008 ps |
| T963 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1782917740 |
|
|
Apr 16 12:46:54 PM PDT 24 |
Apr 16 12:47:04 PM PDT 24 |
15678327 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.871806329 |
|
|
Apr 16 12:46:39 PM PDT 24 |
Apr 16 12:46:41 PM PDT 24 |
82075023 ps |
| T965 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4149064856 |
|
|
Apr 16 12:46:56 PM PDT 24 |
Apr 16 12:47:02 PM PDT 24 |
26029344 ps |
| T966 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2569281168 |
|
|
Apr 16 12:46:59 PM PDT 24 |
Apr 16 12:47:05 PM PDT 24 |
761278624 ps |
| T967 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1754000398 |
|
|
Apr 16 12:46:49 PM PDT 24 |
Apr 16 12:46:51 PM PDT 24 |
17922985 ps |
| T968 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3532320571 |
|
|
Apr 16 12:46:51 PM PDT 24 |
Apr 16 12:46:53 PM PDT 24 |
46010288 ps |
| T79 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1985340757 |
|
|
Apr 16 12:46:54 PM PDT 24 |
Apr 16 12:47:00 PM PDT 24 |
1725849717 ps |
| T969 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.389248228 |
|
|
Apr 16 12:46:56 PM PDT 24 |
Apr 16 12:47:01 PM PDT 24 |
36525769 ps |
| T80 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.285408396 |
|
|
Apr 16 12:46:54 PM PDT 24 |
Apr 16 12:47:01 PM PDT 24 |
983076837 ps |
| T970 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.2194447913 |
|
|
Apr 16 12:46:55 PM PDT 24 |
Apr 16 12:47:00 PM PDT 24 |
131799202 ps |
| T971 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1947323535 |
|
|
Apr 16 12:47:05 PM PDT 24 |
Apr 16 12:47:08 PM PDT 24 |
16676922 ps |
| T108 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.20941368 |
|
|
Apr 16 12:46:52 PM PDT 24 |
Apr 16 12:46:57 PM PDT 24 |
473891384 ps |
| T972 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4031497872 |
|
|
Apr 16 12:47:05 PM PDT 24 |
Apr 16 12:47:08 PM PDT 24 |
53845918 ps |
| T973 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3454454809 |
|
|
Apr 16 12:46:53 PM PDT 24 |
Apr 16 12:46:58 PM PDT 24 |
488366172 ps |
| T974 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.328620772 |
|
|
Apr 16 12:46:53 PM PDT 24 |
Apr 16 12:46:58 PM PDT 24 |
58041003 ps |
| T975 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.360851385 |
|
|
Apr 16 12:46:43 PM PDT 24 |
Apr 16 12:46:46 PM PDT 24 |
86752363 ps |
| T111 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2216157774 |
|
|
Apr 16 12:46:54 PM PDT 24 |
Apr 16 12:47:01 PM PDT 24 |
1566595591 ps |
| T976 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1205678879 |
|
|
Apr 16 12:46:55 PM PDT 24 |
Apr 16 12:46:59 PM PDT 24 |
18854206 ps |
| T81 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.509376184 |
|
|
Apr 16 12:46:53 PM PDT 24 |
Apr 16 12:46:59 PM PDT 24 |
840733767 ps |
| T977 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1536396592 |
|
|
Apr 16 12:46:47 PM PDT 24 |
Apr 16 12:46:53 PM PDT 24 |
136619090 ps |
| T84 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2702991463 |
|
|
Apr 16 12:46:57 PM PDT 24 |
Apr 16 12:47:04 PM PDT 24 |
393781252 ps |
| T978 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.3318567770 |
|
|
Apr 16 12:47:02 PM PDT 24 |
Apr 16 12:47:07 PM PDT 24 |
178824539 ps |
| T979 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3621700698 |
|
|
Apr 16 12:46:56 PM PDT 24 |
Apr 16 12:47:01 PM PDT 24 |
26813219 ps |
| T980 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1106470143 |
|
|
Apr 16 12:46:49 PM PDT 24 |
Apr 16 12:46:53 PM PDT 24 |
382399641 ps |
| T981 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.482161085 |
|
|
Apr 16 12:46:47 PM PDT 24 |
Apr 16 12:46:51 PM PDT 24 |
284608867 ps |
| T982 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3583066248 |
|
|
Apr 16 12:46:44 PM PDT 24 |
Apr 16 12:46:46 PM PDT 24 |
17234366 ps |
| T983 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4029999924 |
|
|
Apr 16 12:47:03 PM PDT 24 |
Apr 16 12:47:07 PM PDT 24 |
108913585 ps |
| T112 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2765667532 |
|
|
Apr 16 12:47:05 PM PDT 24 |
Apr 16 12:47:08 PM PDT 24 |
369213960 ps |
| T984 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1047353622 |
|
|
Apr 16 12:46:57 PM PDT 24 |
Apr 16 12:47:01 PM PDT 24 |
17624343 ps |
| T985 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.169608077 |
|
|
Apr 16 12:46:52 PM PDT 24 |
Apr 16 12:46:55 PM PDT 24 |
26411611 ps |
| T986 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.876970347 |
|
|
Apr 16 12:46:56 PM PDT 24 |
Apr 16 12:47:02 PM PDT 24 |
58512261 ps |
| T987 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1082247560 |
|
|
Apr 16 12:46:50 PM PDT 24 |
Apr 16 12:46:54 PM PDT 24 |
357887902 ps |
| T82 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1533880054 |
|
|
Apr 16 12:47:01 PM PDT 24 |
Apr 16 12:47:06 PM PDT 24 |
212332976 ps |
| T988 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3706173046 |
|
|
Apr 16 12:46:55 PM PDT 24 |
Apr 16 12:46:59 PM PDT 24 |
98243838 ps |
| T989 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2477180375 |
|
|
Apr 16 12:46:52 PM PDT 24 |
Apr 16 12:46:58 PM PDT 24 |
830172045 ps |
| T990 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.214383169 |
|
|
Apr 16 12:46:37 PM PDT 24 |
Apr 16 12:46:42 PM PDT 24 |
708524158 ps |
| T991 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1043538714 |
|
|
Apr 16 12:46:57 PM PDT 24 |
Apr 16 12:47:01 PM PDT 24 |
20413052 ps |
| T992 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1120453750 |
|
|
Apr 16 12:46:51 PM PDT 24 |
Apr 16 12:46:54 PM PDT 24 |
31899261 ps |
| T993 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.95116462 |
|
|
Apr 16 12:46:54 PM PDT 24 |
Apr 16 12:46:58 PM PDT 24 |
14124192 ps |
| T994 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.51267462 |
|
|
Apr 16 12:47:04 PM PDT 24 |
Apr 16 12:47:07 PM PDT 24 |
102861020 ps |
| T995 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.188833241 |
|
|
Apr 16 12:46:59 PM PDT 24 |
Apr 16 12:47:04 PM PDT 24 |
44872346 ps |
| T996 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.117536008 |
|
|
Apr 16 12:47:11 PM PDT 24 |
Apr 16 12:47:14 PM PDT 24 |
14294770 ps |
| T997 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2084221826 |
|
|
Apr 16 12:46:53 PM PDT 24 |
Apr 16 12:46:58 PM PDT 24 |
1301725477 ps |
| T998 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2095969772 |
|
|
Apr 16 12:46:56 PM PDT 24 |
Apr 16 12:47:03 PM PDT 24 |
121614315 ps |
| T999 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1416521227 |
|
|
Apr 16 12:47:01 PM PDT 24 |
Apr 16 12:47:07 PM PDT 24 |
758292301 ps |
| T1000 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4136397759 |
|
|
Apr 16 12:46:43 PM PDT 24 |
Apr 16 12:46:45 PM PDT 24 |
20255641 ps |
| T1001 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2189181828 |
|
|
Apr 16 12:47:04 PM PDT 24 |
Apr 16 12:47:07 PM PDT 24 |
14624144 ps |
| T1002 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3442703692 |
|
|
Apr 16 12:46:53 PM PDT 24 |
Apr 16 12:46:57 PM PDT 24 |
754872312 ps |