Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(10)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	139990968	1			T1	2040		T2	3862		T3	198
instr_valid_dis	106226227	1			T1	2040		T2	3862		T3	198
instr_en	22696406	1			T14	57228		T15	32070		T16	44

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	10893789	1			T14	67112		T15	91524		T16	62
sram_ifetch_valid_disable	106569270	1			T1	2040		T2	3862		T3	198
sram_ifetch_enable	22527909	1			T14	42814		T15	24318		T28	105802

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	139990968	1			T1	2040		T2	3862		T3	198
hw_debug_en_valid_off	105909736	1			T1	2040		T2	3862		T3	198
hw_debug_en_on	22822528	1			T14	90406		T15	101752		T16	12762

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	106569270	1			T1	2040		T2	3862		T3	198
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	93576449	1			T1	2040		T2	3862		T3	198
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	8585337	1			T16	44		T28	6258		T138	71852
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	4193266	1			T14	21674		T16	62		T28	99386
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1636764	1			T14	1674		T140	38772		T145	35024
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	1671774	1			T14	20000		T28	99386		T138	56820
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	4246741	1			T14	45438		T15	59454		T28	14046
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1587408	1			T14	45438		T15	59454		T28	14046
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	1548140	1			T145	3024		T137	20000		T57	2228
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	8182812	1			T14	7740		T15	42298		T16	12762
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3518382	1			T15	42298		T140	51658		T145	50418
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	2641600	1			T16	44		T138	35986		T137	73426

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	9731289	1			T14	37228		T28	105802		T138	101318
lc_exec_en	10392975	1			T14	37228		T28	31840		T140	44808
valid_exec_dis	102118456	1			T1	2040		T2	3862		T3	198
invalid_exec_dis	33421698	1			T14	109926		T15	115842		T16	62