Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.09 99.81 97.02 100.00 100.00 98.58 99.70 98.52


Total tests in report: 1024
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
85.51 85.51 97.66 97.66 77.63 77.63 87.05 87.05 100.00 100.00 92.82 92.82 94.76 94.76 48.61 48.61 /workspace/coverage/default/10.sram_ctrl_lc_escalation.2717139498
91.70 6.20 98.64 0.97 83.68 6.04 88.91 1.86 100.00 0.00 95.11 2.30 96.56 1.80 79.04 30.43 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.834654717
94.84 3.13 99.03 0.39 90.10 6.43 98.21 9.30 100.00 0.00 96.84 1.72 96.56 0.00 83.12 4.08 /workspace/coverage/default/13.sram_ctrl_regwen.3146482079
95.80 0.97 99.42 0.39 92.29 2.19 99.14 0.93 100.00 0.00 98.56 1.72 97.16 0.60 84.04 0.93 /workspace/coverage/default/2.sram_ctrl_sec_cm.2133406661
96.53 0.73 99.42 0.00 92.93 0.64 99.14 0.00 100.00 0.00 98.56 0.00 97.16 0.00 88.50 4.45 /workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.565001263
97.25 0.72 99.71 0.29 93.19 0.26 99.14 0.00 100.00 0.00 98.85 0.29 97.46 0.30 92.39 3.90 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3756720196
97.62 0.37 99.71 0.00 93.57 0.39 99.14 0.00 100.00 0.00 98.85 0.00 97.46 0.00 94.62 2.23 /workspace/coverage/default/48.sram_ctrl_stress_all.311608345
97.87 0.25 99.71 0.00 93.83 0.26 99.14 0.00 100.00 0.00 98.85 0.00 98.20 0.75 95.36 0.74 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.3652985947
98.07 0.20 99.71 0.00 93.83 0.00 99.21 0.07 100.00 0.00 98.85 0.00 99.55 1.35 95.36 0.00 /workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2075716151
98.23 0.15 99.81 0.10 94.09 0.26 99.93 0.72 100.00 0.00 98.85 0.00 99.55 0.00 95.36 0.00 /workspace/coverage/default/49.sram_ctrl_ram_cfg.1035377996
98.33 0.11 99.81 0.00 94.09 0.00 99.93 0.00 100.00 0.00 98.85 0.00 99.55 0.00 96.10 0.74 /workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3422626604
98.44 0.11 99.81 0.00 94.09 0.00 99.93 0.00 100.00 0.00 98.85 0.00 99.55 0.00 96.85 0.74 /workspace/coverage/default/22.sram_ctrl_executable.2390472816
98.52 0.08 99.81 0.00 94.09 0.00 99.93 0.00 100.00 0.00 98.85 0.00 99.55 0.00 97.40 0.56 /workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3264925902
98.58 0.07 99.81 0.00 94.47 0.39 100.00 0.07 100.00 0.00 98.85 0.00 99.55 0.00 97.40 0.00 /workspace/coverage/default/0.sram_ctrl_alert_test.1910465036
98.64 0.05 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 97.77 0.37 /workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2913075275
98.69 0.05 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 98.14 0.37 /workspace/coverage/default/15.sram_ctrl_executable.1264253224
98.72 0.03 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 98.33 0.19 /workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1275287682
98.74 0.03 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.55 0.00 98.52 0.19 /workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4107133199
98.76 0.02 99.81 0.00 94.47 0.00 100.00 0.00 100.00 0.00 98.85 0.00 99.70 0.15 98.52 0.00 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.847866259

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1309823904
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1157605002
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1027874012
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4006006894
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.451717746
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2613102744
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1254285509
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3664241111
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1401813949
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1727910295
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.914264160
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2689034798
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1978521921
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3471153360
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2970321557
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3914582808
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.131662194
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4104259024
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3028375352
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1325891759
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.329274187
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3895674981
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3944109940
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1609616651
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3078998821
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2777306890
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.269384627
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4052051937
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2225374141
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.193850038
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2206094803
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3534548329
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2568083145
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1017135575
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3579231961
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4010955865
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3300667592
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2171359176
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3731448959
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2299937583
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.216692667
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3584964283
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.770900020
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.80102319
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2786126126
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3463010874
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1696591906
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3148898418
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.3472537267
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3883493153
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2610004581
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2165363661
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1525803843
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4154310869
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2652498480
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1692935820
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1749449487
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4056131309
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2107469050
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.187728318
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.596994387
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2281962296
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4019037753
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3736907771
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1018948600
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3412716559
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.2517441380
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3360680281
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3296311631
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3569570565
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1651729199
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.233743262
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3512304238
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4262759257
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1925311704
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1042087966
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3008895865
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3474003231
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2195816199
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3947000791
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3576887034
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3280602533
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1572528095
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2332909439
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.600718929
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2114544108
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1024501512
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4147562867
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3631383369
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3293204964
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2288722216
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.407662999
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1443030090
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.210345467
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1566676187
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.4006007913
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3798840861
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1786191416
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1954279155
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2039721758
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3228292946
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.338825293
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2686386858
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1794940731
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.558810247
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1950584566
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2674015823
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1132246973
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2082185385
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2757675
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.98073230
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1472482568
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4276133481
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3242432353
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3156665247
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1854169566
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1939908385
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2769010367
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.853290316
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3398777732
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.29700552
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3222982261
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2150527607
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1308168989
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2359091891
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4234537163
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1125049441
/workspace/coverage/default/0.sram_ctrl_bijection.4059788271
/workspace/coverage/default/0.sram_ctrl_executable.1445364430
/workspace/coverage/default/0.sram_ctrl_lc_escalation.158402830
/workspace/coverage/default/0.sram_ctrl_max_throughput.1982126542
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.1851435824
/workspace/coverage/default/0.sram_ctrl_mem_walk.28173757
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2352465835
/workspace/coverage/default/0.sram_ctrl_partial_access.2847094823
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3325471484
/workspace/coverage/default/0.sram_ctrl_ram_cfg.3382691682
/workspace/coverage/default/0.sram_ctrl_regwen.2119074321
/workspace/coverage/default/0.sram_ctrl_sec_cm.4274287431
/workspace/coverage/default/0.sram_ctrl_smoke.3317138451
/workspace/coverage/default/0.sram_ctrl_stress_all.1164975045
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.2743651558
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3159333576
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1048617350
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3263922504
/workspace/coverage/default/1.sram_ctrl_alert_test.3153063301
/workspace/coverage/default/1.sram_ctrl_bijection.2774929528
/workspace/coverage/default/1.sram_ctrl_executable.3346865497
/workspace/coverage/default/1.sram_ctrl_lc_escalation.1506719171
/workspace/coverage/default/1.sram_ctrl_max_throughput.3925728408
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.1185693814
/workspace/coverage/default/1.sram_ctrl_mem_walk.2534311408
/workspace/coverage/default/1.sram_ctrl_multiple_keys.725114099
/workspace/coverage/default/1.sram_ctrl_partial_access.2591367513
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.2283947439
/workspace/coverage/default/1.sram_ctrl_ram_cfg.4181436335
/workspace/coverage/default/1.sram_ctrl_regwen.171069758
/workspace/coverage/default/1.sram_ctrl_sec_cm.3661775491
/workspace/coverage/default/1.sram_ctrl_smoke.3818476378
/workspace/coverage/default/1.sram_ctrl_stress_all.663138966
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2835003022
/workspace/coverage/default/1.sram_ctrl_stress_pipeline.293323080
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.325994067
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2039716908
/workspace/coverage/default/10.sram_ctrl_alert_test.89151160
/workspace/coverage/default/10.sram_ctrl_bijection.153541940
/workspace/coverage/default/10.sram_ctrl_executable.2029248875
/workspace/coverage/default/10.sram_ctrl_max_throughput.3761526452
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2515666189
/workspace/coverage/default/10.sram_ctrl_mem_walk.3402796099
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2404345877
/workspace/coverage/default/10.sram_ctrl_partial_access.204400507
/workspace/coverage/default/10.sram_ctrl_partial_access_b2b.569497984
/workspace/coverage/default/10.sram_ctrl_ram_cfg.3202311956
/workspace/coverage/default/10.sram_ctrl_regwen.920669498
/workspace/coverage/default/10.sram_ctrl_smoke.920951185
/workspace/coverage/default/10.sram_ctrl_stress_all.1254554871
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.2894632331
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.26284295
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.825253688
/workspace/coverage/default/11.sram_ctrl_alert_test.1746643562
/workspace/coverage/default/11.sram_ctrl_bijection.3181267863
/workspace/coverage/default/11.sram_ctrl_executable.640931484
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3836069626
/workspace/coverage/default/11.sram_ctrl_max_throughput.1485461938
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3751488813
/workspace/coverage/default/11.sram_ctrl_mem_walk.1478106973
/workspace/coverage/default/11.sram_ctrl_multiple_keys.368125496
/workspace/coverage/default/11.sram_ctrl_partial_access.2806200092
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.360406401
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3522264468
/workspace/coverage/default/11.sram_ctrl_regwen.4165933359
/workspace/coverage/default/11.sram_ctrl_smoke.1918021590
/workspace/coverage/default/11.sram_ctrl_stress_pipeline.1457883930
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1299932485
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.360106612
/workspace/coverage/default/12.sram_ctrl_alert_test.863938175
/workspace/coverage/default/12.sram_ctrl_bijection.1352237131
/workspace/coverage/default/12.sram_ctrl_executable.3232953752
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3971384343
/workspace/coverage/default/12.sram_ctrl_max_throughput.245343259
/workspace/coverage/default/12.sram_ctrl_mem_partial_access.643821112
/workspace/coverage/default/12.sram_ctrl_mem_walk.3343364417
/workspace/coverage/default/12.sram_ctrl_multiple_keys.649452949
/workspace/coverage/default/12.sram_ctrl_partial_access.3727038892
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2694251273
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3332556139
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/workspace/coverage/default/43.sram_ctrl_ram_cfg.1784892453
/workspace/coverage/default/43.sram_ctrl_regwen.3455052311
/workspace/coverage/default/43.sram_ctrl_smoke.2052299720
/workspace/coverage/default/43.sram_ctrl_stress_all.2981563123
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2625829076
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2589078180
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.13880212
/workspace/coverage/default/44.sram_ctrl_access_during_key_req.1302250204
/workspace/coverage/default/44.sram_ctrl_alert_test.2778335398
/workspace/coverage/default/44.sram_ctrl_bijection.2182669415
/workspace/coverage/default/44.sram_ctrl_executable.1516103147
/workspace/coverage/default/44.sram_ctrl_lc_escalation.776922472
/workspace/coverage/default/44.sram_ctrl_max_throughput.3605163651
/workspace/coverage/default/44.sram_ctrl_mem_partial_access.3328156682
/workspace/coverage/default/44.sram_ctrl_mem_walk.3807527435
/workspace/coverage/default/44.sram_ctrl_multiple_keys.2251348770
/workspace/coverage/default/44.sram_ctrl_partial_access.2356002740
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.4118769813
/workspace/coverage/default/44.sram_ctrl_ram_cfg.1642211364
/workspace/coverage/default/44.sram_ctrl_regwen.4196250331
/workspace/coverage/default/44.sram_ctrl_smoke.3250191521
/workspace/coverage/default/44.sram_ctrl_stress_all.4072227433
/workspace/coverage/default/44.sram_ctrl_stress_all_with_rand_reset.3194615713
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2179085797
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.3119581292
/workspace/coverage/default/45.sram_ctrl_access_during_key_req.2489158196
/workspace/coverage/default/45.sram_ctrl_alert_test.3964134526
/workspace/coverage/default/45.sram_ctrl_bijection.649694822
/workspace/coverage/default/45.sram_ctrl_executable.3699357175
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3245033438
/workspace/coverage/default/45.sram_ctrl_max_throughput.4048903709
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.2179215981
/workspace/coverage/default/45.sram_ctrl_mem_walk.3144375053
/workspace/coverage/default/45.sram_ctrl_multiple_keys.1780891450
/workspace/coverage/default/45.sram_ctrl_partial_access.1517517057
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2560531403
/workspace/coverage/default/45.sram_ctrl_ram_cfg.2738654037
/workspace/coverage/default/45.sram_ctrl_regwen.1944002075
/workspace/coverage/default/45.sram_ctrl_smoke.2321489571
/workspace/coverage/default/45.sram_ctrl_stress_all_with_rand_reset.2931048990
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3121847968
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4007629690
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.158459619
/workspace/coverage/default/46.sram_ctrl_alert_test.2922847077
/workspace/coverage/default/46.sram_ctrl_bijection.2576448217
/workspace/coverage/default/46.sram_ctrl_executable.848073303
/workspace/coverage/default/46.sram_ctrl_lc_escalation.74036068
/workspace/coverage/default/46.sram_ctrl_max_throughput.2272312788
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.3909294128
/workspace/coverage/default/46.sram_ctrl_mem_walk.312817095
/workspace/coverage/default/46.sram_ctrl_multiple_keys.912206906
/workspace/coverage/default/46.sram_ctrl_partial_access.2552049349
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3651245592
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1833736978
/workspace/coverage/default/46.sram_ctrl_regwen.3330618173
/workspace/coverage/default/46.sram_ctrl_smoke.372348892
/workspace/coverage/default/46.sram_ctrl_stress_all.791518563
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1281828643
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.2527228773
/workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.2859090069
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.560153405
/workspace/coverage/default/47.sram_ctrl_alert_test.1279252922
/workspace/coverage/default/47.sram_ctrl_bijection.2216764060
/workspace/coverage/default/47.sram_ctrl_executable.1032274935
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2088321703
/workspace/coverage/default/47.sram_ctrl_max_throughput.1670396892
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.2206868371
/workspace/coverage/default/47.sram_ctrl_mem_walk.4070187824
/workspace/coverage/default/47.sram_ctrl_multiple_keys.2436671260
/workspace/coverage/default/47.sram_ctrl_partial_access.2281681645
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2866112644
/workspace/coverage/default/47.sram_ctrl_ram_cfg.697579445
/workspace/coverage/default/47.sram_ctrl_regwen.3281787478
/workspace/coverage/default/47.sram_ctrl_smoke.935997452
/workspace/coverage/default/47.sram_ctrl_stress_all.324773736
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.2291781508
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3234370277
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2879489819
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.1463197989
/workspace/coverage/default/48.sram_ctrl_alert_test.889896498
/workspace/coverage/default/48.sram_ctrl_bijection.4016215469
/workspace/coverage/default/48.sram_ctrl_executable.2885633189
/workspace/coverage/default/48.sram_ctrl_lc_escalation.31202426
/workspace/coverage/default/48.sram_ctrl_max_throughput.2604905951
/workspace/coverage/default/48.sram_ctrl_mem_partial_access.3711180121
/workspace/coverage/default/48.sram_ctrl_mem_walk.1271406852
/workspace/coverage/default/48.sram_ctrl_multiple_keys.3037973415
/workspace/coverage/default/48.sram_ctrl_partial_access.1624573278
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1592678687
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3641212418
/workspace/coverage/default/48.sram_ctrl_regwen.1160090352
/workspace/coverage/default/48.sram_ctrl_smoke.1183480690
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.2601662331
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1623923493
/workspace/coverage/default/48.sram_ctrl_throughput_w_partial_write.402326804
/workspace/coverage/default/49.sram_ctrl_access_during_key_req.2212154416
/workspace/coverage/default/49.sram_ctrl_alert_test.3892276724
/workspace/coverage/default/49.sram_ctrl_bijection.2203318316
/workspace/coverage/default/49.sram_ctrl_executable.3863367122
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2201262323
/workspace/coverage/default/49.sram_ctrl_max_throughput.492154212
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.3144377383
/workspace/coverage/default/49.sram_ctrl_mem_walk.1383417341
/workspace/coverage/default/49.sram_ctrl_multiple_keys.1587808233
/workspace/coverage/default/49.sram_ctrl_partial_access.2263223792
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.38557533
/workspace/coverage/default/49.sram_ctrl_regwen.2768251634
/workspace/coverage/default/49.sram_ctrl_smoke.2004572211
/workspace/coverage/default/49.sram_ctrl_stress_all.185481608
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3828364405
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.310400208
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.110585622
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.2114819157
/workspace/coverage/default/5.sram_ctrl_alert_test.1618254606
/workspace/coverage/default/5.sram_ctrl_bijection.2554292626
/workspace/coverage/default/5.sram_ctrl_executable.1381100661
/workspace/coverage/default/5.sram_ctrl_lc_escalation.139704781
/workspace/coverage/default/5.sram_ctrl_max_throughput.3975018766
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.2630605220
/workspace/coverage/default/5.sram_ctrl_mem_walk.3303513767
/workspace/coverage/default/5.sram_ctrl_multiple_keys.4205796406
/workspace/coverage/default/5.sram_ctrl_partial_access.2357757635
/workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1004434450
/workspace/coverage/default/5.sram_ctrl_ram_cfg.266087945
/workspace/coverage/default/5.sram_ctrl_regwen.262855651
/workspace/coverage/default/5.sram_ctrl_smoke.259339061
/workspace/coverage/default/5.sram_ctrl_stress_all.3591093990
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2542302593
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.1841442595
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.3704062287
/workspace/coverage/default/6.sram_ctrl_access_during_key_req.2696989625
/workspace/coverage/default/6.sram_ctrl_alert_test.2064290793
/workspace/coverage/default/6.sram_ctrl_bijection.2046875320
/workspace/coverage/default/6.sram_ctrl_executable.1082638402
/workspace/coverage/default/6.sram_ctrl_lc_escalation.4228518167
/workspace/coverage/default/6.sram_ctrl_max_throughput.3645499122
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3282472589
/workspace/coverage/default/6.sram_ctrl_mem_walk.1322372104
/workspace/coverage/default/6.sram_ctrl_multiple_keys.451986581
/workspace/coverage/default/6.sram_ctrl_partial_access.1599831785
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.3091395890
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2838162074
/workspace/coverage/default/6.sram_ctrl_regwen.1369920044
/workspace/coverage/default/6.sram_ctrl_smoke.639278037
/workspace/coverage/default/6.sram_ctrl_stress_all.2585975628
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1135859022
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.636851226
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1425617217
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2789631424
/workspace/coverage/default/7.sram_ctrl_alert_test.4116437937
/workspace/coverage/default/7.sram_ctrl_bijection.2508303205
/workspace/coverage/default/7.sram_ctrl_executable.3995265195
/workspace/coverage/default/7.sram_ctrl_lc_escalation.3151709546
/workspace/coverage/default/7.sram_ctrl_max_throughput.4290836937
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.3540505706
/workspace/coverage/default/7.sram_ctrl_mem_walk.3789812192
/workspace/coverage/default/7.sram_ctrl_multiple_keys.1362016506
/workspace/coverage/default/7.sram_ctrl_partial_access.3812951083
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.4012447856
/workspace/coverage/default/7.sram_ctrl_ram_cfg.355920311
/workspace/coverage/default/7.sram_ctrl_regwen.3403190496
/workspace/coverage/default/7.sram_ctrl_smoke.2667997168
/workspace/coverage/default/7.sram_ctrl_stress_all.1151514160
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2641233648
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.1457881853
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.2626064666
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.651307576
/workspace/coverage/default/8.sram_ctrl_alert_test.3158485112
/workspace/coverage/default/8.sram_ctrl_bijection.2050579675
/workspace/coverage/default/8.sram_ctrl_executable.376600947
/workspace/coverage/default/8.sram_ctrl_lc_escalation.4098358327
/workspace/coverage/default/8.sram_ctrl_max_throughput.3180937337
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1767598431
/workspace/coverage/default/8.sram_ctrl_mem_walk.3669328000
/workspace/coverage/default/8.sram_ctrl_multiple_keys.619259553
/workspace/coverage/default/8.sram_ctrl_partial_access.1529754169
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.978680733
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2368642631
/workspace/coverage/default/8.sram_ctrl_regwen.2234957851
/workspace/coverage/default/8.sram_ctrl_smoke.1525484558
/workspace/coverage/default/8.sram_ctrl_stress_all.733374129
/workspace/coverage/default/8.sram_ctrl_stress_all_with_rand_reset.3819968550
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2712115034
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2322258463
/workspace/coverage/default/9.sram_ctrl_access_during_key_req.1248342164
/workspace/coverage/default/9.sram_ctrl_alert_test.3187328396
/workspace/coverage/default/9.sram_ctrl_bijection.4111914090
/workspace/coverage/default/9.sram_ctrl_executable.2484437828
/workspace/coverage/default/9.sram_ctrl_lc_escalation.3650681421
/workspace/coverage/default/9.sram_ctrl_max_throughput.167729513
/workspace/coverage/default/9.sram_ctrl_mem_partial_access.3494452468
/workspace/coverage/default/9.sram_ctrl_mem_walk.1911465629
/workspace/coverage/default/9.sram_ctrl_multiple_keys.3367343670
/workspace/coverage/default/9.sram_ctrl_partial_access.1403752632
/workspace/coverage/default/9.sram_ctrl_partial_access_b2b.1732096064
/workspace/coverage/default/9.sram_ctrl_ram_cfg.2429799721
/workspace/coverage/default/9.sram_ctrl_regwen.118215342
/workspace/coverage/default/9.sram_ctrl_smoke.2254407342
/workspace/coverage/default/9.sram_ctrl_stress_all.920124766
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2056762336
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.2380326198
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.2349560223



Total test records in report: 1024
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/15.sram_ctrl_mem_partial_access.2372232180 Apr 18 02:11:10 PM PDT 24 Apr 18 02:11:13 PM PDT 24 150507577 ps
T2 /workspace/coverage/default/0.sram_ctrl_mem_partial_access.1851435824 Apr 18 02:09:00 PM PDT 24 Apr 18 02:09:06 PM PDT 24 330975926 ps
T3 /workspace/coverage/default/14.sram_ctrl_partial_access.362971139 Apr 18 02:10:58 PM PDT 24 Apr 18 02:11:02 PM PDT 24 92999515 ps
T4 /workspace/coverage/default/21.sram_ctrl_partial_access_b2b.3756720196 Apr 18 02:12:09 PM PDT 24 Apr 18 02:21:28 PM PDT 24 99348144693 ps
T8 /workspace/coverage/default/21.sram_ctrl_smoke.295573876 Apr 18 02:12:04 PM PDT 24 Apr 18 02:14:19 PM PDT 24 651113320 ps
T9 /workspace/coverage/default/43.sram_ctrl_multiple_keys.2966773376 Apr 18 02:16:24 PM PDT 24 Apr 18 02:28:17 PM PDT 24 8158749846 ps
T5 /workspace/coverage/default/10.sram_ctrl_lc_escalation.2717139498 Apr 18 02:10:22 PM PDT 24 Apr 18 02:10:32 PM PDT 24 2086232416 ps
T10 /workspace/coverage/default/16.sram_ctrl_mem_partial_access.265011996 Apr 18 02:11:41 PM PDT 24 Apr 18 02:11:45 PM PDT 24 87539640 ps
T11 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.3751488813 Apr 18 02:10:32 PM PDT 24 Apr 18 02:10:37 PM PDT 24 178854609 ps
T12 /workspace/coverage/default/11.sram_ctrl_bijection.3181267863 Apr 18 02:10:30 PM PDT 24 Apr 18 02:11:16 PM PDT 24 2052531854 ps
T27 /workspace/coverage/default/44.sram_ctrl_bijection.2182669415 Apr 18 02:16:32 PM PDT 24 Apr 18 02:16:52 PM PDT 24 3405921099 ps
T13 /workspace/coverage/default/7.sram_ctrl_stress_pipeline.1457881853 Apr 18 02:09:51 PM PDT 24 Apr 18 02:12:57 PM PDT 24 8433615989 ps
T31 /workspace/coverage/default/42.sram_ctrl_multiple_keys.863595556 Apr 18 02:16:14 PM PDT 24 Apr 18 02:30:17 PM PDT 24 4035100056 ps
T6 /workspace/coverage/default/1.sram_ctrl_lc_escalation.1506719171 Apr 18 02:09:09 PM PDT 24 Apr 18 02:09:15 PM PDT 24 2267576020 ps
T17 /workspace/coverage/default/14.sram_ctrl_access_during_key_req.3652985947 Apr 18 02:10:57 PM PDT 24 Apr 18 02:15:11 PM PDT 24 1168400857 ps
T64 /workspace/coverage/default/38.sram_ctrl_throughput_w_partial_write.1624849543 Apr 18 02:15:31 PM PDT 24 Apr 18 02:15:56 PM PDT 24 222514199 ps
T75 /workspace/coverage/default/6.sram_ctrl_multiple_keys.451986581 Apr 18 02:09:47 PM PDT 24 Apr 18 02:23:53 PM PDT 24 10390936289 ps
T76 /workspace/coverage/default/28.sram_ctrl_multiple_keys.2329283516 Apr 18 02:13:34 PM PDT 24 Apr 18 02:26:34 PM PDT 24 1694518426 ps
T18 /workspace/coverage/default/29.sram_ctrl_access_during_key_req.633192068 Apr 18 02:13:53 PM PDT 24 Apr 18 02:26:40 PM PDT 24 1183872710 ps
T14 /workspace/coverage/default/11.sram_ctrl_executable.640931484 Apr 18 02:10:32 PM PDT 24 Apr 18 02:17:09 PM PDT 24 11885963313 ps
T99 /workspace/coverage/default/2.sram_ctrl_partial_access_b2b.636353470 Apr 18 02:09:12 PM PDT 24 Apr 18 02:13:19 PM PDT 24 3571189709 ps
T161 /workspace/coverage/default/26.sram_ctrl_mem_walk.937204534 Apr 18 02:13:18 PM PDT 24 Apr 18 02:13:25 PM PDT 24 1318364455 ps
T100 /workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1147084631 Apr 18 02:09:33 PM PDT 24 Apr 18 02:15:17 PM PDT 24 61222416386 ps
T82 /workspace/coverage/default/30.sram_ctrl_mem_partial_access.2485749896 Apr 18 02:14:03 PM PDT 24 Apr 18 02:14:08 PM PDT 24 181574263 ps
T157 /workspace/coverage/default/22.sram_ctrl_max_throughput.794097053 Apr 18 02:12:19 PM PDT 24 Apr 18 02:12:57 PM PDT 24 355021773 ps
T83 /workspace/coverage/default/34.sram_ctrl_mem_partial_access.3812029270 Apr 18 02:14:41 PM PDT 24 Apr 18 02:14:46 PM PDT 24 264880672 ps
T15 /workspace/coverage/default/13.sram_ctrl_regwen.3146482079 Apr 18 02:10:51 PM PDT 24 Apr 18 02:21:11 PM PDT 24 24995517718 ps
T7 /workspace/coverage/default/3.sram_ctrl_lc_escalation.3396650004 Apr 18 02:09:28 PM PDT 24 Apr 18 02:09:35 PM PDT 24 1416981210 ps
T62 /workspace/coverage/default/29.sram_ctrl_lc_escalation.4094189814 Apr 18 02:13:46 PM PDT 24 Apr 18 02:13:52 PM PDT 24 2431864862 ps
T63 /workspace/coverage/default/46.sram_ctrl_lc_escalation.74036068 Apr 18 02:17:09 PM PDT 24 Apr 18 02:17:19 PM PDT 24 889358632 ps
T23 /workspace/coverage/default/23.sram_ctrl_alert_test.3546617133 Apr 18 02:12:34 PM PDT 24 Apr 18 02:12:35 PM PDT 24 39637841 ps
T35 /workspace/coverage/default/19.sram_ctrl_ram_cfg.3862279402 Apr 18 02:11:49 PM PDT 24 Apr 18 02:11:50 PM PDT 24 27111489 ps
T29 /workspace/coverage/default/41.sram_ctrl_lc_escalation.1642696202 Apr 18 02:15:56 PM PDT 24 Apr 18 02:16:03 PM PDT 24 979866886 ps
T160 /workspace/coverage/default/48.sram_ctrl_partial_access.1624573278 Apr 18 02:17:36 PM PDT 24 Apr 18 02:19:49 PM PDT 24 652624892 ps
T16 /workspace/coverage/default/15.sram_ctrl_regwen.2039834404 Apr 18 02:11:10 PM PDT 24 Apr 18 02:11:34 PM PDT 24 2018627715 ps
T159 /workspace/coverage/default/27.sram_ctrl_max_throughput.3103829280 Apr 18 02:13:24 PM PDT 24 Apr 18 02:14:00 PM PDT 24 324956092 ps
T28 /workspace/coverage/default/48.sram_ctrl_stress_all.311608345 Apr 18 02:17:42 PM PDT 24 Apr 18 02:48:05 PM PDT 24 29992372027 ps
T30 /workspace/coverage/default/0.sram_ctrl_lc_escalation.158402830 Apr 18 02:09:00 PM PDT 24 Apr 18 02:09:08 PM PDT 24 564110601 ps
T101 /workspace/coverage/default/32.sram_ctrl_stress_pipeline.1141931839 Apr 18 02:14:16 PM PDT 24 Apr 18 02:18:11 PM PDT 24 9004934070 ps
T150 /workspace/coverage/default/34.sram_ctrl_throughput_w_partial_write.3362967885 Apr 18 02:14:41 PM PDT 24 Apr 18 02:14:42 PM PDT 24 273009159 ps
T19 /workspace/coverage/default/0.sram_ctrl_access_during_key_req.847866259 Apr 18 02:08:59 PM PDT 24 Apr 18 02:27:57 PM PDT 24 19564478410 ps
T140 /workspace/coverage/default/38.sram_ctrl_stress_all.2018370702 Apr 18 02:15:40 PM PDT 24 Apr 18 02:46:19 PM PDT 24 30093619395 ps
T102 /workspace/coverage/default/38.sram_ctrl_stress_pipeline.618368373 Apr 18 02:15:24 PM PDT 24 Apr 18 02:18:48 PM PDT 24 4106113326 ps
T162 /workspace/coverage/default/1.sram_ctrl_mem_walk.2534311408 Apr 18 02:09:05 PM PDT 24 Apr 18 02:09:13 PM PDT 24 516064035 ps
T163 /workspace/coverage/default/24.sram_ctrl_smoke.795086476 Apr 18 02:12:41 PM PDT 24 Apr 18 02:14:06 PM PDT 24 1782678296 ps
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T84 /workspace/coverage/default/23.sram_ctrl_access_during_key_req.3614131649 Apr 18 02:12:30 PM PDT 24 Apr 18 02:27:24 PM PDT 24 2593243687 ps
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T36 /workspace/coverage/default/43.sram_ctrl_ram_cfg.1784892453 Apr 18 02:16:28 PM PDT 24 Apr 18 02:16:29 PM PDT 24 77196789 ps
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T42 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1354426374 Apr 18 02:14:09 PM PDT 24 Apr 18 02:14:13 PM PDT 24 310781385 ps
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T32 /workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2951182130 Apr 18 02:13:06 PM PDT 24 Apr 18 02:16:53 PM PDT 24 1631234224 ps
T55 /workspace/coverage/default/5.sram_ctrl_partial_access_b2b.1004434450 Apr 18 02:09:40 PM PDT 24 Apr 18 02:14:54 PM PDT 24 4483285859 ps
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T56 /workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.2509944406 Apr 18 02:11:44 PM PDT 24 Apr 18 02:12:14 PM PDT 24 362247886 ps
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T33 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1780555845 Apr 18 02:14:04 PM PDT 24 Apr 18 02:16:25 PM PDT 24 7627982851 ps
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T151 /workspace/coverage/default/9.sram_ctrl_stress_all.920124766 Apr 18 02:10:22 PM PDT 24 Apr 18 02:26:57 PM PDT 24 96732566039 ps
T153 /workspace/coverage/default/35.sram_ctrl_access_during_key_req.505447637 Apr 18 02:14:46 PM PDT 24 Apr 18 02:30:15 PM PDT 24 2122578680 ps
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T169 /workspace/coverage/default/10.sram_ctrl_mem_partial_access.2515666189 Apr 18 02:10:23 PM PDT 24 Apr 18 02:10:29 PM PDT 24 123761651 ps
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T170 /workspace/coverage/default/5.sram_ctrl_stress_pipeline.1841442595 Apr 18 02:09:39 PM PDT 24 Apr 18 02:12:29 PM PDT 24 1848709275 ps
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T171 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.3144377383 Apr 18 02:18:01 PM PDT 24 Apr 18 02:18:04 PM PDT 24 334888645 ps
T172 /workspace/coverage/default/3.sram_ctrl_stress_pipeline.1546247204 Apr 18 02:09:25 PM PDT 24 Apr 18 02:12:31 PM PDT 24 2046812758 ps
T173 /workspace/coverage/default/12.sram_ctrl_access_during_key_req.360106612 Apr 18 02:10:37 PM PDT 24 Apr 18 02:23:05 PM PDT 24 2496004658 ps
T174 /workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.2322258463 Apr 18 02:10:04 PM PDT 24 Apr 18 02:11:01 PM PDT 24 1688573073 ps
T144 /workspace/coverage/default/20.sram_ctrl_stress_all.3828431243 Apr 18 02:12:03 PM PDT 24 Apr 18 03:24:44 PM PDT 24 245201179013 ps
T175 /workspace/coverage/default/37.sram_ctrl_alert_test.1834027817 Apr 18 02:15:22 PM PDT 24 Apr 18 02:15:23 PM PDT 24 77225831 ps
T176 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.978680733 Apr 18 02:09:58 PM PDT 24 Apr 18 02:14:37 PM PDT 24 10194739082 ps
T177 /workspace/coverage/default/22.sram_ctrl_smoke.174889413 Apr 18 02:12:18 PM PDT 24 Apr 18 02:13:16 PM PDT 24 418164027 ps
T34 /workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.834654717 Apr 18 02:09:40 PM PDT 24 Apr 18 02:10:52 PM PDT 24 828721625 ps
T115 /workspace/coverage/default/47.sram_ctrl_stress_all.324773736 Apr 18 02:17:25 PM PDT 24 Apr 18 02:36:42 PM PDT 24 31154190159 ps
T116 /workspace/coverage/default/37.sram_ctrl_stress_pipeline.2917720026 Apr 18 02:15:13 PM PDT 24 Apr 18 02:19:38 PM PDT 24 4497763597 ps
T117 /workspace/coverage/default/4.sram_ctrl_max_throughput.2521520823 Apr 18 02:09:32 PM PDT 24 Apr 18 02:12:13 PM PDT 24 268228395 ps
T118 /workspace/coverage/default/14.sram_ctrl_bijection.4234668236 Apr 18 02:10:53 PM PDT 24 Apr 18 02:11:19 PM PDT 24 2107499724 ps
T119 /workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.1425617217 Apr 18 02:09:46 PM PDT 24 Apr 18 02:09:58 PM PDT 24 87028959 ps
T21 /workspace/coverage/default/2.sram_ctrl_sec_cm.2133406661 Apr 18 02:09:19 PM PDT 24 Apr 18 02:09:23 PM PDT 24 844070945 ps
T120 /workspace/coverage/default/47.sram_ctrl_smoke.935997452 Apr 18 02:17:15 PM PDT 24 Apr 18 02:17:31 PM PDT 24 9109888529 ps
T121 /workspace/coverage/default/42.sram_ctrl_lc_escalation.1417333622 Apr 18 02:16:18 PM PDT 24 Apr 18 02:16:20 PM PDT 24 535900808 ps
T122 /workspace/coverage/default/1.sram_ctrl_partial_access.2591367513 Apr 18 02:09:09 PM PDT 24 Apr 18 02:09:10 PM PDT 24 37262782 ps
T178 /workspace/coverage/default/0.sram_ctrl_regwen.2119074321 Apr 18 02:09:00 PM PDT 24 Apr 18 02:09:52 PM PDT 24 826750550 ps
T179 /workspace/coverage/default/1.sram_ctrl_mem_partial_access.1185693814 Apr 18 02:09:05 PM PDT 24 Apr 18 02:09:08 PM PDT 24 163844520 ps
T180 /workspace/coverage/default/39.sram_ctrl_regwen.2452628489 Apr 18 02:15:40 PM PDT 24 Apr 18 02:29:37 PM PDT 24 18211626477 ps
T181 /workspace/coverage/default/14.sram_ctrl_stress_pipeline.2666465878 Apr 18 02:11:00 PM PDT 24 Apr 18 02:13:33 PM PDT 24 1610627089 ps
T158 /workspace/coverage/default/25.sram_ctrl_lc_escalation.1843036519 Apr 18 02:12:58 PM PDT 24 Apr 18 02:13:02 PM PDT 24 361611235 ps
T48 /workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.1339059578 Apr 18 02:14:16 PM PDT 24 Apr 18 02:15:01 PM PDT 24 616794234 ps
T182 /workspace/coverage/default/27.sram_ctrl_ram_cfg.1546094372 Apr 18 02:13:31 PM PDT 24 Apr 18 02:13:32 PM PDT 24 27959107 ps
T183 /workspace/coverage/default/38.sram_ctrl_alert_test.1429967067 Apr 18 02:15:34 PM PDT 24 Apr 18 02:15:35 PM PDT 24 14490086 ps
T184 /workspace/coverage/default/23.sram_ctrl_max_throughput.3260788442 Apr 18 02:12:30 PM PDT 24 Apr 18 02:13:27 PM PDT 24 345584243 ps
T185 /workspace/coverage/default/45.sram_ctrl_lc_escalation.3245033438 Apr 18 02:16:54 PM PDT 24 Apr 18 02:17:04 PM PDT 24 3409073652 ps
T186 /workspace/coverage/default/40.sram_ctrl_ram_cfg.2361366318 Apr 18 02:15:52 PM PDT 24 Apr 18 02:15:53 PM PDT 24 27363807 ps
T187 /workspace/coverage/default/4.sram_ctrl_multiple_keys.563036682 Apr 18 02:09:33 PM PDT 24 Apr 18 02:19:52 PM PDT 24 38310796020 ps
T49 /workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.3512265135 Apr 18 02:13:32 PM PDT 24 Apr 18 02:14:35 PM PDT 24 1758339948 ps
T188 /workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.3358191080 Apr 18 02:10:48 PM PDT 24 Apr 18 02:12:48 PM PDT 24 272328466 ps
T189 /workspace/coverage/default/24.sram_ctrl_lc_escalation.3020842498 Apr 18 02:12:47 PM PDT 24 Apr 18 02:12:58 PM PDT 24 3443938294 ps
T50 /workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.831057441 Apr 18 02:12:09 PM PDT 24 Apr 18 02:26:01 PM PDT 24 1317733479 ps
T190 /workspace/coverage/default/35.sram_ctrl_lc_escalation.1099656117 Apr 18 02:14:49 PM PDT 24 Apr 18 02:14:56 PM PDT 24 1706103570 ps
T147 /workspace/coverage/default/39.sram_ctrl_multiple_keys.3635043868 Apr 18 02:15:37 PM PDT 24 Apr 18 02:31:15 PM PDT 24 60002330878 ps
T51 /workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1268815786 Apr 18 02:11:55 PM PDT 24 Apr 18 02:12:18 PM PDT 24 1246857435 ps
T191 /workspace/coverage/default/9.sram_ctrl_mem_partial_access.3494452468 Apr 18 02:10:23 PM PDT 24 Apr 18 02:10:27 PM PDT 24 191756825 ps
T192 /workspace/coverage/default/19.sram_ctrl_lc_escalation.3163489185 Apr 18 02:11:45 PM PDT 24 Apr 18 02:11:52 PM PDT 24 2898764333 ps
T193 /workspace/coverage/default/46.sram_ctrl_smoke.372348892 Apr 18 02:17:04 PM PDT 24 Apr 18 02:19:31 PM PDT 24 257643941 ps
T194 /workspace/coverage/default/16.sram_ctrl_max_throughput.3252332322 Apr 18 02:11:19 PM PDT 24 Apr 18 02:12:52 PM PDT 24 204543353 ps
T195 /workspace/coverage/default/20.sram_ctrl_executable.1919331038 Apr 18 02:11:56 PM PDT 24 Apr 18 02:14:22 PM PDT 24 912941358 ps
T196 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2701496027 Apr 18 02:09:18 PM PDT 24 Apr 18 02:09:21 PM PDT 24 176821740 ps
T197 /workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1299932485 Apr 18 02:10:30 PM PDT 24 Apr 18 02:11:44 PM PDT 24 424689200 ps
T198 /workspace/coverage/default/17.sram_ctrl_mem_walk.4279532711 Apr 18 02:11:41 PM PDT 24 Apr 18 02:11:49 PM PDT 24 136143783 ps
T199 /workspace/coverage/default/13.sram_ctrl_max_throughput.3734749933 Apr 18 02:10:56 PM PDT 24 Apr 18 02:11:10 PM PDT 24 249148709 ps
T200 /workspace/coverage/default/21.sram_ctrl_access_during_key_req.2058021822 Apr 18 02:12:15 PM PDT 24 Apr 18 02:21:31 PM PDT 24 6096094173 ps
T201 /workspace/coverage/default/30.sram_ctrl_partial_access.1974732549 Apr 18 02:13:54 PM PDT 24 Apr 18 02:15:38 PM PDT 24 1612345489 ps
T202 /workspace/coverage/default/46.sram_ctrl_multiple_keys.912206906 Apr 18 02:17:03 PM PDT 24 Apr 18 02:24:07 PM PDT 24 1504184822 ps
T203 /workspace/coverage/default/30.sram_ctrl_mem_walk.2103845079 Apr 18 02:14:04 PM PDT 24 Apr 18 02:14:13 PM PDT 24 1433453098 ps
T204 /workspace/coverage/default/49.sram_ctrl_mem_walk.1383417341 Apr 18 02:17:56 PM PDT 24 Apr 18 02:18:02 PM PDT 24 586455083 ps
T141 /workspace/coverage/default/27.sram_ctrl_executable.4222593987 Apr 18 02:13:24 PM PDT 24 Apr 18 02:27:34 PM PDT 24 7987792635 ps
T205 /workspace/coverage/default/3.sram_ctrl_mem_walk.2527412914 Apr 18 02:09:28 PM PDT 24 Apr 18 02:09:33 PM PDT 24 78156506 ps
T206 /workspace/coverage/default/40.sram_ctrl_mem_partial_access.2706316451 Apr 18 02:15:51 PM PDT 24 Apr 18 02:15:54 PM PDT 24 44364916 ps
T207 /workspace/coverage/default/49.sram_ctrl_max_throughput.492154212 Apr 18 02:17:52 PM PDT 24 Apr 18 02:20:10 PM PDT 24 142410945 ps
T208 /workspace/coverage/default/48.sram_ctrl_executable.2885633189 Apr 18 02:17:36 PM PDT 24 Apr 18 02:28:50 PM PDT 24 44796475997 ps
T209 /workspace/coverage/default/33.sram_ctrl_max_throughput.1622193219 Apr 18 02:14:32 PM PDT 24 Apr 18 02:16:06 PM PDT 24 131613805 ps
T210 /workspace/coverage/default/40.sram_ctrl_access_during_key_req.1151621435 Apr 18 02:15:52 PM PDT 24 Apr 18 02:47:57 PM PDT 24 7809188947 ps
T211 /workspace/coverage/default/31.sram_ctrl_partial_access.2472035624 Apr 18 02:14:10 PM PDT 24 Apr 18 02:14:30 PM PDT 24 3547433675 ps
T212 /workspace/coverage/default/18.sram_ctrl_mem_walk.1457623227 Apr 18 02:11:40 PM PDT 24 Apr 18 02:11:51 PM PDT 24 5504500982 ps
T213 /workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.1048617350 Apr 18 02:09:05 PM PDT 24 Apr 18 02:09:35 PM PDT 24 143265929 ps
T214 /workspace/coverage/default/22.sram_ctrl_mem_walk.2337310743 Apr 18 02:12:23 PM PDT 24 Apr 18 02:12:29 PM PDT 24 889449637 ps
T215 /workspace/coverage/default/32.sram_ctrl_lc_escalation.956869765 Apr 18 02:14:19 PM PDT 24 Apr 18 02:14:24 PM PDT 24 708686934 ps
T216 /workspace/coverage/default/26.sram_ctrl_bijection.3079037935 Apr 18 02:13:04 PM PDT 24 Apr 18 02:14:04 PM PDT 24 14443896555 ps
T217 /workspace/coverage/default/25.sram_ctrl_mem_walk.3761159173 Apr 18 02:13:03 PM PDT 24 Apr 18 02:13:08 PM PDT 24 75022482 ps
T52 /workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.1135859022 Apr 18 02:09:52 PM PDT 24 Apr 18 02:10:04 PM PDT 24 968031303 ps
T218 /workspace/coverage/default/17.sram_ctrl_alert_test.2606355687 Apr 18 02:11:40 PM PDT 24 Apr 18 02:11:42 PM PDT 24 23375002 ps
T219 /workspace/coverage/default/28.sram_ctrl_smoke.1927837049 Apr 18 02:13:32 PM PDT 24 Apr 18 02:14:19 PM PDT 24 1644859337 ps
T149 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.4080213546 Apr 18 02:14:44 PM PDT 24 Apr 18 02:19:51 PM PDT 24 52681906883 ps
T220 /workspace/coverage/default/0.sram_ctrl_alert_test.1910465036 Apr 18 02:09:09 PM PDT 24 Apr 18 02:09:10 PM PDT 24 11200979 ps
T221 /workspace/coverage/default/43.sram_ctrl_lc_escalation.1229036101 Apr 18 02:16:28 PM PDT 24 Apr 18 02:16:33 PM PDT 24 352765392 ps
T222 /workspace/coverage/default/21.sram_ctrl_max_throughput.3775250336 Apr 18 02:12:09 PM PDT 24 Apr 18 02:12:25 PM PDT 24 93637004 ps
T223 /workspace/coverage/default/32.sram_ctrl_partial_access_b2b.1871132838 Apr 18 02:14:20 PM PDT 24 Apr 18 02:18:32 PM PDT 24 14297950176 ps
T224 /workspace/coverage/default/14.sram_ctrl_alert_test.1144267816 Apr 18 02:10:58 PM PDT 24 Apr 18 02:11:01 PM PDT 24 63656207 ps
T225 /workspace/coverage/default/15.sram_ctrl_bijection.2440799068 Apr 18 02:11:03 PM PDT 24 Apr 18 02:11:19 PM PDT 24 1187099791 ps
T226 /workspace/coverage/default/44.sram_ctrl_partial_access_b2b.4118769813 Apr 18 02:16:34 PM PDT 24 Apr 18 02:20:46 PM PDT 24 3507449042 ps
T142 /workspace/coverage/default/31.sram_ctrl_executable.3155546789 Apr 18 02:14:09 PM PDT 24 Apr 18 02:19:14 PM PDT 24 10272430981 ps
T227 /workspace/coverage/default/30.sram_ctrl_ram_cfg.4012756981 Apr 18 02:14:04 PM PDT 24 Apr 18 02:14:05 PM PDT 24 31925872 ps
T228 /workspace/coverage/default/7.sram_ctrl_smoke.2667997168 Apr 18 02:09:50 PM PDT 24 Apr 18 02:10:21 PM PDT 24 91498135 ps
T229 /workspace/coverage/default/15.sram_ctrl_partial_access.1619102910 Apr 18 02:11:06 PM PDT 24 Apr 18 02:11:31 PM PDT 24 360457868 ps
T230 /workspace/coverage/default/44.sram_ctrl_alert_test.2778335398 Apr 18 02:16:49 PM PDT 24 Apr 18 02:16:50 PM PDT 24 13609699 ps
T231 /workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2560531403 Apr 18 02:16:53 PM PDT 24 Apr 18 02:21:26 PM PDT 24 43717351002 ps
T232 /workspace/coverage/default/26.sram_ctrl_max_throughput.2370565648 Apr 18 02:13:13 PM PDT 24 Apr 18 02:13:20 PM PDT 24 941264445 ps
T233 /workspace/coverage/default/31.sram_ctrl_lc_escalation.4027370506 Apr 18 02:14:09 PM PDT 24 Apr 18 02:14:12 PM PDT 24 294447148 ps
T234 /workspace/coverage/default/46.sram_ctrl_regwen.3330618173 Apr 18 02:17:10 PM PDT 24 Apr 18 02:26:13 PM PDT 24 2358081604 ps
T235 /workspace/coverage/default/9.sram_ctrl_lc_escalation.3650681421 Apr 18 02:10:11 PM PDT 24 Apr 18 02:10:13 PM PDT 24 153114348 ps
T236 /workspace/coverage/default/30.sram_ctrl_partial_access_b2b.4052057694 Apr 18 02:13:58 PM PDT 24 Apr 18 02:18:54 PM PDT 24 4302144241 ps
T237 /workspace/coverage/default/26.sram_ctrl_stress_pipeline.3054666485 Apr 18 02:13:04 PM PDT 24 Apr 18 02:15:45 PM PDT 24 3585079567 ps
T238 /workspace/coverage/default/14.sram_ctrl_max_throughput.3565345194 Apr 18 02:11:03 PM PDT 24 Apr 18 02:11:37 PM PDT 24 104385830 ps
T239 /workspace/coverage/default/3.sram_ctrl_partial_access_b2b.643349509 Apr 18 02:09:25 PM PDT 24 Apr 18 02:11:21 PM PDT 24 3448993161 ps
T240 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.797369979 Apr 18 02:13:43 PM PDT 24 Apr 18 02:13:46 PM PDT 24 342550521 ps
T241 /workspace/coverage/default/33.sram_ctrl_stress_all.4264847970 Apr 18 02:14:32 PM PDT 24 Apr 18 02:21:44 PM PDT 24 48777103005 ps
T22 /workspace/coverage/default/3.sram_ctrl_sec_cm.1858290057 Apr 18 02:09:33 PM PDT 24 Apr 18 02:09:37 PM PDT 24 905738791 ps
T242 /workspace/coverage/default/41.sram_ctrl_partial_access.2320966097 Apr 18 02:15:56 PM PDT 24 Apr 18 02:16:04 PM PDT 24 430828867 ps
T243 /workspace/coverage/default/30.sram_ctrl_max_throughput.3833163903 Apr 18 02:13:57 PM PDT 24 Apr 18 02:14:20 PM PDT 24 131064521 ps
T244 /workspace/coverage/default/40.sram_ctrl_partial_access_b2b.270162425 Apr 18 02:15:48 PM PDT 24 Apr 18 02:22:13 PM PDT 24 30701718820 ps
T245 /workspace/coverage/default/22.sram_ctrl_regwen.748787099 Apr 18 02:12:25 PM PDT 24 Apr 18 02:22:44 PM PDT 24 46660699190 ps
T53 /workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1567002403 Apr 18 02:14:22 PM PDT 24 Apr 18 02:14:53 PM PDT 24 630452215 ps
T246 /workspace/coverage/default/20.sram_ctrl_partial_access_b2b.3087066671 Apr 18 02:11:57 PM PDT 24 Apr 18 02:17:52 PM PDT 24 13613505974 ps
T247 /workspace/coverage/default/31.sram_ctrl_max_throughput.3822492982 Apr 18 02:14:09 PM PDT 24 Apr 18 02:14:31 PM PDT 24 295021538 ps
T248 /workspace/coverage/default/44.sram_ctrl_access_during_key_req.1302250204 Apr 18 02:16:39 PM PDT 24 Apr 18 02:25:10 PM PDT 24 16944014278 ps
T249 /workspace/coverage/default/37.sram_ctrl_bijection.890816478 Apr 18 02:15:12 PM PDT 24 Apr 18 02:15:48 PM PDT 24 2238882036 ps
T250 /workspace/coverage/default/47.sram_ctrl_ram_cfg.697579445 Apr 18 02:17:25 PM PDT 24 Apr 18 02:17:26 PM PDT 24 395194331 ps
T251 /workspace/coverage/default/37.sram_ctrl_ram_cfg.2335012990 Apr 18 02:15:20 PM PDT 24 Apr 18 02:15:21 PM PDT 24 45145465 ps
T252 /workspace/coverage/default/33.sram_ctrl_smoke.3620862974 Apr 18 02:14:26 PM PDT 24 Apr 18 02:15:00 PM PDT 24 4945887251 ps
T253 /workspace/coverage/default/42.sram_ctrl_mem_partial_access.113089639 Apr 18 02:16:18 PM PDT 24 Apr 18 02:16:21 PM PDT 24 118439237 ps
T254 /workspace/coverage/default/12.sram_ctrl_bijection.1352237131 Apr 18 02:10:39 PM PDT 24 Apr 18 02:10:54 PM PDT 24 919314370 ps
T255 /workspace/coverage/default/13.sram_ctrl_lc_escalation.3248831836 Apr 18 02:10:47 PM PDT 24 Apr 18 02:10:53 PM PDT 24 545163003 ps
T256 /workspace/coverage/default/9.sram_ctrl_executable.2484437828 Apr 18 02:10:15 PM PDT 24 Apr 18 02:15:16 PM PDT 24 4783765664 ps
T257 /workspace/coverage/default/41.sram_ctrl_ram_cfg.1824959967 Apr 18 02:16:11 PM PDT 24 Apr 18 02:16:12 PM PDT 24 37279865 ps
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T260 /workspace/coverage/default/11.sram_ctrl_multiple_keys.368125496 Apr 18 02:10:31 PM PDT 24 Apr 18 02:31:03 PM PDT 24 18633308139 ps
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T270 /workspace/coverage/default/10.sram_ctrl_partial_access_b2b.569497984 Apr 18 02:10:22 PM PDT 24 Apr 18 02:15:39 PM PDT 24 23492443180 ps
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T275 /workspace/coverage/default/15.sram_ctrl_access_during_key_req.2782751870 Apr 18 02:11:12 PM PDT 24 Apr 18 02:25:13 PM PDT 24 3117277633 ps
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T279 /workspace/coverage/default/49.sram_ctrl_lc_escalation.2201262323 Apr 18 02:17:51 PM PDT 24 Apr 18 02:17:59 PM PDT 24 2595055558 ps
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T288 /workspace/coverage/default/17.sram_ctrl_lc_escalation.2834056286 Apr 18 02:11:40 PM PDT 24 Apr 18 02:11:49 PM PDT 24 692239150 ps
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T291 /workspace/coverage/default/6.sram_ctrl_lc_escalation.4228518167 Apr 18 02:09:50 PM PDT 24 Apr 18 02:09:54 PM PDT 24 309442788 ps
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T293 /workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.2879489819 Apr 18 02:17:29 PM PDT 24 Apr 18 02:17:44 PM PDT 24 141181578 ps
T294 /workspace/coverage/default/33.sram_ctrl_lc_escalation.3338578325 Apr 18 02:14:31 PM PDT 24 Apr 18 02:14:38 PM PDT 24 1080457740 ps
T295 /workspace/coverage/default/26.sram_ctrl_executable.1591240880 Apr 18 02:13:11 PM PDT 24 Apr 18 02:20:45 PM PDT 24 29288667594 ps
T296 /workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2384118915 Apr 18 02:09:32 PM PDT 24 Apr 18 02:09:48 PM PDT 24 154884236 ps
T297 /workspace/coverage/default/12.sram_ctrl_lc_escalation.3971384343 Apr 18 02:10:45 PM PDT 24 Apr 18 02:10:53 PM PDT 24 691127672 ps
T298 /workspace/coverage/default/34.sram_ctrl_mem_walk.964826953 Apr 18 02:14:42 PM PDT 24 Apr 18 02:14:47 PM PDT 24 237867301 ps
T299 /workspace/coverage/default/33.sram_ctrl_regwen.3453385611 Apr 18 02:14:30 PM PDT 24 Apr 18 02:41:43 PM PDT 24 29861178830 ps
T300 /workspace/coverage/default/47.sram_ctrl_max_throughput.1670396892 Apr 18 02:17:20 PM PDT 24 Apr 18 02:17:39 PM PDT 24 77703137 ps
T301 /workspace/coverage/default/33.sram_ctrl_access_during_key_req.2458874436 Apr 18 02:14:32 PM PDT 24 Apr 18 02:27:24 PM PDT 24 3108305732 ps
T302 /workspace/coverage/default/7.sram_ctrl_partial_access.3812951083 Apr 18 02:09:51 PM PDT 24 Apr 18 02:10:01 PM PDT 24 186951171 ps
T303 /workspace/coverage/default/46.sram_ctrl_partial_access_b2b.3651245592 Apr 18 02:17:06 PM PDT 24 Apr 18 02:22:38 PM PDT 24 13410119586 ps
T110 /workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.2056762336 Apr 18 02:10:18 PM PDT 24 Apr 18 02:14:36 PM PDT 24 14326372935 ps
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