| T796 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3727038892 |
|
|
Apr 18 02:10:40 PM PDT 24 |
Apr 18 02:12:22 PM PDT 24 |
882640971 ps |
| T797 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1468502926 |
|
|
Apr 18 02:09:27 PM PDT 24 |
Apr 18 02:09:32 PM PDT 24 |
66459495 ps |
| T798 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3696569190 |
|
|
Apr 18 02:14:08 PM PDT 24 |
Apr 18 02:14:09 PM PDT 24 |
13108420 ps |
| T799 |
/workspace/coverage/default/17.sram_ctrl_bijection.625466000 |
|
|
Apr 18 02:11:39 PM PDT 24 |
Apr 18 02:12:27 PM PDT 24 |
729411295 ps |
| T800 |
/workspace/coverage/default/47.sram_ctrl_bijection.2216764060 |
|
|
Apr 18 02:17:17 PM PDT 24 |
Apr 18 02:18:10 PM PDT 24 |
2928594821 ps |
| T801 |
/workspace/coverage/default/0.sram_ctrl_stress_all.1164975045 |
|
|
Apr 18 02:08:58 PM PDT 24 |
Apr 18 03:27:28 PM PDT 24 |
172643488195 ps |
| T802 |
/workspace/coverage/default/17.sram_ctrl_executable.2548919135 |
|
|
Apr 18 02:11:40 PM PDT 24 |
Apr 18 02:21:37 PM PDT 24 |
2098019339 ps |
| T803 |
/workspace/coverage/default/47.sram_ctrl_partial_access_b2b.2866112644 |
|
|
Apr 18 02:17:20 PM PDT 24 |
Apr 18 02:22:34 PM PDT 24 |
152332669742 ps |
| T804 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.3343364417 |
|
|
Apr 18 02:10:47 PM PDT 24 |
Apr 18 02:10:54 PM PDT 24 |
1200133091 ps |
| T805 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.1620337216 |
|
|
Apr 18 02:11:39 PM PDT 24 |
Apr 18 02:12:36 PM PDT 24 |
103936372 ps |
| T806 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.2179085797 |
|
|
Apr 18 02:16:33 PM PDT 24 |
Apr 18 02:21:40 PM PDT 24 |
12821770098 ps |
| T807 |
/workspace/coverage/default/3.sram_ctrl_bijection.3740464945 |
|
|
Apr 18 02:09:26 PM PDT 24 |
Apr 18 02:10:23 PM PDT 24 |
7193521079 ps |
| T808 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.1485461938 |
|
|
Apr 18 02:10:31 PM PDT 24 |
Apr 18 02:10:33 PM PDT 24 |
37395175 ps |
| T809 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.1527072357 |
|
|
Apr 18 02:15:18 PM PDT 24 |
Apr 18 02:27:07 PM PDT 24 |
1925258194 ps |
| T810 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.2931028777 |
|
|
Apr 18 02:14:58 PM PDT 24 |
Apr 18 02:19:12 PM PDT 24 |
23235477571 ps |
| T811 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1484746890 |
|
|
Apr 18 02:13:58 PM PDT 24 |
Apr 18 02:14:48 PM PDT 24 |
124372579 ps |
| T812 |
/workspace/coverage/default/32.sram_ctrl_ram_cfg.94831941 |
|
|
Apr 18 02:14:20 PM PDT 24 |
Apr 18 02:14:21 PM PDT 24 |
46153229 ps |
| T813 |
/workspace/coverage/default/16.sram_ctrl_partial_access.3088250696 |
|
|
Apr 18 02:11:21 PM PDT 24 |
Apr 18 02:11:25 PM PDT 24 |
208374071 ps |
| T814 |
/workspace/coverage/default/19.sram_ctrl_stress_all.872484191 |
|
|
Apr 18 02:11:50 PM PDT 24 |
Apr 18 02:25:28 PM PDT 24 |
17057998889 ps |
| T815 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.3395931786 |
|
|
Apr 18 02:15:36 PM PDT 24 |
Apr 18 02:15:44 PM PDT 24 |
145317912 ps |
| T39 |
/workspace/coverage/default/4.sram_ctrl_sec_cm.3105927677 |
|
|
Apr 18 02:09:39 PM PDT 24 |
Apr 18 02:09:42 PM PDT 24 |
902037085 ps |
| T816 |
/workspace/coverage/default/21.sram_ctrl_bijection.234951923 |
|
|
Apr 18 02:12:25 PM PDT 24 |
Apr 18 02:13:22 PM PDT 24 |
9355531574 ps |
| T817 |
/workspace/coverage/default/22.sram_ctrl_throughput_w_partial_write.660446595 |
|
|
Apr 18 02:12:18 PM PDT 24 |
Apr 18 02:13:53 PM PDT 24 |
267261300 ps |
| T818 |
/workspace/coverage/default/16.sram_ctrl_stress_all.2619367760 |
|
|
Apr 18 02:11:43 PM PDT 24 |
Apr 18 02:34:59 PM PDT 24 |
42071291069 ps |
| T819 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.3761526452 |
|
|
Apr 18 02:10:25 PM PDT 24 |
Apr 18 02:11:40 PM PDT 24 |
455516529 ps |
| T820 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.3753258364 |
|
|
Apr 18 02:10:58 PM PDT 24 |
Apr 18 02:11:10 PM PDT 24 |
1876512628 ps |
| T821 |
/workspace/coverage/default/23.sram_ctrl_smoke.2978126395 |
|
|
Apr 18 02:12:24 PM PDT 24 |
Apr 18 02:12:36 PM PDT 24 |
193476267 ps |
| T822 |
/workspace/coverage/default/5.sram_ctrl_alert_test.1618254606 |
|
|
Apr 18 02:09:45 PM PDT 24 |
Apr 18 02:09:46 PM PDT 24 |
33823430 ps |
| T823 |
/workspace/coverage/default/9.sram_ctrl_smoke.2254407342 |
|
|
Apr 18 02:10:11 PM PDT 24 |
Apr 18 02:10:18 PM PDT 24 |
126961674 ps |
| T824 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1389520409 |
|
|
Apr 18 02:14:33 PM PDT 24 |
Apr 18 02:15:17 PM PDT 24 |
421511711 ps |
| T825 |
/workspace/coverage/default/15.sram_ctrl_ram_cfg.1051809273 |
|
|
Apr 18 02:11:11 PM PDT 24 |
Apr 18 02:11:12 PM PDT 24 |
44152446 ps |
| T826 |
/workspace/coverage/default/27.sram_ctrl_smoke.2085195265 |
|
|
Apr 18 02:13:21 PM PDT 24 |
Apr 18 02:13:31 PM PDT 24 |
313480642 ps |
| T827 |
/workspace/coverage/default/34.sram_ctrl_alert_test.454402320 |
|
|
Apr 18 02:14:43 PM PDT 24 |
Apr 18 02:14:44 PM PDT 24 |
17442565 ps |
| T828 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.2618753013 |
|
|
Apr 18 02:10:53 PM PDT 24 |
Apr 18 02:26:31 PM PDT 24 |
17922125392 ps |
| T829 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.2404345877 |
|
|
Apr 18 02:10:17 PM PDT 24 |
Apr 18 02:19:09 PM PDT 24 |
42448978415 ps |
| T830 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.2805176219 |
|
|
Apr 18 02:12:42 PM PDT 24 |
Apr 18 02:16:51 PM PDT 24 |
9891188872 ps |
| T831 |
/workspace/coverage/default/17.sram_ctrl_stress_all.2901238934 |
|
|
Apr 18 02:11:38 PM PDT 24 |
Apr 18 02:37:51 PM PDT 24 |
6194653113 ps |
| T832 |
/workspace/coverage/default/23.sram_ctrl_regwen.3800147211 |
|
|
Apr 18 02:12:29 PM PDT 24 |
Apr 18 02:26:40 PM PDT 24 |
4073622697 ps |
| T833 |
/workspace/coverage/default/4.sram_ctrl_smoke.3711066201 |
|
|
Apr 18 02:09:32 PM PDT 24 |
Apr 18 02:09:42 PM PDT 24 |
636285149 ps |
| T834 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.3325471484 |
|
|
Apr 18 02:09:02 PM PDT 24 |
Apr 18 02:13:41 PM PDT 24 |
4030742916 ps |
| T835 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.3159333576 |
|
|
Apr 18 02:09:00 PM PDT 24 |
Apr 18 02:11:38 PM PDT 24 |
6769490834 ps |
| T836 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.565955591 |
|
|
Apr 18 02:15:32 PM PDT 24 |
Apr 18 02:21:41 PM PDT 24 |
2769485909 ps |
| T837 |
/workspace/coverage/default/23.sram_ctrl_stress_pipeline.2672646581 |
|
|
Apr 18 02:12:26 PM PDT 24 |
Apr 18 02:15:37 PM PDT 24 |
7856130274 ps |
| T838 |
/workspace/coverage/default/13.sram_ctrl_smoke.1266648308 |
|
|
Apr 18 02:10:45 PM PDT 24 |
Apr 18 02:10:47 PM PDT 24 |
124558613 ps |
| T839 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.3398089444 |
|
|
Apr 18 02:14:56 PM PDT 24 |
Apr 18 02:16:32 PM PDT 24 |
263293636 ps |
| T840 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.1799021818 |
|
|
Apr 18 02:16:11 PM PDT 24 |
Apr 18 02:18:44 PM PDT 24 |
139302914 ps |
| T841 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.2789631424 |
|
|
Apr 18 02:09:51 PM PDT 24 |
Apr 18 02:21:51 PM PDT 24 |
2826740907 ps |
| T842 |
/workspace/coverage/default/5.sram_ctrl_executable.1381100661 |
|
|
Apr 18 02:09:45 PM PDT 24 |
Apr 18 02:21:01 PM PDT 24 |
18567020324 ps |
| T843 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.2626463949 |
|
|
Apr 18 02:15:19 PM PDT 24 |
Apr 18 02:16:33 PM PDT 24 |
4948509253 ps |
| T844 |
/workspace/coverage/default/11.sram_ctrl_regwen.4165933359 |
|
|
Apr 18 02:10:31 PM PDT 24 |
Apr 18 02:19:06 PM PDT 24 |
10568117719 ps |
| T845 |
/workspace/coverage/default/6.sram_ctrl_regwen.1369920044 |
|
|
Apr 18 02:09:45 PM PDT 24 |
Apr 18 02:38:01 PM PDT 24 |
20975250149 ps |
| T846 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.327086171 |
|
|
Apr 18 02:15:42 PM PDT 24 |
Apr 18 02:27:53 PM PDT 24 |
3997812338 ps |
| T847 |
/workspace/coverage/default/4.sram_ctrl_bijection.35097968 |
|
|
Apr 18 02:09:33 PM PDT 24 |
Apr 18 02:09:49 PM PDT 24 |
452695005 ps |
| T848 |
/workspace/coverage/default/24.sram_ctrl_bijection.1005757397 |
|
|
Apr 18 02:12:42 PM PDT 24 |
Apr 18 02:14:08 PM PDT 24 |
51695811049 ps |
| T849 |
/workspace/coverage/default/44.sram_ctrl_smoke.3250191521 |
|
|
Apr 18 02:16:28 PM PDT 24 |
Apr 18 02:16:32 PM PDT 24 |
104535111 ps |
| T850 |
/workspace/coverage/default/6.sram_ctrl_partial_access.1599831785 |
|
|
Apr 18 02:09:44 PM PDT 24 |
Apr 18 02:09:59 PM PDT 24 |
801514907 ps |
| T851 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1671691465 |
|
|
Apr 18 02:10:57 PM PDT 24 |
Apr 18 02:11:03 PM PDT 24 |
445351133 ps |
| T852 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.1239767210 |
|
|
Apr 18 02:13:33 PM PDT 24 |
Apr 18 02:13:43 PM PDT 24 |
607355908 ps |
| T853 |
/workspace/coverage/default/27.sram_ctrl_bijection.4229263307 |
|
|
Apr 18 02:13:23 PM PDT 24 |
Apr 18 02:13:50 PM PDT 24 |
562325545 ps |
| T854 |
/workspace/coverage/default/5.sram_ctrl_bijection.2554292626 |
|
|
Apr 18 02:09:40 PM PDT 24 |
Apr 18 02:10:53 PM PDT 24 |
7326572606 ps |
| T855 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.3067242351 |
|
|
Apr 18 02:11:55 PM PDT 24 |
Apr 18 02:27:52 PM PDT 24 |
3202758272 ps |
| T856 |
/workspace/coverage/default/34.sram_ctrl_executable.2288347691 |
|
|
Apr 18 02:14:41 PM PDT 24 |
Apr 18 02:19:57 PM PDT 24 |
7288207505 ps |
| T857 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3828364405 |
|
|
Apr 18 02:18:04 PM PDT 24 |
Apr 18 02:26:38 PM PDT 24 |
34753769290 ps |
| T858 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.651307576 |
|
|
Apr 18 02:10:05 PM PDT 24 |
Apr 18 02:16:58 PM PDT 24 |
1406167043 ps |
| T859 |
/workspace/coverage/default/42.sram_ctrl_regwen.907419420 |
|
|
Apr 18 02:16:18 PM PDT 24 |
Apr 18 02:20:33 PM PDT 24 |
9730215064 ps |
| T860 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.3978829939 |
|
|
Apr 18 02:09:20 PM PDT 24 |
Apr 18 02:09:25 PM PDT 24 |
921997714 ps |
| T861 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.2568603569 |
|
|
Apr 18 02:15:11 PM PDT 24 |
Apr 18 02:15:15 PM PDT 24 |
230187360 ps |
| T862 |
/workspace/coverage/default/2.sram_ctrl_regwen.4055081768 |
|
|
Apr 18 02:09:20 PM PDT 24 |
Apr 18 02:17:29 PM PDT 24 |
67365940593 ps |
| T863 |
/workspace/coverage/default/42.sram_ctrl_alert_test.1602624117 |
|
|
Apr 18 02:16:25 PM PDT 24 |
Apr 18 02:16:26 PM PDT 24 |
30617962 ps |
| T864 |
/workspace/coverage/default/24.sram_ctrl_alert_test.1071795032 |
|
|
Apr 18 02:12:53 PM PDT 24 |
Apr 18 02:12:54 PM PDT 24 |
41391151 ps |
| T865 |
/workspace/coverage/default/6.sram_ctrl_bijection.2046875320 |
|
|
Apr 18 02:09:46 PM PDT 24 |
Apr 18 02:10:33 PM PDT 24 |
4522997298 ps |
| T866 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.14576541 |
|
|
Apr 18 02:11:39 PM PDT 24 |
Apr 18 02:15:37 PM PDT 24 |
6602252407 ps |
| T867 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.3416214727 |
|
|
Apr 18 02:10:44 PM PDT 24 |
Apr 18 02:18:23 PM PDT 24 |
1183942450 ps |
| T868 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.1371336159 |
|
|
Apr 18 02:15:47 PM PDT 24 |
Apr 18 02:20:59 PM PDT 24 |
23544480725 ps |
| T869 |
/workspace/coverage/default/48.sram_ctrl_smoke.1183480690 |
|
|
Apr 18 02:17:28 PM PDT 24 |
Apr 18 02:19:24 PM PDT 24 |
1949098373 ps |
| T870 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.3807527435 |
|
|
Apr 18 02:16:42 PM PDT 24 |
Apr 18 02:16:52 PM PDT 24 |
443288453 ps |
| T871 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.37783824 |
|
|
Apr 18 02:10:47 PM PDT 24 |
Apr 18 02:13:18 PM PDT 24 |
7002250363 ps |
| T872 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.513995546 |
|
|
Apr 18 02:11:42 PM PDT 24 |
Apr 18 02:11:43 PM PDT 24 |
42705321 ps |
| T873 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.1082169123 |
|
|
Apr 18 02:12:09 PM PDT 24 |
Apr 18 02:15:54 PM PDT 24 |
15229478612 ps |
| T874 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.296177801 |
|
|
Apr 18 02:14:58 PM PDT 24 |
Apr 18 02:22:38 PM PDT 24 |
297422715604 ps |
| T875 |
/workspace/coverage/default/41.sram_ctrl_stress_all.479469416 |
|
|
Apr 18 02:16:15 PM PDT 24 |
Apr 18 02:26:18 PM PDT 24 |
62275599847 ps |
| T876 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1696936378 |
|
|
Apr 18 02:11:41 PM PDT 24 |
Apr 18 02:12:15 PM PDT 24 |
712199027 ps |
| T877 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3014290328 |
|
|
Apr 18 02:16:08 PM PDT 24 |
Apr 18 02:16:22 PM PDT 24 |
881781404 ps |
| T878 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.1814490850 |
|
|
Apr 18 02:11:43 PM PDT 24 |
Apr 18 02:13:44 PM PDT 24 |
179279591 ps |
| T879 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.3777142186 |
|
|
Apr 18 02:13:32 PM PDT 24 |
Apr 18 02:19:20 PM PDT 24 |
3515813867 ps |
| T880 |
/workspace/coverage/default/20.sram_ctrl_regwen.1023497730 |
|
|
Apr 18 02:11:56 PM PDT 24 |
Apr 18 02:21:20 PM PDT 24 |
8792665895 ps |
| T881 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1090860451 |
|
|
Apr 18 02:14:37 PM PDT 24 |
Apr 18 02:17:17 PM PDT 24 |
1779644646 ps |
| T882 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.997062805 |
|
|
Apr 18 02:11:39 PM PDT 24 |
Apr 18 02:32:54 PM PDT 24 |
4008716496 ps |
| T883 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.2712115034 |
|
|
Apr 18 02:10:00 PM PDT 24 |
Apr 18 02:13:08 PM PDT 24 |
2010754434 ps |
| T884 |
/workspace/coverage/default/20.sram_ctrl_mem_walk.3553003696 |
|
|
Apr 18 02:11:57 PM PDT 24 |
Apr 18 02:12:08 PM PDT 24 |
4846137425 ps |
| T885 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.360406401 |
|
|
Apr 18 02:10:31 PM PDT 24 |
Apr 18 02:13:28 PM PDT 24 |
4259883530 ps |
| T886 |
/workspace/coverage/default/32.sram_ctrl_alert_test.1306082799 |
|
|
Apr 18 02:14:23 PM PDT 24 |
Apr 18 02:14:24 PM PDT 24 |
34723156 ps |
| T887 |
/workspace/coverage/default/37.sram_ctrl_stress_all.3726420640 |
|
|
Apr 18 02:15:20 PM PDT 24 |
Apr 18 02:43:19 PM PDT 24 |
104004653844 ps |
| T888 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.3596190201 |
|
|
Apr 18 02:10:54 PM PDT 24 |
Apr 18 02:10:58 PM PDT 24 |
29294765 ps |
| T889 |
/workspace/coverage/default/18.sram_ctrl_stress_all_with_rand_reset.1821251038 |
|
|
Apr 18 02:11:39 PM PDT 24 |
Apr 18 02:12:54 PM PDT 24 |
12622274526 ps |
| T890 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.1592678687 |
|
|
Apr 18 02:17:38 PM PDT 24 |
Apr 18 02:21:27 PM PDT 24 |
3236342718 ps |
| T891 |
/workspace/coverage/default/12.sram_ctrl_executable.3232953752 |
|
|
Apr 18 02:10:45 PM PDT 24 |
Apr 18 02:16:12 PM PDT 24 |
2185373409 ps |
| T892 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3282472589 |
|
|
Apr 18 02:09:52 PM PDT 24 |
Apr 18 02:09:55 PM PDT 24 |
160549421 ps |
| T893 |
/workspace/coverage/default/46.sram_ctrl_bijection.2576448217 |
|
|
Apr 18 02:17:36 PM PDT 24 |
Apr 18 02:18:37 PM PDT 24 |
11511317980 ps |
| T894 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.3321924974 |
|
|
Apr 18 02:11:39 PM PDT 24 |
Apr 18 02:21:25 PM PDT 24 |
99148528928 ps |
| T895 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.2990638038 |
|
|
Apr 18 02:14:44 PM PDT 24 |
Apr 18 02:15:11 PM PDT 24 |
341800107 ps |
| T896 |
/workspace/coverage/default/19.sram_ctrl_regwen.4105059528 |
|
|
Apr 18 02:11:55 PM PDT 24 |
Apr 18 02:25:23 PM PDT 24 |
8335119788 ps |
| T897 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.649452949 |
|
|
Apr 18 02:10:38 PM PDT 24 |
Apr 18 02:36:36 PM PDT 24 |
68923048738 ps |
| T898 |
/workspace/coverage/default/42.sram_ctrl_stress_pipeline.679388077 |
|
|
Apr 18 02:16:20 PM PDT 24 |
Apr 18 02:19:44 PM PDT 24 |
8329359209 ps |
| T899 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.4007629690 |
|
|
Apr 18 02:16:55 PM PDT 24 |
Apr 18 02:17:59 PM PDT 24 |
225777014 ps |
| T900 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.3311106956 |
|
|
Apr 18 02:13:26 PM PDT 24 |
Apr 18 02:20:43 PM PDT 24 |
4977842743 ps |
| T901 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.717436513 |
|
|
Apr 18 02:15:46 PM PDT 24 |
Apr 18 02:15:50 PM PDT 24 |
1380750806 ps |
| T902 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.3332556139 |
|
|
Apr 18 02:10:47 PM PDT 24 |
Apr 18 02:10:50 PM PDT 24 |
84974376 ps |
| T903 |
/workspace/coverage/default/21.sram_ctrl_mem_walk.2722215487 |
|
|
Apr 18 02:12:13 PM PDT 24 |
Apr 18 02:12:22 PM PDT 24 |
1692040172 ps |
| T904 |
/workspace/coverage/default/4.sram_ctrl_executable.2895506021 |
|
|
Apr 18 02:09:33 PM PDT 24 |
Apr 18 02:31:48 PM PDT 24 |
110700273057 ps |
| T905 |
/workspace/coverage/default/36.sram_ctrl_regwen.3993524825 |
|
|
Apr 18 02:15:06 PM PDT 24 |
Apr 18 02:39:45 PM PDT 24 |
64832589625 ps |
| T906 |
/workspace/coverage/default/41.sram_ctrl_alert_test.3641188943 |
|
|
Apr 18 02:16:16 PM PDT 24 |
Apr 18 02:16:17 PM PDT 24 |
28602409 ps |
| T907 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3234370277 |
|
|
Apr 18 02:17:19 PM PDT 24 |
Apr 18 02:21:20 PM PDT 24 |
4932866098 ps |
| T908 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.1320859760 |
|
|
Apr 18 02:12:48 PM PDT 24 |
Apr 18 02:18:07 PM PDT 24 |
2129262830 ps |
| T909 |
/workspace/coverage/default/36.sram_ctrl_smoke.1113771881 |
|
|
Apr 18 02:14:57 PM PDT 24 |
Apr 18 02:15:39 PM PDT 24 |
200090787 ps |
| T910 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2838162074 |
|
|
Apr 18 02:09:48 PM PDT 24 |
Apr 18 02:09:49 PM PDT 24 |
26965576 ps |
| T911 |
/workspace/coverage/default/38.sram_ctrl_regwen.2601393439 |
|
|
Apr 18 02:15:29 PM PDT 24 |
Apr 18 02:19:36 PM PDT 24 |
4816086426 ps |
| T912 |
/workspace/coverage/default/3.sram_ctrl_alert_test.3720579145 |
|
|
Apr 18 02:09:32 PM PDT 24 |
Apr 18 02:09:34 PM PDT 24 |
13061329 ps |
| T913 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.3617401663 |
|
|
Apr 18 02:16:01 PM PDT 24 |
Apr 18 02:18:43 PM PDT 24 |
3379167908 ps |
| T914 |
/workspace/coverage/default/27.sram_ctrl_partial_access.889591066 |
|
|
Apr 18 02:13:24 PM PDT 24 |
Apr 18 02:13:28 PM PDT 24 |
76352830 ps |
| T915 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.2054967629 |
|
|
Apr 18 02:13:11 PM PDT 24 |
Apr 18 02:30:13 PM PDT 24 |
2675908874 ps |
| T916 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.3522264468 |
|
|
Apr 18 02:10:31 PM PDT 24 |
Apr 18 02:10:32 PM PDT 24 |
92536009 ps |
| T917 |
/workspace/coverage/default/11.sram_ctrl_partial_access.2806200092 |
|
|
Apr 18 02:10:32 PM PDT 24 |
Apr 18 02:10:45 PM PDT 24 |
1218434151 ps |
| T918 |
/workspace/coverage/default/43.sram_ctrl_max_throughput.209991089 |
|
|
Apr 18 02:16:24 PM PDT 24 |
Apr 18 02:18:25 PM PDT 24 |
145312342 ps |
| T919 |
/workspace/coverage/default/45.sram_ctrl_bijection.649694822 |
|
|
Apr 18 02:16:49 PM PDT 24 |
Apr 18 02:18:01 PM PDT 24 |
43223622330 ps |
| T920 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.1629498329 |
|
|
Apr 18 02:16:09 PM PDT 24 |
Apr 18 02:16:14 PM PDT 24 |
138868633 ps |
| T921 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.4138066849 |
|
|
Apr 18 02:15:11 PM PDT 24 |
Apr 18 02:21:55 PM PDT 24 |
2414380145 ps |
| T922 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1254554871 |
|
|
Apr 18 02:10:23 PM PDT 24 |
Apr 18 02:45:54 PM PDT 24 |
72726492046 ps |
| T923 |
/workspace/coverage/default/30.sram_ctrl_bijection.3036556541 |
|
|
Apr 18 02:13:52 PM PDT 24 |
Apr 18 02:15:15 PM PDT 24 |
50322749908 ps |
| T924 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1623923493 |
|
|
Apr 18 02:17:29 PM PDT 24 |
Apr 18 02:23:38 PM PDT 24 |
8795421424 ps |
| T925 |
/workspace/coverage/default/24.sram_ctrl_max_throughput.1571045778 |
|
|
Apr 18 02:12:42 PM PDT 24 |
Apr 18 02:14:59 PM PDT 24 |
165056965 ps |
| T926 |
/workspace/coverage/default/35.sram_ctrl_max_throughput.4058566015 |
|
|
Apr 18 02:14:46 PM PDT 24 |
Apr 18 02:14:59 PM PDT 24 |
304311484 ps |
| T927 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.1433474121 |
|
|
Apr 18 02:13:53 PM PDT 24 |
Apr 18 02:19:09 PM PDT 24 |
15739995738 ps |
| T928 |
/workspace/coverage/default/33.sram_ctrl_alert_test.598834532 |
|
|
Apr 18 02:14:31 PM PDT 24 |
Apr 18 02:14:32 PM PDT 24 |
37998197 ps |
| T929 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2779203205 |
|
|
Apr 18 02:10:47 PM PDT 24 |
Apr 18 02:15:14 PM PDT 24 |
14934876970 ps |
| T930 |
/workspace/coverage/default/11.sram_ctrl_lc_escalation.3836069626 |
|
|
Apr 18 02:10:30 PM PDT 24 |
Apr 18 02:10:33 PM PDT 24 |
91646283 ps |
| T931 |
/workspace/coverage/default/29.sram_ctrl_regwen.3963813623 |
|
|
Apr 18 02:13:49 PM PDT 24 |
Apr 18 02:18:44 PM PDT 24 |
4458375990 ps |
| T932 |
/workspace/coverage/default/4.sram_ctrl_regwen.5978887 |
|
|
Apr 18 02:09:41 PM PDT 24 |
Apr 18 02:36:07 PM PDT 24 |
87720998293 ps |
| T933 |
/workspace/coverage/default/5.sram_ctrl_smoke.259339061 |
|
|
Apr 18 02:09:45 PM PDT 24 |
Apr 18 02:11:21 PM PDT 24 |
532595450 ps |
| T934 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3166614957 |
|
|
Apr 18 02:09:26 PM PDT 24 |
Apr 18 02:11:48 PM PDT 24 |
6451812022 ps |
| T65 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.3412716559 |
|
|
Apr 18 01:55:32 PM PDT 24 |
Apr 18 01:55:36 PM PDT 24 |
4499647394 ps |
| T935 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3008895865 |
|
|
Apr 18 01:55:06 PM PDT 24 |
Apr 18 01:55:07 PM PDT 24 |
56609846 ps |
| T936 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2757675 |
|
|
Apr 18 01:55:14 PM PDT 24 |
Apr 18 01:55:16 PM PDT 24 |
39852165 ps |
| T937 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4234537163 |
|
|
Apr 18 01:55:16 PM PDT 24 |
Apr 18 01:55:21 PM PDT 24 |
802836168 ps |
| T95 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3228292946 |
|
|
Apr 18 01:55:09 PM PDT 24 |
Apr 18 01:55:10 PM PDT 24 |
13578370 ps |
| T66 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.80102319 |
|
|
Apr 18 01:55:26 PM PDT 24 |
Apr 18 01:55:27 PM PDT 24 |
37067444 ps |
| T105 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3296311631 |
|
|
Apr 18 01:55:30 PM PDT 24 |
Apr 18 01:55:32 PM PDT 24 |
39434935 ps |
| T107 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4019037753 |
|
|
Apr 18 01:55:26 PM PDT 24 |
Apr 18 01:55:28 PM PDT 24 |
134104914 ps |
| T938 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.558810247 |
|
|
Apr 18 01:55:16 PM PDT 24 |
Apr 18 01:55:17 PM PDT 24 |
30067218 ps |
| T939 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1794940731 |
|
|
Apr 18 01:55:09 PM PDT 24 |
Apr 18 01:55:12 PM PDT 24 |
32615579 ps |
| T67 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2568083145 |
|
|
Apr 18 01:55:21 PM PDT 24 |
Apr 18 01:55:23 PM PDT 24 |
14937908 ps |
| T68 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2359091891 |
|
|
Apr 18 01:55:29 PM PDT 24 |
Apr 18 01:55:31 PM PDT 24 |
114431739 ps |
| T69 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3471153360 |
|
|
Apr 18 01:54:57 PM PDT 24 |
Apr 18 01:54:58 PM PDT 24 |
20932534 ps |
| T108 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.565001263 |
|
|
Apr 18 01:55:12 PM PDT 24 |
Apr 18 01:55:14 PM PDT 24 |
150376553 ps |
| T940 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.131662194 |
|
|
Apr 18 01:54:56 PM PDT 24 |
Apr 18 01:54:59 PM PDT 24 |
69545240 ps |
| T109 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.4104259024 |
|
|
Apr 18 01:55:08 PM PDT 24 |
Apr 18 01:55:10 PM PDT 24 |
242485048 ps |
| T941 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1786191416 |
|
|
Apr 18 01:55:10 PM PDT 24 |
Apr 18 01:55:14 PM PDT 24 |
114599228 ps |
| T942 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1132246973 |
|
|
Apr 18 01:55:14 PM PDT 24 |
Apr 18 01:55:16 PM PDT 24 |
25669895 ps |
| T943 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2039721758 |
|
|
Apr 18 01:55:11 PM PDT 24 |
Apr 18 01:55:12 PM PDT 24 |
33169783 ps |
| T96 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3914582808 |
|
|
Apr 18 01:55:04 PM PDT 24 |
Apr 18 01:55:05 PM PDT 24 |
35676766 ps |
| T944 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2225374141 |
|
|
Apr 18 01:55:38 PM PDT 24 |
Apr 18 01:55:43 PM PDT 24 |
130318919 ps |
| T106 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.914264160 |
|
|
Apr 18 01:54:58 PM PDT 24 |
Apr 18 01:55:00 PM PDT 24 |
187905470 ps |
| T945 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.233743262 |
|
|
Apr 18 01:55:34 PM PDT 24 |
Apr 18 01:55:38 PM PDT 24 |
145448680 ps |
| T70 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2075716151 |
|
|
Apr 18 01:55:10 PM PDT 24 |
Apr 18 01:55:13 PM PDT 24 |
816872635 ps |
| T97 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3895674981 |
|
|
Apr 18 01:55:20 PM PDT 24 |
Apr 18 01:55:21 PM PDT 24 |
39879425 ps |
| T946 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1017135575 |
|
|
Apr 18 01:55:19 PM PDT 24 |
Apr 18 01:55:23 PM PDT 24 |
459355007 ps |
| T71 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1925311704 |
|
|
Apr 18 01:55:04 PM PDT 24 |
Apr 18 01:55:05 PM PDT 24 |
93282790 ps |
| T72 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2332909439 |
|
|
Apr 18 01:55:04 PM PDT 24 |
Apr 18 01:55:07 PM PDT 24 |
43183678 ps |
| T947 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3242432353 |
|
|
Apr 18 01:55:19 PM PDT 24 |
Apr 18 01:55:24 PM PDT 24 |
165693156 ps |
| T123 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.4107133199 |
|
|
Apr 18 01:55:02 PM PDT 24 |
Apr 18 01:55:05 PM PDT 24 |
321192738 ps |
| T948 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.4056131309 |
|
|
Apr 18 01:55:33 PM PDT 24 |
Apr 18 01:55:37 PM PDT 24 |
62813557 ps |
| T949 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3944109940 |
|
|
Apr 18 01:55:30 PM PDT 24 |
Apr 18 01:55:35 PM PDT 24 |
285938494 ps |
| T73 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.269384627 |
|
|
Apr 18 01:55:19 PM PDT 24 |
Apr 18 01:55:22 PM PDT 24 |
603048167 ps |
| T74 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1443030090 |
|
|
Apr 18 01:55:11 PM PDT 24 |
Apr 18 01:55:12 PM PDT 24 |
24642621 ps |
| T98 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.853290316 |
|
|
Apr 18 01:55:14 PM PDT 24 |
Apr 18 01:55:15 PM PDT 24 |
58874240 ps |
| T77 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.770900020 |
|
|
Apr 18 01:55:24 PM PDT 24 |
Apr 18 01:55:26 PM PDT 24 |
222044224 ps |
| T78 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4147562867 |
|
|
Apr 18 01:55:04 PM PDT 24 |
Apr 18 01:55:08 PM PDT 24 |
2923341063 ps |
| T950 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.3736907771 |
|
|
Apr 18 01:55:32 PM PDT 24 |
Apr 18 01:55:34 PM PDT 24 |
230224785 ps |
| T127 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3512304238 |
|
|
Apr 18 01:55:33 PM PDT 24 |
Apr 18 01:55:35 PM PDT 24 |
1294960915 ps |
| T951 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3883493153 |
|
|
Apr 18 01:55:25 PM PDT 24 |
Apr 18 01:55:26 PM PDT 24 |
28438429 ps |
| T952 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1651729199 |
|
|
Apr 18 01:55:34 PM PDT 24 |
Apr 18 01:55:35 PM PDT 24 |
34520454 ps |
| T953 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3293204964 |
|
|
Apr 18 01:55:02 PM PDT 24 |
Apr 18 01:55:05 PM PDT 24 |
51748692 ps |
| T128 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2082185385 |
|
|
Apr 18 01:55:14 PM PDT 24 |
Apr 18 01:55:17 PM PDT 24 |
158047865 ps |
| T954 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.2171359176 |
|
|
Apr 18 01:55:23 PM PDT 24 |
Apr 18 01:55:24 PM PDT 24 |
17962317 ps |
| T955 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1024501512 |
|
|
Apr 18 01:55:05 PM PDT 24 |
Apr 18 01:55:06 PM PDT 24 |
15130319 ps |
| T956 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3576887034 |
|
|
Apr 18 01:55:07 PM PDT 24 |
Apr 18 01:55:10 PM PDT 24 |
89526089 ps |
| T79 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3534548329 |
|
|
Apr 18 01:55:23 PM PDT 24 |
Apr 18 01:55:26 PM PDT 24 |
1384302895 ps |
| T957 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1978521921 |
|
|
Apr 18 01:55:04 PM PDT 24 |
Apr 18 01:55:06 PM PDT 24 |
28079153 ps |
| T958 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1950584566 |
|
|
Apr 18 01:55:14 PM PDT 24 |
Apr 18 01:55:15 PM PDT 24 |
18526477 ps |
| T80 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.4010955865 |
|
|
Apr 18 01:55:21 PM PDT 24 |
Apr 18 01:55:22 PM PDT 24 |
12583335 ps |
| T81 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2206094803 |
|
|
Apr 18 01:55:20 PM PDT 24 |
Apr 18 01:55:21 PM PDT 24 |
30464788 ps |
| T124 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2913075275 |
|
|
Apr 18 01:55:31 PM PDT 24 |
Apr 18 01:55:34 PM PDT 24 |
262964273 ps |
| T959 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4052051937 |
|
|
Apr 18 01:55:21 PM PDT 24 |
Apr 18 01:55:22 PM PDT 24 |
30811810 ps |
| T960 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3584964283 |
|
|
Apr 18 01:55:22 PM PDT 24 |
Apr 18 01:55:24 PM PDT 24 |
48424766 ps |
| T130 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1609616651 |
|
|
Apr 18 01:55:17 PM PDT 24 |
Apr 18 01:55:20 PM PDT 24 |
365242588 ps |
| T129 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3280602533 |
|
|
Apr 18 01:55:02 PM PDT 24 |
Apr 18 01:55:05 PM PDT 24 |
494928921 ps |
| T961 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.4276133481 |
|
|
Apr 18 01:55:30 PM PDT 24 |
Apr 18 01:55:32 PM PDT 24 |
67161953 ps |
| T89 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1572528095 |
|
|
Apr 18 01:55:05 PM PDT 24 |
Apr 18 01:55:06 PM PDT 24 |
52087834 ps |
| T962 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.1157605002 |
|
|
Apr 18 01:55:07 PM PDT 24 |
Apr 18 01:55:09 PM PDT 24 |
131007207 ps |
| T963 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1727910295 |
|
|
Apr 18 01:55:07 PM PDT 24 |
Apr 18 01:55:09 PM PDT 24 |
16790465 ps |
| T964 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1692935820 |
|
|
Apr 18 01:55:26 PM PDT 24 |
Apr 18 01:55:29 PM PDT 24 |
63635319 ps |
| T136 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1275287682 |
|
|
Apr 18 01:55:27 PM PDT 24 |
Apr 18 01:55:30 PM PDT 24 |
243027674 ps |
| T93 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1939908385 |
|
|
Apr 18 01:55:30 PM PDT 24 |
Apr 18 01:55:31 PM PDT 24 |
10612873 ps |
| T965 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2686386858 |
|
|
Apr 18 01:55:14 PM PDT 24 |
Apr 18 01:55:15 PM PDT 24 |
81347288 ps |
| T966 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.338825293 |
|
|
Apr 18 01:55:10 PM PDT 24 |
Apr 18 01:55:13 PM PDT 24 |
1527472234 ps |
| T90 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2288722216 |
|
|
Apr 18 01:55:09 PM PDT 24 |
Apr 18 01:55:10 PM PDT 24 |
22299354 ps |
| T91 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.4154310869 |
|
|
Apr 18 01:55:26 PM PDT 24 |
Apr 18 01:55:29 PM PDT 24 |
794071271 ps |
| T131 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3264925902 |
|
|
Apr 18 01:55:31 PM PDT 24 |
Apr 18 01:55:34 PM PDT 24 |
272880799 ps |
| T967 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.1854169566 |
|
|
Apr 18 01:55:16 PM PDT 24 |
Apr 18 01:55:17 PM PDT 24 |
98130866 ps |
| T968 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1566676187 |
|
|
Apr 18 01:55:08 PM PDT 24 |
Apr 18 01:55:09 PM PDT 24 |
14090063 ps |
| T969 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2281962296 |
|
|
Apr 18 01:55:26 PM PDT 24 |
Apr 18 01:55:29 PM PDT 24 |
327448009 ps |
| T970 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.451717746 |
|
|
Apr 18 01:55:07 PM PDT 24 |
Apr 18 01:55:08 PM PDT 24 |
150922670 ps |
| T971 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1472482568 |
|
|
Apr 18 01:55:15 PM PDT 24 |
Apr 18 01:55:17 PM PDT 24 |
2297583239 ps |
| T972 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3398777732 |
|
|
Apr 18 01:55:30 PM PDT 24 |
Apr 18 01:55:35 PM PDT 24 |
158042100 ps |
| T92 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2689034798 |
|
|
Apr 18 01:54:59 PM PDT 24 |
Apr 18 01:55:00 PM PDT 24 |
17935547 ps |
| T973 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2652498480 |
|
|
Apr 18 01:55:25 PM PDT 24 |
Apr 18 01:55:26 PM PDT 24 |
41265973 ps |
| T974 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2613102744 |
|
|
Apr 18 01:54:59 PM PDT 24 |
Apr 18 01:55:02 PM PDT 24 |
846764554 ps |
| T125 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1125049441 |
|
|
Apr 18 01:55:13 PM PDT 24 |
Apr 18 01:55:15 PM PDT 24 |
137314487 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3664241111 |
|
|
Apr 18 01:54:58 PM PDT 24 |
Apr 18 01:55:01 PM PDT 24 |
1264982059 ps |
| T976 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2114544108 |
|
|
Apr 18 01:55:05 PM PDT 24 |
Apr 18 01:55:07 PM PDT 24 |
85771314 ps |
| T977 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2165363661 |
|
|
Apr 18 01:55:27 PM PDT 24 |
Apr 18 01:55:29 PM PDT 24 |
33860512 ps |
| T978 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.596994387 |
|
|
Apr 18 01:55:30 PM PDT 24 |
Apr 18 01:55:32 PM PDT 24 |
15121743 ps |
| T979 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.29700552 |
|
|
Apr 18 01:55:17 PM PDT 24 |
Apr 18 01:55:20 PM PDT 24 |
1640711081 ps |
| T980 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.216692667 |
|
|
Apr 18 01:55:26 PM PDT 24 |
Apr 18 01:55:27 PM PDT 24 |
34868736 ps |
| T133 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1401813949 |
|
|
Apr 18 01:54:58 PM PDT 24 |
Apr 18 01:55:00 PM PDT 24 |
154003894 ps |
| T981 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1042087966 |
|
|
Apr 18 01:55:05 PM PDT 24 |
Apr 18 01:55:06 PM PDT 24 |
37172733 ps |
| T982 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3579231961 |
|
|
Apr 18 01:55:20 PM PDT 24 |
Apr 18 01:55:22 PM PDT 24 |
55967395 ps |
| T983 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1696591906 |
|
|
Apr 18 01:55:27 PM PDT 24 |
Apr 18 01:55:30 PM PDT 24 |
28778621 ps |
| T984 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.3360680281 |
|
|
Apr 18 01:55:29 PM PDT 24 |
Apr 18 01:55:34 PM PDT 24 |
42273140 ps |
| T985 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.4262759257 |
|
|
Apr 18 01:55:05 PM PDT 24 |
Apr 18 01:55:06 PM PDT 24 |
13690510 ps |
| T986 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.210345467 |
|
|
Apr 18 01:55:10 PM PDT 24 |
Apr 18 01:55:13 PM PDT 24 |
239909298 ps |
| T987 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1027874012 |
|
|
Apr 18 01:55:07 PM PDT 24 |
Apr 18 01:55:08 PM PDT 24 |
75358678 ps |
| T126 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3422626604 |
|
|
Apr 18 01:55:22 PM PDT 24 |
Apr 18 01:55:25 PM PDT 24 |
751785968 ps |
| T988 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.407662999 |
|
|
Apr 18 01:55:10 PM PDT 24 |
Apr 18 01:55:12 PM PDT 24 |
153785279 ps |
| T989 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.1308168989 |
|
|
Apr 18 01:55:14 PM PDT 24 |
Apr 18 01:55:18 PM PDT 24 |
514347505 ps |
| T990 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3569570565 |
|
|
Apr 18 01:55:33 PM PDT 24 |
Apr 18 01:55:36 PM PDT 24 |
649400551 ps |
| T991 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.1325891759 |
|
|
Apr 18 01:55:29 PM PDT 24 |
Apr 18 01:55:31 PM PDT 24 |
63409790 ps |
| T992 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3148898418 |
|
|
Apr 18 01:55:27 PM PDT 24 |
Apr 18 01:55:28 PM PDT 24 |
23801700 ps |
| T993 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3731448959 |
|
|
Apr 18 01:55:21 PM PDT 24 |
Apr 18 01:55:26 PM PDT 24 |
178176831 ps |
| T994 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2610004581 |
|
|
Apr 18 01:55:29 PM PDT 24 |
Apr 18 01:55:32 PM PDT 24 |
293132699 ps |
| T995 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2970321557 |
|
|
Apr 18 01:55:06 PM PDT 24 |
Apr 18 01:55:10 PM PDT 24 |
644560679 ps |
| T996 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1954279155 |
|
|
Apr 18 01:55:09 PM PDT 24 |
Apr 18 01:55:12 PM PDT 24 |
612677496 ps |
| T997 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.4006006894 |
|
|
Apr 18 01:54:57 PM PDT 24 |
Apr 18 01:54:59 PM PDT 24 |
37348397 ps |
| T998 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3474003231 |
|
|
Apr 18 01:55:05 PM PDT 24 |
Apr 18 01:55:06 PM PDT 24 |
12054601 ps |
| T999 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.3078998821 |
|
|
Apr 18 01:55:19 PM PDT 24 |
Apr 18 01:55:21 PM PDT 24 |
141747724 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2674015823 |
|
|
Apr 18 01:55:15 PM PDT 24 |
Apr 18 01:55:16 PM PDT 24 |
11314556 ps |
| T1001 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2107469050 |
|
|
Apr 18 01:55:26 PM PDT 24 |
Apr 18 01:55:27 PM PDT 24 |
39261960 ps |
| T88 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1309823904 |
|
|
Apr 18 01:54:58 PM PDT 24 |
Apr 18 01:55:00 PM PDT 24 |
38263093 ps |
| T134 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3156665247 |
|
|
Apr 18 01:55:30 PM PDT 24 |
Apr 18 01:55:33 PM PDT 24 |
348147341 ps |
| T1002 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.98073230 |
|
|
Apr 18 01:55:14 PM PDT 24 |
Apr 18 01:55:15 PM PDT 24 |
125033671 ps |